diff options
Diffstat (limited to 'arch/arm/boot/dts/microchip/at91-natte.dtsi')
-rw-r--r-- | arch/arm/boot/dts/microchip/at91-natte.dtsi | 244 |
1 files changed, 244 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/microchip/at91-natte.dtsi b/arch/arm/boot/dts/microchip/at91-natte.dtsi new file mode 100644 index 0000000000..49f0a0c46c --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-natte.dtsi @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * at91-natte.dts - Device Tree include file for the Natte board + * + * Copyright (C) 2017 Axentia Technologies AB + * + * Author: Peter Rosin <peda@axentia.se> + */ + +/ { + mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>, + <&ioexp 1 GPIO_ACTIVE_HIGH>, + <&ioexp 2 GPIO_ACTIVE_HIGH>; + }; + + batntc-mux { + compatible = "io-channel-mux"; + io-channels = <&adc 5>; + io-channel-names = "parent"; + mux-controls = <&mux>; + + channels = + "batntc0", "batntc1", "batntc2", "batntc3", + "batntc4", "batntc5", "batntc6", "batntc7"; + }; + + batv-mux { + compatible = "io-channel-mux"; + io-channels = <&adc 6>; + io-channel-names = "parent"; + mux-controls = <&mux>; + + channels = + "batv0", "batv1", "batv2", "batv3", + "batv4", "batv5", "batv6", "batv7"; + }; + + iout-mux { + compatible = "io-channel-mux"; + io-channels = <&adc 7>; + io-channel-names = "parent"; + mux-controls = <&mux>; + + channels = + "iout0", "iout1", "iout2", "iout3", + "iout4", "iout5", "iout6", "iout7"; + }; + + i2c-mux { + compatible = "i2c-mux"; + mux-locked; + i2c-parent = <&i2c0>; + mux-controls = <&mux>; + + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + + charger@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + + ti,charge-current = <2000>; + ti,charge-voltage = <16800>; + + poll-interval = <20000>; + }; + }; + }; +}; + +&i2c0 { + status = "okay"; + + ioexp: ioexp@20 { + #gpio-cells = <2>; + compatible = "semtech,sx1502q"; + reg = <0x20>; + + gpio-controller; + ngpios = <8>; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio3_cfg_pins>; + + gpio3_cfg_pins: gpio3_cfg { + pins = "gpio3"; + bias-pull-up; + }; + }; + + adc: adc@48 { + compatible = "ti,ads1015"; + reg = <0x48>; + #io-channel-cells = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + channel@5 { + reg = <5>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + channel@6 { + reg = <6>; + ti,gain = <1>; + ti,datarate = <4>; + }; + + channel@7 { + reg = <7>; + ti,gain = <3>; + ti,datarate = <4>; + }; + }; +}; |