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-rw-r--r--arch/arm/boot/dts/rockchip/rk3128.dtsi185
1 files changed, 185 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index 01edf244dd..e2264c40b9 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rk3128-power.h>
/ {
compatible = "rockchip,rk3128";
@@ -15,6 +16,20 @@
#address-cells = <1>;
#size-cells = <1>;
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
@@ -100,6 +115,27 @@
};
};
+ gpu_opp_table: opp-table-1 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <975000 975000 1250000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1050000 1050000 1250000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1150000 1150000 1250000>;
+ };
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <1250000 1250000 1250000>;
+ };
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
@@ -130,9 +166,119 @@
};
};
+ gpu: gpu@10090000 {
+ compatible = "rockchip,rk3128-mali", "arm,mali-400";
+ reg = <0x10090000 0x10000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1";
+ clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
+ clock-names = "bus", "core";
+ operating-points-v2 = <&gpu_opp_table>;
+ resets = <&cru SRST_GPU>;
+ power-domains = <&power RK3128_PD_GPU>;
+ status = "disabled";
+ };
+
pmu: syscon@100a0000 {
compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
reg = <0x100a0000 0x1000>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3128-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3128_PD_VIO {
+ reg = <RK3128_PD_VIO>;
+ clocks = <&cru ACLK_CIF>,
+ <&cru HCLK_CIF>,
+ <&cru DCLK_EBC>,
+ <&cru HCLK_EBC>,
+ <&cru ACLK_IEP>,
+ <&cru HCLK_IEP>,
+ <&cru ACLK_LCDC0>,
+ <&cru HCLK_LCDC0>,
+ <&cru PCLK_MIPI>,
+ <&cru ACLK_RGA>,
+ <&cru HCLK_RGA>,
+ <&cru ACLK_VIO0>,
+ <&cru ACLK_VIO1>,
+ <&cru HCLK_VIO>,
+ <&cru HCLK_VIO_H2P>,
+ <&cru DCLK_VOP>,
+ <&cru SCLK_VOP>;
+ pm_qos = <&qos_ebc>,
+ <&qos_iep>,
+ <&qos_lcdc>,
+ <&qos_rga>,
+ <&qos_vip>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3128_PD_VIDEO {
+ reg = <RK3128_PD_VIDEO>;
+ clocks = <&cru ACLK_VDPU>,
+ <&cru HCLK_VDPU>,
+ <&cru ACLK_VEPU>,
+ <&cru HCLK_VEPU>,
+ <&cru SCLK_HEVC_CORE>;
+ pm_qos = <&qos_vpu>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3128_PD_GPU {
+ reg = <RK3128_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ qos_gpu: qos@1012d000 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012d000 0x20>;
+ };
+
+ qos_vpu: qos@1012e000 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012e000 0x20>;
+ };
+
+ qos_rga: qos@1012f000 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012f000 0x20>;
+ };
+
+ qos_ebc: qos@1012f080 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012f080 0x20>;
+ };
+
+ qos_iep: qos@1012f100 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012f100 0x20>;
+ };
+
+ qos_lcdc: qos@1012f180 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012f180 0x20>;
+ };
+
+ qos_vip: qos@1012f200 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012f200 0x20>;
};
gic: interrupt-controller@10139000 {
@@ -154,6 +300,9 @@
clocks = <&cru HCLK_OTG>;
clock-names = "otg";
dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <280>;
+ g-tx-fifo-size = <256 128 128 64 32 16>;
phys = <&usb2phy_otg>;
phy-names = "usb2-phy";
status = "disabled";
@@ -163,6 +312,7 @@
compatible = "generic-ehci";
reg = <0x101c0000 0x20000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST2>;
phys = <&usb2phy_host>;
phy-names = "usb";
status = "disabled";
@@ -172,6 +322,7 @@
compatible = "generic-ohci";
reg = <0x101e0000 0x20000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST2>;
phys = <&usb2phy_host>;
phy-names = "usb";
status = "disabled";
@@ -261,6 +412,8 @@
clocks = <&cru SCLK_OTGPHY0>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy";
+ assigned-clocks = <&cru SCLK_USB480M>;
+ assigned-clock-parents = <&usb2phy>;
#clock-cells = <0>;
status = "disabled";
@@ -518,6 +671,34 @@
#dma-cells = <1>;
};
+ gmac: ethernet@2008c000 {
+ compatible = "rockchip,rk3128-gmac";
+ reg = <0x2008c000 0x4000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ clocks = <&cru SCLK_MAC>,
+ <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
+ <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
+ <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
+ clock-names = "stmmaceth",
+ "mac_clk_rx", "mac_clk_tx",
+ "clk_mac_ref", "clk_mac_refout",
+ "aclk_mac", "pclk_mac";
+ resets = <&cru SRST_GMAC>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&grf>;
+ rx-fifo-depth = <4096>;
+ tx-fifo-depth = <2048>;
+ status = "disabled";
+
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3128-pinctrl";
rockchip,grf = <&grf>;
@@ -843,6 +1024,10 @@
rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
};
+ sdmmc_det: sdmmc-det {
+ rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
+ };
+
sdmmc_wp: sdmmc-wp {
rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
};
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-03 07:00:29 +0000