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+# SPDX-License-Identifier: GPL-2.0-only
+menuconfig ARCH_AT91
+ bool "AT91/Microchip SoCs"
+ depends on (CPU_LITTLE_ENDIAN && (ARCH_MULTI_V4T || ARCH_MULTI_V5)) || \
+ ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
+ select ARM_CPU_SUSPEND if PM && ARCH_MULTI_V7
+ select COMMON_CLK_AT91
+ select GPIOLIB
+ select PINCTRL
+ select SOC_BUS
+
+if ARCH_AT91
+config SOC_SAMV7
+ bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M
+ select COMMON_CLK_AT91
+ select PINCTRL_AT91
+ help
+ Select this if you are using an SoC from Microchip's SAME7, SAMS7 or SAMV7
+ families.
+
+config SOC_SAMA5D2
+ bool "SAMA5D2 family"
+ depends on ARCH_MULTI_V7
+ select SOC_SAMA5
+ select CACHE_L2X0
+ select HAVE_AT91_UTMI
+ select HAVE_AT91_USB_CLK
+ select HAVE_AT91_H32MX
+ select HAVE_AT91_GENERATED_CLK
+ select HAVE_AT91_AUDIO_PLL
+ select HAVE_AT91_I2S_MUX_CLK
+ select PINCTRL_AT91PIO4
+ help
+ Select this if ou are using one of Microchip's SAMA5D2 family SoC.
+
+config SOC_SAMA5D3
+ bool "SAMA5D3 family"
+ depends on ARCH_MULTI_V7
+ select SOC_SAMA5
+ select HAVE_AT91_UTMI
+ select HAVE_AT91_SMD
+ select HAVE_AT91_USB_CLK
+ select PINCTRL_AT91
+ help
+ Select this if you are using one of Microchip's SAMA5D3 family SoC.
+ This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36.
+
+config SOC_SAMA5D4
+ bool "SAMA5D4 family"
+ depends on ARCH_MULTI_V7
+ select SOC_SAMA5
+ select CACHE_L2X0
+ select HAVE_AT91_UTMI
+ select HAVE_AT91_SMD
+ select HAVE_AT91_USB_CLK
+ select HAVE_AT91_H32MX
+ select PINCTRL_AT91
+ help
+ Select this if you are using one of Microchip's SAMA5D4 family SoC.
+
+config SOC_SAMA7G5
+ bool "SAMA7G5 family"
+ depends on ARCH_MULTI_V7
+ select HAVE_AT91_GENERATED_CLK
+ select HAVE_AT91_SAM9X60_PLL
+ select HAVE_AT91_UTMI
+ select PM_OPP
+ select SOC_SAMA7
+ help
+ Select this if you are using one of Microchip's SAMA7G5 family SoC.
+
+config SOC_LAN966
+ bool "ARMv7 based Microchip LAN966 SoC family"
+ depends on ARCH_MULTI_V7
+ select DW_APB_TIMER_OF
+ select ARM_GIC
+ select MEMORY
+ help
+ This enables support for ARMv7 based Microchip LAN966 SoC family.
+
+config SOC_AT91RM9200
+ bool "AT91RM9200"
+ depends on ARCH_MULTI_V4T
+ select ATMEL_AIC_IRQ
+ select ATMEL_PM if PM
+ select ATMEL_ST
+ select CPU_ARM920T
+ select HAVE_AT91_USB_CLK
+ select PINCTRL_AT91
+ select SOC_SAM_V4_V5
+ select SRAM if PM
+ help
+ Select this if you are using Microchip's AT91RM9200 SoC.
+
+config SOC_AT91SAM9
+ bool "AT91SAM9"
+ depends on ARCH_MULTI_V5
+ select ATMEL_AIC_IRQ
+ select ATMEL_PM if PM
+ select CPU_ARM926T
+ select HAVE_AT91_SMD
+ select HAVE_AT91_USB_CLK
+ select HAVE_AT91_UTMI
+ select HAVE_FB_ATMEL
+ select MEMORY
+ select PINCTRL_AT91
+ select SOC_SAM_V4_V5
+ select SRAM if PM
+ help
+ Select this if you are using one of those Microchip SoC:
+ AT91SAM9260
+ AT91SAM9261
+ AT91SAM9263
+ AT91SAM9G15
+ AT91SAM9G20
+ AT91SAM9G25
+ AT91SAM9G35
+ AT91SAM9G45
+ AT91SAM9G46
+ AT91SAM9M10
+ AT91SAM9M11
+ AT91SAM9N12
+ AT91SAM9RL
+ AT91SAM9X25
+ AT91SAM9X35
+ AT91SAM9XE
+
+config SOC_SAM9X60
+ bool "SAM9X60"
+ depends on ARCH_MULTI_V5
+ select ATMEL_AIC5_IRQ
+ select ATMEL_PM if PM
+ select CPU_ARM926T
+ select HAVE_AT91_USB_CLK
+ select HAVE_AT91_GENERATED_CLK
+ select HAVE_AT91_SAM9X60_PLL
+ select MEMORY
+ select PINCTRL_AT91
+ select SOC_SAM_V4_V5
+ select SRAM if PM
+ help
+ Select this if you are using Microchip's SAM9X60 SoC
+
+comment "Clocksource driver selection"
+
+config ATMEL_CLOCKSOURCE_PIT
+ bool "Periodic Interval Timer (PIT) support"
+ depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
+ default SOC_AT91SAM9 || SOC_SAMA5
+ select ATMEL_PIT
+ help
+ Select this to get a clocksource based on the Atmel Periodic Interval
+ Timer. It has a relatively low resolution and the TC Block clocksource
+ should be preferred.
+
+config ATMEL_CLOCKSOURCE_TCB
+ bool "Timer Counter Blocks (TCB) support"
+ default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
+ select ATMEL_TCB_CLKSRC
+ help
+ Select this to get a high precision clocksource based on a
+ TC block with a 5+ MHz base clock rate.
+ On platforms with 16-bit counters, two timer channels are combined
+ to make a single 32-bit timer.
+ It can also be used as a clock event device supporting oneshot mode.
+
+config MICROCHIP_CLOCKSOURCE_PIT64B
+ bool "64-bit Periodic Interval Timer (PIT64B) support"
+ default SOC_SAM9X60 || SOC_SAMA7
+ select MICROCHIP_PIT64B
+ help
+ Select this to get a high resolution clockevent (SAM9X60) or
+ clocksource and clockevent (SAMA7G5) based on Microchip 64-bit
+ Periodic Interval Timer.
+
+config HAVE_AT91_UTMI
+ bool
+
+config HAVE_AT91_USB_CLK
+ bool
+
+config COMMON_CLK_AT91
+ bool
+ select MFD_SYSCON
+
+config HAVE_AT91_SMD
+ bool
+
+config HAVE_AT91_H32MX
+ bool
+
+config HAVE_AT91_GENERATED_CLK
+ bool
+
+config HAVE_AT91_AUDIO_PLL
+ bool
+
+config HAVE_AT91_I2S_MUX_CLK
+ bool
+
+config HAVE_AT91_SAM9X60_PLL
+ bool
+
+config SOC_SAM_V4_V5
+ bool
+
+config SOC_SAM_V7
+ bool
+
+config SOC_SAMA5
+ bool
+ select ATMEL_AIC5_IRQ
+ select ATMEL_PM if PM
+ select MEMORY
+ select SOC_SAM_V7
+ select SRAM if PM
+
+config ATMEL_PM
+ bool
+
+config ATMEL_SECURE_PM
+ bool "Atmel Secure PM support"
+ depends on SOC_SAMA5D2 && ATMEL_PM
+ select ARM_PSCI
+ help
+ When running under a TEE, the suspend mode must be requested to be set
+ at TEE level. When enable, this option will use secure monitor calls
+ to set the suspend level. PSCI is then used to enter suspend.
+
+config SOC_SAMA7
+ bool
+ select ARM_GIC
+ select ATMEL_PM if PM
+ select MEMORY
+ select SOC_SAM_V7
+ select SRAM if PM
+endif