diff options
Diffstat (limited to 'arch/arm/mach-davinci')
26 files changed, 3473 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig new file mode 100644 index 0000000000..2a8a9fe465 --- /dev/null +++ b/arch/arm/mach-davinci/Kconfig @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0 + +menuconfig ARCH_DAVINCI + bool "TI DaVinci" + depends on ARCH_MULTI_V5 + depends on CPU_LITTLE_ENDIAN + select CPU_ARM926T + select DAVINCI_TIMER + select ZONE_DMA + select PM_GENERIC_DOMAINS if PM + select PM_GENERIC_DOMAINS_OF if PM && OF + select REGMAP_MMIO + select RESET_CONTROLLER + select PINCTRL + select PINCTRL_SINGLE + +if ARCH_DAVINCI + +comment "DaVinci Core Type" + +config ARCH_DAVINCI_DA830 + bool "DA830/OMAP-L137/AM17x based system" + select ARCH_DAVINCI_DA8XX + # needed on silicon revs 1.0, 1.1: + select CPU_DCACHE_WRITETHROUGH if !CPU_DCACHE_DISABLE + select DAVINCI_CP_INTC + +config ARCH_DAVINCI_DA850 + bool "DA850/OMAP-L138/AM18x based system" + select DAVINCI_CP_INTC + +config ARCH_DAVINCI_DA8XX + bool + +config DAVINCI_MUX + bool "DAVINCI multiplexing support" + depends on ARCH_DAVINCI + default y + help + Pin multiplexing support for DAVINCI boards. If your bootloader + sets the multiplexing correctly, say N. Otherwise, or if unsure, + say Y. + +config DAVINCI_MUX_DEBUG + bool "Multiplexing debug output" + depends on DAVINCI_MUX + help + Makes the multiplexing functions print out a lot of debug info. + This is useful if you want to find out the correct values of the + multiplexing registers. + +config DAVINCI_MUX_WARNINGS + bool "Warn about pins the bootloader didn't set up" + depends on DAVINCI_MUX + help + Choose Y here to warn whenever driver initialization logic needs + to change the pin multiplexing setup. When there are no warnings + printed, it's safe to deselect DAVINCI_MUX for your product. + +endif diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile new file mode 100644 index 0000000000..450883ea0e --- /dev/null +++ b/arch/arm/mach-davinci/Makefile @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the linux kernel. +# +# +# +# Common objects +obj-y := common.o sram.o devices-da8xx.o + +obj-$(CONFIG_DAVINCI_MUX) += mux.o + +# Chip specific +obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o +obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o pdata-quirks.o + +obj-y += da8xx-dt.o + +# Power Management +obj-$(CONFIG_CPU_IDLE) += cpuidle.o +obj-$(CONFIG_HAVE_CLK) += pm_domain.o +ifeq ($(CONFIG_SUSPEND),y) +obj-$(CONFIG_ARCH_DAVINCI_DA850) += pm.o sleep.o +endif diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h new file mode 100644 index 0000000000..54f5663b08 --- /dev/null +++ b/arch/arm/mach-davinci/clock.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * TI DaVinci clock definitions + * + * Copyright (C) 2006-2007 Texas Instruments. + * Copyright (C) 2008-2009 Deep Root Systems, LLC + */ + +#ifndef __ARCH_ARM_DAVINCI_CLOCK_H +#define __ARCH_ARM_DAVINCI_CLOCK_H + +/* PLL/Reset register offsets */ +#define PLLCTL 0x100 +#define PLLCTL_PLLEN BIT(0) +#define PLLCTL_PLLPWRDN BIT(1) +#define PLLCTL_PLLRST BIT(3) +#define PLLCTL_PLLDIS BIT(4) +#define PLLCTL_PLLENSRC BIT(5) +#define PLLCTL_CLKMODE BIT(8) + +#define PLLM 0x110 +#define PLLM_PLLM_MASK 0xff + +#define PREDIV 0x114 +#define PLLDIV1 0x118 +#define PLLDIV2 0x11c +#define PLLDIV3 0x120 +#define POSTDIV 0x128 +#define BPDIV 0x12c +#define PLLCMD 0x138 +#define PLLSTAT 0x13c +#define PLLALNCTL 0x140 +#define PLLDCHANGE 0x144 +#define PLLCKEN 0x148 +#define PLLCKSTAT 0x14c +#define PLLSYSTAT 0x150 +#define PLLDIV4 0x160 +#define PLLDIV5 0x164 +#define PLLDIV6 0x168 +#define PLLDIV7 0x16c +#define PLLDIV8 0x170 +#define PLLDIV9 0x174 +#define PLLDIV_EN BIT(15) +#define PLLDIV_RATIO_MASK 0x1f + +/* + * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN + * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us + * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input + * is ~25MHz. Units are micro seconds. + */ +#define PLL_BYPASS_TIME 1 +/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */ +#define PLL_RESET_TIME 1 +/* + * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4 + * Units are micro seconds. + */ +#define PLL_LOCK_TIME 20 + +#endif diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c new file mode 100644 index 0000000000..7bc7018688 --- /dev/null +++ b/arch/arm/mach-davinci/common.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Code commons to all DaVinci SoCs. + * + * Author: Mark A. Greer <mgreer@mvista.com> + * + * 2009 (c) MontaVista Software, Inc. + */ +#include <linux/module.h> +#include <linux/io.h> +#include <linux/etherdevice.h> +#include <linux/davinci_emac.h> +#include <linux/dma-mapping.h> +#include <linux/platform_data/davinci-cpufreq.h> + +#include <asm/tlb.h> +#include <asm/mach/map.h> + +#include "common.h" +#include "cputype.h" + +struct davinci_soc_info davinci_soc_info; +EXPORT_SYMBOL(davinci_soc_info); + +static int __init davinci_init_id(struct davinci_soc_info *soc_info) +{ + int i; + struct davinci_id *dip; + u8 variant; + u16 part_no; + void __iomem *base; + + base = ioremap(soc_info->jtag_id_reg, SZ_4K); + if (!base) { + pr_err("Unable to map JTAG ID register\n"); + return -ENOMEM; + } + + soc_info->jtag_id = __raw_readl(base); + iounmap(base); + + variant = (soc_info->jtag_id & 0xf0000000) >> 28; + part_no = (soc_info->jtag_id & 0x0ffff000) >> 12; + + for (i = 0, dip = soc_info->ids; i < soc_info->ids_num; + i++, dip++) + /* Don't care about the manufacturer right now */ + if ((dip->part_no == part_no) && (dip->variant == variant)) { + soc_info->cpu_id = dip->cpu_id; + pr_info("DaVinci %s variant 0x%x\n", dip->name, + dip->variant); + return 0; + } + + pr_err("Unknown DaVinci JTAG ID 0x%x\n", soc_info->jtag_id); + return -EINVAL; +} + +void __init davinci_common_init(const struct davinci_soc_info *soc_info) +{ + int ret; + + if (!soc_info) { + ret = -EINVAL; + goto err; + } + + memcpy(&davinci_soc_info, soc_info, sizeof(struct davinci_soc_info)); + + if (davinci_soc_info.io_desc && (davinci_soc_info.io_desc_num > 0)) + iotable_init(davinci_soc_info.io_desc, + davinci_soc_info.io_desc_num); + + /* + * Normally devicemaps_init() would flush caches and tlb after + * mdesc->map_io(), but we must also do it here because of the CPU + * revision check below. + */ + local_flush_tlb_all(); + flush_cache_all(); + + /* + * We want to check CPU revision early for cpu_is_xxxx() macros. + * IO space mapping must be initialized before we can do that. + */ + ret = davinci_init_id(&davinci_soc_info); + if (ret < 0) + goto err; + + + return; + +err: + panic("davinci_common_init: SoC Initialization failed\n"); +} + +void __init davinci_init_late(void) +{ + davinci_cpufreq_init(); +} diff --git a/arch/arm/mach-davinci/common.h b/arch/arm/mach-davinci/common.h new file mode 100644 index 0000000000..8aa6d4fc3f --- /dev/null +++ b/arch/arm/mach-davinci/common.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Header for code common to all DaVinci machines. + * + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. + */ + +#ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H +#define __ARCH_ARM_MACH_DAVINCI_COMMON_H + +#include <linux/clk.h> +#include <linux/compiler.h> +#include <linux/types.h> +#include <linux/reboot.h> + +#include <asm/irq.h> + +#define DAVINCI_INTC_START NR_IRQS +#define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum)) + +struct davinci_gpio_controller; + +/* + * SoC info passed into common davinci modules. + * + * Base addresses in this structure should be physical and not virtual. + * Modules that take such base addresses, should internally ioremap() them to + * use. + */ +struct davinci_soc_info { + struct map_desc *io_desc; + unsigned long io_desc_num; + u32 cpu_id; + u32 jtag_id; + u32 jtag_id_reg; + struct davinci_id *ids; + unsigned long ids_num; + u32 pinmux_base; + const struct mux_config *pinmux_pins; + unsigned long pinmux_pins_num; + int gpio_type; + u32 gpio_base; + unsigned gpio_num; + unsigned gpio_irq; + unsigned gpio_unbanked; + dma_addr_t sram_dma; + unsigned sram_len; +}; + +extern struct davinci_soc_info davinci_soc_info; + +extern void davinci_common_init(const struct davinci_soc_info *soc_info); +extern void davinci_init_ide(void); +void davinci_init_late(void); + +#ifdef CONFIG_SUSPEND +int davinci_pm_init(void); +#else +static inline int davinci_pm_init(void) { return 0; } +#endif + +void __init pdata_quirks_init(void); + +#define SRAM_SIZE SZ_128K + +#endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */ diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c new file mode 100644 index 0000000000..78a1575c38 --- /dev/null +++ b/arch/arm/mach-davinci/cpuidle.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * CPU idle for DaVinci SoCs + * + * Copyright (C) 2009 Texas Instruments Incorporated. https://www.ti.com/ + * + * Derived from Marvell Kirkwood CPU idle code + * (arch/arm/mach-kirkwood/cpuidle.c) + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/cpuidle.h> +#include <linux/io.h> +#include <linux/export.h> +#include <asm/cpuidle.h> + +#include "cpuidle.h" +#include "ddr2.h" + +#define DAVINCI_CPUIDLE_MAX_STATES 2 + +static void __iomem *ddr2_reg_base; +static bool ddr2_pdown; + +static void davinci_save_ddr_power(int enter, bool pdown) +{ + u32 val; + + val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET); + + if (enter) { + if (pdown) + val |= DDR2_SRPD_BIT; + else + val &= ~DDR2_SRPD_BIT; + val |= DDR2_LPMODEN_BIT; + } else { + val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT); + } + + __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET); +} + +/* Actual code that puts the SoC in different idle states */ +static __cpuidle int davinci_enter_idle(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + davinci_save_ddr_power(1, ddr2_pdown); + cpu_do_idle(); + davinci_save_ddr_power(0, ddr2_pdown); + + return index; +} + +static struct cpuidle_driver davinci_idle_driver = { + .name = "cpuidle-davinci", + .owner = THIS_MODULE, + .states[0] = ARM_CPUIDLE_WFI_STATE, + .states[1] = { + .enter = davinci_enter_idle, + .exit_latency = 10, + .target_residency = 10000, + .name = "DDR SR", + .desc = "WFI and DDR Self Refresh", + }, + .state_count = DAVINCI_CPUIDLE_MAX_STATES, +}; + +static int __init davinci_cpuidle_probe(struct platform_device *pdev) +{ + struct davinci_cpuidle_config *pdata = pdev->dev.platform_data; + + if (!pdata) { + dev_err(&pdev->dev, "cannot get platform data\n"); + return -ENOENT; + } + + ddr2_reg_base = pdata->ddr2_ctlr_base; + + ddr2_pdown = pdata->ddr2_pdown; + + return cpuidle_register(&davinci_idle_driver, NULL); +} + +static struct platform_driver davinci_cpuidle_driver = { + .driver = { + .name = "cpuidle-davinci", + }, +}; + +static int __init davinci_cpuidle_init(void) +{ + return platform_driver_probe(&davinci_cpuidle_driver, + davinci_cpuidle_probe); +} +device_initcall(davinci_cpuidle_init); + diff --git a/arch/arm/mach-davinci/cpuidle.h b/arch/arm/mach-davinci/cpuidle.h new file mode 100644 index 0000000000..976d430735 --- /dev/null +++ b/arch/arm/mach-davinci/cpuidle.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * TI DaVinci cpuidle platform support + * + * 2009 (C) Texas Instruments, Inc. https://www.ti.com/ + */ +#ifndef _MACH_DAVINCI_CPUIDLE_H +#define _MACH_DAVINCI_CPUIDLE_H + +struct davinci_cpuidle_config { + u32 ddr2_pdown; + void __iomem *ddr2_ctlr_base; +}; + +#endif diff --git a/arch/arm/mach-davinci/cputype.h b/arch/arm/mach-davinci/cputype.h new file mode 100644 index 0000000000..148a738391 --- /dev/null +++ b/arch/arm/mach-davinci/cputype.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * DaVinci CPU type detection + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * Defines the cpu_is_*() macros for runtime detection of DaVinci + * device type. In addition, if support for a given device is not + * compiled in to the kernel, the macros return 0 so that + * resulting code can be optimized out. + * + * 2009 (c) Deep Root Systems, LLC. + */ +#ifndef _ASM_ARCH_CPU_H +#define _ASM_ARCH_CPU_H + +#include "common.h" + +struct davinci_id { + u8 variant; /* JTAG ID bits 31:28 */ + u16 part_no; /* JTAG ID bits 27:12 */ + u16 manufacturer; /* JTAG ID bits 11:1 */ + u32 cpu_id; + char *name; +}; + +/* Can use lower 16 bits of cpu id for a variant when required */ +#define DAVINCI_CPU_ID_DA830 0x08300000 +#define DAVINCI_CPU_ID_DA850 0x08500000 + +#endif diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c new file mode 100644 index 0000000000..2e497745b6 --- /dev/null +++ b/arch/arm/mach-davinci/da830.c @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * TI DA830/OMAP L137 chip specific setup + * + * Author: Mark A. Greer <mgreer@mvista.com> + * + * 2009 (c) MontaVista Software, Inc. + */ +#include <linux/clk-provider.h> +#include <linux/clk/davinci.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/irqchip/irq-davinci-cp-intc.h> + +#include <clocksource/timer-davinci.h> + +#include <asm/mach/map.h> + +#include "common.h" +#include "cputype.h" +#include "da8xx.h" +#include "irqs.h" +#include "mux.h" + +/* Offsets of the 8 compare registers on the da830 */ +#define DA830_CMP12_0 0x60 +#define DA830_CMP12_1 0x64 +#define DA830_CMP12_2 0x68 +#define DA830_CMP12_3 0x6c +#define DA830_CMP12_4 0x70 +#define DA830_CMP12_5 0x74 +#define DA830_CMP12_6 0x78 +#define DA830_CMP12_7 0x7c + +#define DA830_REF_FREQ 24000000 + +/* + * Device specific mux setup + * + * soc description mux mode mode mux dbg + * reg offset mask mode + */ +static const struct mux_config da830_pins[] = { +#ifdef CONFIG_DAVINCI_MUX + MUX_CFG(DA830, GPIO7_14, 0, 0, 0xf, 1, false) + MUX_CFG(DA830, RTCK, 0, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_15, 0, 4, 0xf, 1, false) + MUX_CFG(DA830, EMU_0, 0, 4, 0xf, 8, false) + MUX_CFG(DA830, EMB_SDCKE, 0, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_CLK_GLUE, 0, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_CLK, 0, 12, 0xf, 2, false) + MUX_CFG(DA830, NEMB_CS_0, 0, 16, 0xf, 1, false) + MUX_CFG(DA830, NEMB_CAS, 0, 20, 0xf, 1, false) + MUX_CFG(DA830, NEMB_RAS, 0, 24, 0xf, 1, false) + MUX_CFG(DA830, NEMB_WE, 0, 28, 0xf, 1, false) + MUX_CFG(DA830, EMB_BA_1, 1, 0, 0xf, 1, false) + MUX_CFG(DA830, EMB_BA_0, 1, 4, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_0, 1, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_1, 1, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_2, 1, 16, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_3, 1, 20, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_4, 1, 24, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_5, 1, 28, 0xf, 1, false) + MUX_CFG(DA830, GPIO7_0, 1, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_1, 1, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_2, 1, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_3, 1, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_4, 1, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_5, 1, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_6, 1, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_7, 1, 28, 0xf, 8, false) + MUX_CFG(DA830, EMB_A_6, 2, 0, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_7, 2, 4, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_8, 2, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_9, 2, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_10, 2, 16, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_11, 2, 20, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_12, 2, 24, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_31, 2, 28, 0xf, 1, false) + MUX_CFG(DA830, GPIO7_8, 2, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_9, 2, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_10, 2, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_11, 2, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_12, 2, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_13, 2, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_13, 2, 24, 0xf, 8, false) + MUX_CFG(DA830, EMB_D_30, 3, 0, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_29, 3, 4, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_28, 3, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_27, 3, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_26, 3, 16, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_25, 3, 20, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_24, 3, 24, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_23, 3, 28, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_22, 4, 0, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_21, 4, 4, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_20, 4, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_19, 4, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_18, 4, 16, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_17, 4, 20, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_16, 4, 24, 0xf, 1, false) + MUX_CFG(DA830, NEMB_WE_DQM_3, 4, 28, 0xf, 1, false) + MUX_CFG(DA830, NEMB_WE_DQM_2, 5, 0, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_0, 5, 4, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_1, 5, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_2, 5, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_3, 5, 16, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_4, 5, 20, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_5, 5, 24, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_6, 5, 28, 0xf, 1, false) + MUX_CFG(DA830, GPIO6_0, 5, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_1, 5, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_2, 5, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_3, 5, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_4, 5, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_5, 5, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_6, 5, 28, 0xf, 8, false) + MUX_CFG(DA830, EMB_D_7, 6, 0, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_8, 6, 4, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_9, 6, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_10, 6, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_11, 6, 16, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_12, 6, 20, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_13, 6, 24, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_14, 6, 28, 0xf, 1, false) + MUX_CFG(DA830, GPIO6_7, 6, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_8, 6, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_9, 6, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_10, 6, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_11, 6, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_12, 6, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_13, 6, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_14, 6, 28, 0xf, 8, false) + MUX_CFG(DA830, EMB_D_15, 7, 0, 0xf, 1, false) + MUX_CFG(DA830, NEMB_WE_DQM_1, 7, 4, 0xf, 1, false) + MUX_CFG(DA830, NEMB_WE_DQM_0, 7, 8, 0xf, 1, false) + MUX_CFG(DA830, SPI0_SOMI_0, 7, 12, 0xf, 1, false) + MUX_CFG(DA830, SPI0_SIMO_0, 7, 16, 0xf, 1, false) + MUX_CFG(DA830, SPI0_CLK, 7, 20, 0xf, 1, false) + MUX_CFG(DA830, NSPI0_ENA, 7, 24, 0xf, 1, false) + MUX_CFG(DA830, NSPI0_SCS_0, 7, 28, 0xf, 1, false) + MUX_CFG(DA830, EQEP0I, 7, 12, 0xf, 2, false) + MUX_CFG(DA830, EQEP0S, 7, 16, 0xf, 2, false) + MUX_CFG(DA830, EQEP1I, 7, 20, 0xf, 2, false) + MUX_CFG(DA830, NUART0_CTS, 7, 24, 0xf, 2, false) + MUX_CFG(DA830, NUART0_RTS, 7, 28, 0xf, 2, false) + MUX_CFG(DA830, EQEP0A, 7, 24, 0xf, 4, false) + MUX_CFG(DA830, EQEP0B, 7, 28, 0xf, 4, false) + MUX_CFG(DA830, GPIO6_15, 7, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_14, 7, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_15, 7, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_0, 7, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_1, 7, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_2, 7, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_3, 7, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_4, 7, 28, 0xf, 8, false) + MUX_CFG(DA830, SPI1_SOMI_0, 8, 0, 0xf, 1, false) + MUX_CFG(DA830, SPI1_SIMO_0, 8, 4, 0xf, 1, false) + MUX_CFG(DA830, SPI1_CLK, 8, 8, 0xf, 1, false) + MUX_CFG(DA830, UART0_RXD, 8, 12, 0xf, 1, false) + MUX_CFG(DA830, UART0_TXD, 8, 16, 0xf, 1, false) + MUX_CFG(DA830, AXR1_10, 8, 20, 0xf, 1, false) + MUX_CFG(DA830, AXR1_11, 8, 24, 0xf, 1, false) + MUX_CFG(DA830, NSPI1_ENA, 8, 28, 0xf, 1, false) + MUX_CFG(DA830, I2C1_SCL, 8, 0, 0xf, 2, false) + MUX_CFG(DA830, I2C1_SDA, 8, 4, 0xf, 2, false) + MUX_CFG(DA830, EQEP1S, 8, 8, 0xf, 2, false) + MUX_CFG(DA830, I2C0_SDA, 8, 12, 0xf, 2, false) + MUX_CFG(DA830, I2C0_SCL, 8, 16, 0xf, 2, false) + MUX_CFG(DA830, UART2_RXD, 8, 28, 0xf, 2, false) + MUX_CFG(DA830, TM64P0_IN12, 8, 12, 0xf, 4, false) + MUX_CFG(DA830, TM64P0_OUT12, 8, 16, 0xf, 4, false) + MUX_CFG(DA830, GPIO5_5, 8, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_6, 8, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_7, 8, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_8, 8, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_9, 8, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_10, 8, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_11, 8, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_12, 8, 28, 0xf, 8, false) + MUX_CFG(DA830, NSPI1_SCS_0, 9, 0, 0xf, 1, false) + MUX_CFG(DA830, USB0_DRVVBUS, 9, 4, 0xf, 1, false) + MUX_CFG(DA830, AHCLKX0, 9, 8, 0xf, 1, false) + MUX_CFG(DA830, ACLKX0, 9, 12, 0xf, 1, false) + MUX_CFG(DA830, AFSX0, 9, 16, 0xf, 1, false) + MUX_CFG(DA830, AHCLKR0, 9, 20, 0xf, 1, false) + MUX_CFG(DA830, ACLKR0, 9, 24, 0xf, 1, false) + MUX_CFG(DA830, AFSR0, 9, 28, 0xf, 1, false) + MUX_CFG(DA830, UART2_TXD, 9, 0, 0xf, 2, false) + MUX_CFG(DA830, AHCLKX2, 9, 8, 0xf, 2, false) + MUX_CFG(DA830, ECAP0_APWM0, 9, 12, 0xf, 2, false) + MUX_CFG(DA830, RMII_MHZ_50_CLK, 9, 20, 0xf, 2, false) + MUX_CFG(DA830, ECAP1_APWM1, 9, 24, 0xf, 2, false) + MUX_CFG(DA830, USB_REFCLKIN, 9, 8, 0xf, 4, false) + MUX_CFG(DA830, GPIO5_13, 9, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_15, 9, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_11, 9, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_12, 9, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_13, 9, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_14, 9, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_15, 9, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_12, 9, 28, 0xf, 8, false) + MUX_CFG(DA830, AMUTE0, 10, 0, 0xf, 1, false) + MUX_CFG(DA830, AXR0_0, 10, 4, 0xf, 1, false) + MUX_CFG(DA830, AXR0_1, 10, 8, 0xf, 1, false) + MUX_CFG(DA830, AXR0_2, 10, 12, 0xf, 1, false) + MUX_CFG(DA830, AXR0_3, 10, 16, 0xf, 1, false) + MUX_CFG(DA830, AXR0_4, 10, 20, 0xf, 1, false) + MUX_CFG(DA830, AXR0_5, 10, 24, 0xf, 1, false) + MUX_CFG(DA830, AXR0_6, 10, 28, 0xf, 1, false) + MUX_CFG(DA830, RMII_TXD_0, 10, 4, 0xf, 2, false) + MUX_CFG(DA830, RMII_TXD_1, 10, 8, 0xf, 2, false) + MUX_CFG(DA830, RMII_TXEN, 10, 12, 0xf, 2, false) + MUX_CFG(DA830, RMII_CRS_DV, 10, 16, 0xf, 2, false) + MUX_CFG(DA830, RMII_RXD_0, 10, 20, 0xf, 2, false) + MUX_CFG(DA830, RMII_RXD_1, 10, 24, 0xf, 2, false) + MUX_CFG(DA830, RMII_RXER, 10, 28, 0xf, 2, false) + MUX_CFG(DA830, AFSR2, 10, 4, 0xf, 4, false) + MUX_CFG(DA830, ACLKX2, 10, 8, 0xf, 4, false) + MUX_CFG(DA830, AXR2_3, 10, 12, 0xf, 4, false) + MUX_CFG(DA830, AXR2_2, 10, 16, 0xf, 4, false) + MUX_CFG(DA830, AXR2_1, 10, 20, 0xf, 4, false) + MUX_CFG(DA830, AFSX2, 10, 24, 0xf, 4, false) + MUX_CFG(DA830, ACLKR2, 10, 28, 0xf, 4, false) + MUX_CFG(DA830, NRESETOUT, 10, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_0, 10, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_1, 10, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_2, 10, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_3, 10, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_4, 10, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_5, 10, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_6, 10, 28, 0xf, 8, false) + MUX_CFG(DA830, AXR0_7, 11, 0, 0xf, 1, false) + MUX_CFG(DA830, AXR0_8, 11, 4, 0xf, 1, false) + MUX_CFG(DA830, UART1_RXD, 11, 8, 0xf, 1, false) + MUX_CFG(DA830, UART1_TXD, 11, 12, 0xf, 1, false) + MUX_CFG(DA830, AXR0_11, 11, 16, 0xf, 1, false) + MUX_CFG(DA830, AHCLKX1, 11, 20, 0xf, 1, false) + MUX_CFG(DA830, ACLKX1, 11, 24, 0xf, 1, false) + MUX_CFG(DA830, AFSX1, 11, 28, 0xf, 1, false) + MUX_CFG(DA830, MDIO_CLK, 11, 0, 0xf, 2, false) + MUX_CFG(DA830, MDIO_D, 11, 4, 0xf, 2, false) + MUX_CFG(DA830, AXR0_9, 11, 8, 0xf, 2, false) + MUX_CFG(DA830, AXR0_10, 11, 12, 0xf, 2, false) + MUX_CFG(DA830, EPWM0B, 11, 20, 0xf, 2, false) + MUX_CFG(DA830, EPWM0A, 11, 24, 0xf, 2, false) + MUX_CFG(DA830, EPWMSYNCI, 11, 28, 0xf, 2, false) + MUX_CFG(DA830, AXR2_0, 11, 16, 0xf, 4, false) + MUX_CFG(DA830, EPWMSYNC0, 11, 28, 0xf, 4, false) + MUX_CFG(DA830, GPIO3_7, 11, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_8, 11, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_9, 11, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_10, 11, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_11, 11, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_14, 11, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_15, 11, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_10, 11, 28, 0xf, 8, false) + MUX_CFG(DA830, AHCLKR1, 12, 0, 0xf, 1, false) + MUX_CFG(DA830, ACLKR1, 12, 4, 0xf, 1, false) + MUX_CFG(DA830, AFSR1, 12, 8, 0xf, 1, false) + MUX_CFG(DA830, AMUTE1, 12, 12, 0xf, 1, false) + MUX_CFG(DA830, AXR1_0, 12, 16, 0xf, 1, false) + MUX_CFG(DA830, AXR1_1, 12, 20, 0xf, 1, false) + MUX_CFG(DA830, AXR1_2, 12, 24, 0xf, 1, false) + MUX_CFG(DA830, AXR1_3, 12, 28, 0xf, 1, false) + MUX_CFG(DA830, ECAP2_APWM2, 12, 4, 0xf, 2, false) + MUX_CFG(DA830, EHRPWMGLUETZ, 12, 12, 0xf, 2, false) + MUX_CFG(DA830, EQEP1A, 12, 28, 0xf, 2, false) + MUX_CFG(DA830, GPIO4_11, 12, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_12, 12, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_13, 12, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_14, 12, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_0, 12, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_1, 12, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_2, 12, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_3, 12, 28, 0xf, 8, false) + MUX_CFG(DA830, AXR1_4, 13, 0, 0xf, 1, false) + MUX_CFG(DA830, AXR1_5, 13, 4, 0xf, 1, false) + MUX_CFG(DA830, AXR1_6, 13, 8, 0xf, 1, false) + MUX_CFG(DA830, AXR1_7, 13, 12, 0xf, 1, false) + MUX_CFG(DA830, AXR1_8, 13, 16, 0xf, 1, false) + MUX_CFG(DA830, AXR1_9, 13, 20, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_0, 13, 24, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_1, 13, 28, 0xf, 1, false) + MUX_CFG(DA830, EQEP1B, 13, 0, 0xf, 2, false) + MUX_CFG(DA830, EPWM2B, 13, 4, 0xf, 2, false) + MUX_CFG(DA830, EPWM2A, 13, 8, 0xf, 2, false) + MUX_CFG(DA830, EPWM1B, 13, 12, 0xf, 2, false) + MUX_CFG(DA830, EPWM1A, 13, 16, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_0, 13, 24, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_1, 13, 28, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_0, 13, 24, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HD_1, 13, 28, 0xf, 4, false) + MUX_CFG(DA830, GPIO4_4, 13, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_5, 13, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_6, 13, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_7, 13, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_8, 13, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_9, 13, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_0, 13, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_1, 13, 28, 0xf, 8, false) + MUX_CFG(DA830, EMA_D_2, 14, 0, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_3, 14, 4, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_4, 14, 8, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_5, 14, 12, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_6, 14, 16, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_7, 14, 20, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_8, 14, 24, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_9, 14, 28, 0xf, 1, false) + MUX_CFG(DA830, MMCSD_DAT_2, 14, 0, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_3, 14, 4, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_4, 14, 8, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_5, 14, 12, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_6, 14, 16, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_7, 14, 20, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_8, 14, 24, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_9, 14, 28, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_2, 14, 0, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HD_3, 14, 4, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HD_4, 14, 8, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HD_5, 14, 12, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HD_6, 14, 16, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HD_7, 14, 20, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_8, 14, 24, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_9, 14, 28, 0xf, 4, false) + MUX_CFG(DA830, GPIO0_2, 14, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_3, 14, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_4, 14, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_5, 14, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_6, 14, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_7, 14, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_8, 14, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_9, 14, 28, 0xf, 8, false) + MUX_CFG(DA830, EMA_D_10, 15, 0, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_11, 15, 4, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_12, 15, 8, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_13, 15, 12, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_14, 15, 16, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_15, 15, 20, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_0, 15, 24, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_1, 15, 28, 0xf, 1, false) + MUX_CFG(DA830, UHPI_HD_10, 15, 0, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_11, 15, 4, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_12, 15, 8, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_13, 15, 12, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_14, 15, 16, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_15, 15, 20, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_7, 15, 24, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_CLK, 15, 28, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_10, 15, 0, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_11, 15, 4, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_12, 15, 8, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_13, 15, 12, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_14, 15, 16, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_15, 15, 20, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HCNTL0, 15, 28, 0xf, 4, false) + MUX_CFG(DA830, GPIO0_10, 15, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_11, 15, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_12, 15, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_13, 15, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_14, 15, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_15, 15, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_0, 15, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_1, 15, 28, 0xf, 8, false) + MUX_CFG(DA830, EMA_A_2, 16, 0, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_3, 16, 4, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_4, 16, 8, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_5, 16, 12, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_6, 16, 16, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_7, 16, 20, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_8, 16, 24, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_9, 16, 28, 0xf, 1, false) + MUX_CFG(DA830, MMCSD_CMD, 16, 0, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_6, 16, 4, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_3, 16, 8, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_2, 16, 12, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_1, 16, 16, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_0, 16, 20, 0xf, 2, false) + MUX_CFG(DA830, LCD_PCLK, 16, 24, 0xf, 2, false) + MUX_CFG(DA830, LCD_HSYNC, 16, 28, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HCNTL1, 16, 0, 0xf, 4, false) + MUX_CFG(DA830, GPIO1_2, 16, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_3, 16, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_4, 16, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_5, 16, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_6, 16, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_7, 16, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_8, 16, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_9, 16, 28, 0xf, 8, false) + MUX_CFG(DA830, EMA_A_10, 17, 0, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_11, 17, 4, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_12, 17, 8, 0xf, 1, false) + MUX_CFG(DA830, EMA_BA_1, 17, 12, 0xf, 1, false) + MUX_CFG(DA830, EMA_BA_0, 17, 16, 0xf, 1, false) + MUX_CFG(DA830, EMA_CLK, 17, 20, 0xf, 1, false) + MUX_CFG(DA830, EMA_SDCKE, 17, 24, 0xf, 1, false) + MUX_CFG(DA830, NEMA_CAS, 17, 28, 0xf, 1, false) + MUX_CFG(DA830, LCD_VSYNC, 17, 0, 0xf, 2, false) + MUX_CFG(DA830, NLCD_AC_ENB_CS, 17, 4, 0xf, 2, false) + MUX_CFG(DA830, LCD_MCLK, 17, 8, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_5, 17, 12, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_4, 17, 16, 0xf, 2, false) + MUX_CFG(DA830, OBSCLK, 17, 20, 0xf, 2, false) + MUX_CFG(DA830, NEMA_CS_4, 17, 28, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HHWIL, 17, 12, 0xf, 4, false) + MUX_CFG(DA830, AHCLKR2, 17, 20, 0xf, 4, false) + MUX_CFG(DA830, GPIO1_10, 17, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_11, 17, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_12, 17, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_13, 17, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_14, 17, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_15, 17, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_0, 17, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_1, 17, 28, 0xf, 8, false) + MUX_CFG(DA830, NEMA_RAS, 18, 0, 0xf, 1, false) + MUX_CFG(DA830, NEMA_WE, 18, 4, 0xf, 1, false) + MUX_CFG(DA830, NEMA_CS_0, 18, 8, 0xf, 1, false) + MUX_CFG(DA830, NEMA_CS_2, 18, 12, 0xf, 1, false) + MUX_CFG(DA830, NEMA_CS_3, 18, 16, 0xf, 1, false) + MUX_CFG(DA830, NEMA_OE, 18, 20, 0xf, 1, false) + MUX_CFG(DA830, NEMA_WE_DQM_1, 18, 24, 0xf, 1, false) + MUX_CFG(DA830, NEMA_WE_DQM_0, 18, 28, 0xf, 1, false) + MUX_CFG(DA830, NEMA_CS_5, 18, 0, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HRNW, 18, 4, 0xf, 2, false) + MUX_CFG(DA830, NUHPI_HAS, 18, 8, 0xf, 2, false) + MUX_CFG(DA830, NUHPI_HCS, 18, 12, 0xf, 2, false) + MUX_CFG(DA830, NUHPI_HDS1, 18, 20, 0xf, 2, false) + MUX_CFG(DA830, NUHPI_HDS2, 18, 24, 0xf, 2, false) + MUX_CFG(DA830, NUHPI_HINT, 18, 28, 0xf, 2, false) + MUX_CFG(DA830, AXR0_12, 18, 4, 0xf, 4, false) + MUX_CFG(DA830, AMUTE2, 18, 16, 0xf, 4, false) + MUX_CFG(DA830, AXR0_13, 18, 20, 0xf, 4, false) + MUX_CFG(DA830, AXR0_14, 18, 24, 0xf, 4, false) + MUX_CFG(DA830, AXR0_15, 18, 28, 0xf, 4, false) + MUX_CFG(DA830, GPIO2_2, 18, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_3, 18, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_4, 18, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_5, 18, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_6, 18, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_7, 18, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_8, 18, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_9, 18, 28, 0xf, 8, false) + MUX_CFG(DA830, EMA_WAIT_0, 19, 0, 0xf, 1, false) + MUX_CFG(DA830, NUHPI_HRDY, 19, 0, 0xf, 2, false) + MUX_CFG(DA830, GPIO2_10, 19, 0, 0xf, 8, false) +#endif +}; + +static struct map_desc da830_io_desc[] = { + { + .virtual = IO_VIRT, + .pfn = __phys_to_pfn(IO_PHYS), + .length = IO_SIZE, + .type = MT_DEVICE + }, + { + .virtual = DA8XX_CP_INTC_VIRT, + .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), + .length = DA8XX_CP_INTC_SIZE, + .type = MT_DEVICE + }, +}; + +/* Contents of JTAG ID register used to identify exact cpu type */ +static struct davinci_id da830_ids[] = { + { + .variant = 0x0, + .part_no = 0xb7df, + .manufacturer = 0x017, /* 0x02f >> 1 */ + .cpu_id = DAVINCI_CPU_ID_DA830, + .name = "da830/omap-l137 rev1.0", + }, + { + .variant = 0x8, + .part_no = 0xb7df, + .manufacturer = 0x017, + .cpu_id = DAVINCI_CPU_ID_DA830, + .name = "da830/omap-l137 rev1.1", + }, + { + .variant = 0x9, + .part_no = 0xb7df, + .manufacturer = 0x017, + .cpu_id = DAVINCI_CPU_ID_DA830, + .name = "da830/omap-l137 rev2.0", + }, +}; + +static const struct davinci_soc_info davinci_soc_info_da830 = { + .io_desc = da830_io_desc, + .io_desc_num = ARRAY_SIZE(da830_io_desc), + .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG, + .ids = da830_ids, + .ids_num = ARRAY_SIZE(da830_ids), + .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, + .pinmux_pins = da830_pins, + .pinmux_pins_num = ARRAY_SIZE(da830_pins), +}; + +void __init da830_init(void) +{ + davinci_common_init(&davinci_soc_info_da830); + + da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); + WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"); +} diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c new file mode 100644 index 0000000000..287dd98790 --- /dev/null +++ b/arch/arm/mach-davinci/da850.c @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * TI DA850/OMAP-L138 chip specific setup + * + * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/ + * + * Derived from: arch/arm/mach-davinci/da830.c + * Original Copyrights follow: + * + * 2009 (c) MontaVista Software, Inc. + */ + +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/mfd/da8xx-cfgchip.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/regulator/consumer.h> +#include <clocksource/timer-davinci.h> + +#include <asm/mach/map.h> + +#include "common.h" +#include "cputype.h" +#include "da8xx.h" +#include "hardware.h" +#include "pm.h" +#include "irqs.h" +#include "mux.h" + +#define DA850_PLL1_BASE 0x01e1a000 +#define DA850_TIMER64P2_BASE 0x01f0c000 +#define DA850_TIMER64P3_BASE 0x01f0d000 + +#define DA850_REF_FREQ 24000000 + +/* + * Device specific mux setup + * + * soc description mux mode mode mux dbg + * reg offset mask mode + */ +static const struct mux_config da850_pins[] = { +#ifdef CONFIG_DAVINCI_MUX + /* UART0 function */ + MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false) + MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false) + MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false) + MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false) + /* UART1 function */ + MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false) + MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false) + /* UART2 function */ + MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false) + MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false) + /* I2C1 function */ + MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false) + MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false) + /* I2C0 function */ + MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false) + MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false) + /* EMAC function */ + MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false) + MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false) + MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false) + MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false) + MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false) + MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false) + MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false) + MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false) + MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false) + MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false) + MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false) + MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false) + MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false) + MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false) + MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false) + MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false) + MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false) + MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false) + MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false) + MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false) + MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false) + MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false) + MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false) + MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false) + MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false) + /* McASP function */ + MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false) + MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false) + MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false) + MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false) + MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false) + MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false) + MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false) + MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false) + MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false) + MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false) + MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false) + MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false) + MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false) + MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false) + MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false) + MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false) + MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false) + MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false) + MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false) + MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false) + MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false) + MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false) + MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false) + /* LCD function */ + MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false) + MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false) + MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false) + MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false) + MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false) + MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false) + MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false) + MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false) + MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false) + MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false) + MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false) + MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false) + MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false) + MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false) + MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false) + MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false) + MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false) + MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false) + MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false) + MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false) + /* MMC/SD0 function */ + MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false) + MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false) + MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false) + MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false) + MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false) + MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false) + /* MMC/SD1 function */ + MUX_CFG(DA850, MMCSD1_DAT_0, 18, 8, 15, 2, false) + MUX_CFG(DA850, MMCSD1_DAT_1, 19, 16, 15, 2, false) + MUX_CFG(DA850, MMCSD1_DAT_2, 19, 12, 15, 2, false) + MUX_CFG(DA850, MMCSD1_DAT_3, 19, 8, 15, 2, false) + MUX_CFG(DA850, MMCSD1_CLK, 18, 12, 15, 2, false) + MUX_CFG(DA850, MMCSD1_CMD, 18, 16, 15, 2, false) + /* EMIF2.5/EMIFA function */ + MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false) + MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false) + MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false) + MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false) + MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false) + MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false) + MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false) + MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false) + MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false) + MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false) + MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false) + MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false) + MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false) + MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false) + MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false) + MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false) + MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false) + MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false) + MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false) + MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false) + MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false) + MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false) + MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false) + MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false) + MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false) + MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false) + MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false) + MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false) + MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false) + MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false) + MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false) + MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false) + MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false) + MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false) + MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false) + MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false) + MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false) + MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false) + MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false) + MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false) + MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false) + MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false) + MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false) + MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false) + MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false) + MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false) + MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false) + MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false) + /* GPIO function */ + MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false) + MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false) + MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false) + MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false) + MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false) + MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false) + MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false) + MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false) + MUX_CFG(DA850, GPIO6_9, 13, 24, 15, 8, false) + MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false) + MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false) + MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false) + /* VPIF Capture */ + MUX_CFG(DA850, VPIF_DIN0, 15, 4, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN2, 14, 28, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN3, 14, 24, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN4, 14, 20, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN5, 14, 16, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN6, 14, 12, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN7, 14, 8, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN8, 16, 4, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN10, 15, 28, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN11, 15, 24, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN12, 15, 20, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN13, 15, 16, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN14, 15, 12, 15, 1, false) + MUX_CFG(DA850, VPIF_DIN15, 15, 8, 15, 1, false) + MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false) + MUX_CFG(DA850, VPIF_CLKIN1, 14, 4, 15, 1, false) + MUX_CFG(DA850, VPIF_CLKIN2, 19, 8, 15, 1, false) + MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1, false) + /* VPIF Display */ + MUX_CFG(DA850, VPIF_DOUT0, 17, 4, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT2, 16, 28, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT3, 16, 24, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT4, 16, 20, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT5, 16, 16, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT6, 16, 12, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT7, 16, 8, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT8, 18, 4, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1, false) + MUX_CFG(DA850, VPIF_DOUT15, 17, 8, 15, 1, false) + MUX_CFG(DA850, VPIF_CLKO2, 19, 12, 15, 1, false) + MUX_CFG(DA850, VPIF_CLKO3, 19, 20, 15, 1, false) +#endif +}; + +static struct map_desc da850_io_desc[] = { + { + .virtual = IO_VIRT, + .pfn = __phys_to_pfn(IO_PHYS), + .length = IO_SIZE, + .type = MT_DEVICE + }, + { + .virtual = DA8XX_CP_INTC_VIRT, + .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), + .length = DA8XX_CP_INTC_SIZE, + .type = MT_DEVICE + }, +}; + +/* Contents of JTAG ID register used to identify exact cpu type */ +static struct davinci_id da850_ids[] = { + { + .variant = 0x0, + .part_no = 0xb7d1, + .manufacturer = 0x017, /* 0x02f >> 1 */ + .cpu_id = DAVINCI_CPU_ID_DA850, + .name = "da850/omap-l138", + }, + { + .variant = 0x1, + .part_no = 0xb7d1, + .manufacturer = 0x017, /* 0x02f >> 1 */ + .cpu_id = DAVINCI_CPU_ID_DA850, + .name = "da850/omap-l138/am18x", + }, +}; + +/* VPIF resource, platform data */ +static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32); + +static struct resource da850_vpif_display_resource[] = { + { + .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), + .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da850_vpif_display_dev = { + .name = "vpif_display", + .id = -1, + .dev = { + .dma_mask = &da850_vpif_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = da850_vpif_display_resource, + .num_resources = ARRAY_SIZE(da850_vpif_display_resource), +}; + +static struct resource da850_vpif_capture_resource[] = { + { + .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), + .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), + .flags = IORESOURCE_IRQ, + }, + { + .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), + .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da850_vpif_capture_dev = { + .name = "vpif_capture", + .id = -1, + .dev = { + .dma_mask = &da850_vpif_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = da850_vpif_capture_resource, + .num_resources = ARRAY_SIZE(da850_vpif_capture_resource), +}; + +int __init da850_register_vpif_display(struct vpif_display_config + *display_config) +{ + da850_vpif_display_dev.dev.platform_data = display_config; + return platform_device_register(&da850_vpif_display_dev); +} + +int __init da850_register_vpif_capture(struct vpif_capture_config + *capture_config) +{ + da850_vpif_capture_dev.dev.platform_data = capture_config; + return platform_device_register(&da850_vpif_capture_dev); +} + +static const struct davinci_soc_info davinci_soc_info_da850 = { + .io_desc = da850_io_desc, + .io_desc_num = ARRAY_SIZE(da850_io_desc), + .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG, + .ids = da850_ids, + .ids_num = ARRAY_SIZE(da850_ids), + .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, + .pinmux_pins = da850_pins, + .pinmux_pins_num = ARRAY_SIZE(da850_pins), + .sram_dma = DA8XX_SHARED_RAM_BASE, + .sram_len = SZ_128K, +}; + +void __init da850_init(void) +{ + davinci_common_init(&davinci_soc_info_da850); + + da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); + if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module")) + return; + + da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K); + WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"); +} diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c new file mode 100644 index 0000000000..45763a9b37 --- /dev/null +++ b/arch/arm/mach-davinci/da8xx-dt.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ + * + * Modified from mach-omap/omap2/board-generic.c + */ + +#include <asm/mach/arch.h> + +#include "common.h" +#include "da8xx.h" + +#ifdef CONFIG_ARCH_DAVINCI_DA850 + +static void __init da850_init_machine(void) +{ + davinci_pm_init(); + pdata_quirks_init(); +} + +static const char *const da850_boards_compat[] __initconst = { + "enbw,cmc", + "ti,da850-lcdk", + "ti,da850-evm", + "ti,da850", + NULL, +}; + +DT_MACHINE_START(DA850_DT, "Generic DA850/OMAP-L138/AM18x") + .map_io = da850_init, + .init_machine = da850_init_machine, + .dt_compat = da850_boards_compat, + .init_late = davinci_init_late, +MACHINE_END + +#endif diff --git a/arch/arm/mach-davinci/da8xx.h b/arch/arm/mach-davinci/da8xx.h new file mode 100644 index 0000000000..54a255b8d8 --- /dev/null +++ b/arch/arm/mach-davinci/da8xx.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Chip specific defines for DA8XX/OMAP L1XX SoC + * + * Author: Mark A. Greer <mgreer@mvista.com> + * + * 2007, 2009-2010 (c) MontaVista Software, Inc. + */ +#ifndef __ASM_ARCH_DAVINCI_DA8XX_H +#define __ASM_ARCH_DAVINCI_DA8XX_H + +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> +#include <linux/videodev2.h> +#include <linux/reboot.h> +#include <linux/regmap.h> + +#include "hardware.h" +#include "pm.h" + +#include <media/davinci/vpif_types.h> + +extern void __iomem *da8xx_syscfg0_base; +extern void __iomem *da8xx_syscfg1_base; + +/* + * The cp_intc interrupt controller for the da8xx isn't in the same + * chunk of physical memory space as the other registers (like it is + * on the davincis) so it needs to be mapped separately. It will be + * mapped early on when the I/O space is mapped and we'll put it just + * before the I/O space in the processor's virtual memory space. + */ +#define DA8XX_CP_INTC_BASE 0xfffee000 +#define DA8XX_CP_INTC_SIZE SZ_8K +#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K) + +#define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000) +#define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x)) +#define DA8XX_JTAG_ID_REG 0x18 +#define DA8XX_HOST1CFG_REG 0x44 +#define DA8XX_CHIPSIG_REG 0x174 +#define DA8XX_CFGCHIP0_REG 0x17c +#define DA8XX_CFGCHIP1_REG 0x180 +#define DA8XX_CFGCHIP2_REG 0x184 +#define DA8XX_CFGCHIP3_REG 0x188 +#define DA8XX_CFGCHIP4_REG 0x18c + +#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000) +#define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x)) +#define DA8XX_DEEPSLEEP_REG 0x8 +#define DA8XX_PWRDN_REG 0x18 + +#define DA8XX_PSC0_BASE 0x01c10000 +#define DA8XX_PLL0_BASE 0x01c11000 +#define DA8XX_TIMER64P0_BASE 0x01c20000 +#define DA8XX_TIMER64P1_BASE 0x01c21000 +#define DA8XX_VPIF_BASE 0x01e17000 +#define DA8XX_GPIO_BASE 0x01e26000 +#define DA8XX_PSC1_BASE 0x01e27000 + +#define DA8XX_DSP_L2_RAM_BASE 0x11800000 +#define DA8XX_DSP_L1P_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x600000) +#define DA8XX_DSP_L1D_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x700000) + +#define DA8XX_AEMIF_CS2_BASE 0x60000000 +#define DA8XX_AEMIF_CS3_BASE 0x62000000 +#define DA8XX_AEMIF_CTL_BASE 0x68000000 +#define DA8XX_SHARED_RAM_BASE 0x80000000 +#define DA8XX_ARM_RAM_BASE 0xffff0000 + +void da830_init(void); + +void da850_init(void); + +int da850_register_vpif_display + (struct vpif_display_config *display_config); +int da850_register_vpif_capture + (struct vpif_capture_config *capture_config); +struct regmap *da8xx_get_cfgchip(void); +void __iomem *da8xx_get_mem_ctlr(void); + +#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ diff --git a/arch/arm/mach-davinci/ddr2.h b/arch/arm/mach-davinci/ddr2.h new file mode 100644 index 0000000000..4f7d7824b0 --- /dev/null +++ b/arch/arm/mach-davinci/ddr2.h @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#define DDR2_SDRCR_OFFSET 0xc +#define DDR2_SRPD_BIT (1 << 23) +#define DDR2_MCLKSTOPEN_BIT (1 << 30) +#define DDR2_LPMODEN_BIT (1 << 31) diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c new file mode 100644 index 0000000000..6939166c33 --- /dev/null +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DA8XX/OMAP L1XX platform device data + * + * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com> + * Derived from code that was: + * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> + */ +#include <linux/ahci_platform.h> +#include <linux/clk-provider.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/dma-map-ops.h> +#include <linux/dmaengine.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/reboot.h> +#include <linux/serial_8250.h> + +#include "common.h" +#include "cputype.h" +#include "da8xx.h" +#include "cpuidle.h" +#include "irqs.h" +#include "sram.h" + +#define DA8XX_TPCC_BASE 0x01c00000 +#define DA8XX_TPTC0_BASE 0x01c08000 +#define DA8XX_TPTC1_BASE 0x01c08400 +#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ +#define DA8XX_I2C0_BASE 0x01c22000 +#define DA8XX_RTC_BASE 0x01c23000 +#define DA8XX_PRUSS_MEM_BASE 0x01c30000 +#define DA8XX_MMCSD0_BASE 0x01c40000 +#define DA8XX_SPI0_BASE 0x01c41000 +#define DA830_SPI1_BASE 0x01e12000 +#define DA8XX_LCD_CNTRL_BASE 0x01e13000 +#define DA850_SATA_BASE 0x01e18000 +#define DA850_MMCSD1_BASE 0x01e1b000 +#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 +#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 +#define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 +#define DA8XX_EMAC_MDIO_BASE 0x01e24000 +#define DA8XX_I2C1_BASE 0x01e28000 +#define DA850_TPCC1_BASE 0x01e30000 +#define DA850_TPTC2_BASE 0x01e38000 +#define DA850_SPI1_BASE 0x01f0e000 +#define DA8XX_DDR2_CTL_BASE 0xb0000000 + +#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 +#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 +#define DA8XX_EMAC_RAM_OFFSET 0x0000 +#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K + +void __iomem *da8xx_syscfg0_base; +void __iomem *da8xx_syscfg1_base; + +static void __iomem *da8xx_ddr2_ctlr_base; +void __iomem * __init da8xx_get_mem_ctlr(void) +{ + if (da8xx_ddr2_ctlr_base) + return da8xx_ddr2_ctlr_base; + + da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K); + if (!da8xx_ddr2_ctlr_base) + pr_warn("%s: Unable to map DDR2 controller", __func__); + + return da8xx_ddr2_ctlr_base; +} diff --git a/arch/arm/mach-davinci/hardware.h b/arch/arm/mach-davinci/hardware.h new file mode 100644 index 0000000000..7848b6a240 --- /dev/null +++ b/arch/arm/mach-davinci/hardware.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Hardware definitions common to all DaVinci family processors + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * 2007 (c) Deep Root Systems, LLC. + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +/* + * Before you add anything to ths file: + * + * This header is for defines common to ALL DaVinci family chips. + * Anything that is chip specific should go in <chipname>.h, + * and the chip/board init code should then explicitly include + * <chipname>.h + */ +/* + * I/O mapping + */ +#define IO_PHYS UL(0x01c00000) +#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ +#define IO_SIZE 0x00400000 +#define IO_VIRT (IO_PHYS + IO_OFFSET) +#define io_v2p(va) ((va) - IO_OFFSET) +#define __IO_ADDRESS(x) ((x) + IO_OFFSET) +#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa)) + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-davinci/irqs.h b/arch/arm/mach-davinci/irqs.h new file mode 100644 index 0000000000..b1ceed81e9 --- /dev/null +++ b/arch/arm/mach-davinci/irqs.h @@ -0,0 +1,188 @@ +/* + * DaVinci interrupt controller definitions + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +/* DA8XX interrupts */ +#define IRQ_DA8XX_COMMTX 0 +#define IRQ_DA8XX_COMMRX 1 +#define IRQ_DA8XX_NINT 2 +#define IRQ_DA8XX_EVTOUT0 3 +#define IRQ_DA8XX_EVTOUT1 4 +#define IRQ_DA8XX_EVTOUT2 5 +#define IRQ_DA8XX_EVTOUT3 6 +#define IRQ_DA8XX_EVTOUT4 7 +#define IRQ_DA8XX_EVTOUT5 8 +#define IRQ_DA8XX_EVTOUT6 9 +#define IRQ_DA8XX_EVTOUT7 10 +#define IRQ_DA8XX_CCINT0 11 +#define IRQ_DA8XX_CCERRINT 12 +#define IRQ_DA8XX_TCERRINT0 13 +#define IRQ_DA8XX_AEMIFINT 14 +#define IRQ_DA8XX_I2CINT0 15 +#define IRQ_DA8XX_MMCSDINT0 16 +#define IRQ_DA8XX_MMCSDINT1 17 +#define IRQ_DA8XX_ALLINT0 18 +#define IRQ_DA8XX_RTC 19 +#define IRQ_DA8XX_SPINT0 20 +#define IRQ_DA8XX_TINT12_0 21 +#define IRQ_DA8XX_TINT34_0 22 +#define IRQ_DA8XX_TINT12_1 23 +#define IRQ_DA8XX_TINT34_1 24 +#define IRQ_DA8XX_UARTINT0 25 +#define IRQ_DA8XX_KEYMGRINT 26 +#define IRQ_DA8XX_SECINT 26 +#define IRQ_DA8XX_SECKEYERR 26 +#define IRQ_DA8XX_CHIPINT0 28 +#define IRQ_DA8XX_CHIPINT1 29 +#define IRQ_DA8XX_CHIPINT2 30 +#define IRQ_DA8XX_CHIPINT3 31 +#define IRQ_DA8XX_TCERRINT1 32 +#define IRQ_DA8XX_C0_RX_THRESH_PULSE 33 +#define IRQ_DA8XX_C0_RX_PULSE 34 +#define IRQ_DA8XX_C0_TX_PULSE 35 +#define IRQ_DA8XX_C0_MISC_PULSE 36 +#define IRQ_DA8XX_C1_RX_THRESH_PULSE 37 +#define IRQ_DA8XX_C1_RX_PULSE 38 +#define IRQ_DA8XX_C1_TX_PULSE 39 +#define IRQ_DA8XX_C1_MISC_PULSE 40 +#define IRQ_DA8XX_MEMERR 41 +#define IRQ_DA8XX_GPIO0 42 +#define IRQ_DA8XX_GPIO1 43 +#define IRQ_DA8XX_GPIO2 44 +#define IRQ_DA8XX_GPIO3 45 +#define IRQ_DA8XX_GPIO4 46 +#define IRQ_DA8XX_GPIO5 47 +#define IRQ_DA8XX_GPIO6 48 +#define IRQ_DA8XX_GPIO7 49 +#define IRQ_DA8XX_GPIO8 50 +#define IRQ_DA8XX_I2CINT1 51 +#define IRQ_DA8XX_LCDINT 52 +#define IRQ_DA8XX_UARTINT1 53 +#define IRQ_DA8XX_MCASPINT 54 +#define IRQ_DA8XX_ALLINT1 55 +#define IRQ_DA8XX_SPINT1 56 +#define IRQ_DA8XX_UHPI_INT1 57 +#define IRQ_DA8XX_USB_INT 58 +#define IRQ_DA8XX_IRQN 59 +#define IRQ_DA8XX_RWAKEUP 60 +#define IRQ_DA8XX_UARTINT2 61 +#define IRQ_DA8XX_DFTSSINT 62 +#define IRQ_DA8XX_EHRPWM0 63 +#define IRQ_DA8XX_EHRPWM0TZ 64 +#define IRQ_DA8XX_EHRPWM1 65 +#define IRQ_DA8XX_EHRPWM1TZ 66 +#define IRQ_DA8XX_ECAP0 69 +#define IRQ_DA8XX_ECAP1 70 +#define IRQ_DA8XX_ECAP2 71 +#define IRQ_DA8XX_ARMCLKSTOPREQ 90 + +/* DA830 specific interrupts */ +#define IRQ_DA830_MPUERR 27 +#define IRQ_DA830_IOPUERR 27 +#define IRQ_DA830_BOOTCFGERR 27 +#define IRQ_DA830_EHRPWM2 67 +#define IRQ_DA830_EHRPWM2TZ 68 +#define IRQ_DA830_EQEP0 72 +#define IRQ_DA830_EQEP1 73 +#define IRQ_DA830_T12CMPINT0_0 74 +#define IRQ_DA830_T12CMPINT1_0 75 +#define IRQ_DA830_T12CMPINT2_0 76 +#define IRQ_DA830_T12CMPINT3_0 77 +#define IRQ_DA830_T12CMPINT4_0 78 +#define IRQ_DA830_T12CMPINT5_0 79 +#define IRQ_DA830_T12CMPINT6_0 80 +#define IRQ_DA830_T12CMPINT7_0 81 +#define IRQ_DA830_T12CMPINT0_1 82 +#define IRQ_DA830_T12CMPINT1_1 83 +#define IRQ_DA830_T12CMPINT2_1 84 +#define IRQ_DA830_T12CMPINT3_1 85 +#define IRQ_DA830_T12CMPINT4_1 86 +#define IRQ_DA830_T12CMPINT5_1 87 +#define IRQ_DA830_T12CMPINT6_1 88 +#define IRQ_DA830_T12CMPINT7_1 89 + +#define DA830_N_CP_INTC_IRQ 96 + +/* DA850 speicific interrupts */ +#define IRQ_DA850_MPUADDRERR0 27 +#define IRQ_DA850_MPUPROTERR0 27 +#define IRQ_DA850_IOPUADDRERR0 27 +#define IRQ_DA850_IOPUPROTERR0 27 +#define IRQ_DA850_IOPUADDRERR1 27 +#define IRQ_DA850_IOPUPROTERR1 27 +#define IRQ_DA850_IOPUADDRERR2 27 +#define IRQ_DA850_IOPUPROTERR2 27 +#define IRQ_DA850_BOOTCFG_ADDR_ERR 27 +#define IRQ_DA850_BOOTCFG_PROT_ERR 27 +#define IRQ_DA850_MPUADDRERR1 27 +#define IRQ_DA850_MPUPROTERR1 27 +#define IRQ_DA850_IOPUADDRERR3 27 +#define IRQ_DA850_IOPUPROTERR3 27 +#define IRQ_DA850_IOPUADDRERR4 27 +#define IRQ_DA850_IOPUPROTERR4 27 +#define IRQ_DA850_IOPUADDRERR5 27 +#define IRQ_DA850_IOPUPROTERR5 27 +#define IRQ_DA850_MIOPU_BOOTCFG_ERR 27 +#define IRQ_DA850_SATAINT 67 +#define IRQ_DA850_TINT12_2 68 +#define IRQ_DA850_TINT34_2 68 +#define IRQ_DA850_TINTALL_2 68 +#define IRQ_DA850_MMCSDINT0_1 72 +#define IRQ_DA850_MMCSDINT1_1 73 +#define IRQ_DA850_T12CMPINT0_2 74 +#define IRQ_DA850_T12CMPINT1_2 75 +#define IRQ_DA850_T12CMPINT2_2 76 +#define IRQ_DA850_T12CMPINT3_2 77 +#define IRQ_DA850_T12CMPINT4_2 78 +#define IRQ_DA850_T12CMPINT5_2 79 +#define IRQ_DA850_T12CMPINT6_2 80 +#define IRQ_DA850_T12CMPINT7_2 81 +#define IRQ_DA850_T12CMPINT0_3 82 +#define IRQ_DA850_T12CMPINT1_3 83 +#define IRQ_DA850_T12CMPINT2_3 84 +#define IRQ_DA850_T12CMPINT3_3 85 +#define IRQ_DA850_T12CMPINT4_3 86 +#define IRQ_DA850_T12CMPINT5_3 87 +#define IRQ_DA850_T12CMPINT6_3 88 +#define IRQ_DA850_T12CMPINT7_3 89 +#define IRQ_DA850_RPIINT 91 +#define IRQ_DA850_VPIFINT 92 +#define IRQ_DA850_CCINT1 93 +#define IRQ_DA850_CCERRINT1 94 +#define IRQ_DA850_TCERRINT2 95 +#define IRQ_DA850_TINT12_3 96 +#define IRQ_DA850_TINT34_3 96 +#define IRQ_DA850_TINTALL_3 96 +#define IRQ_DA850_MCBSP0RINT 97 +#define IRQ_DA850_MCBSP0XINT 98 +#define IRQ_DA850_MCBSP1RINT 99 +#define IRQ_DA850_MCBSP1XINT 100 + +#define DA850_N_CP_INTC_IRQ 101 + +#endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c new file mode 100644 index 0000000000..37de35eb6e --- /dev/null +++ b/arch/arm/mach-davinci/mux.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Utility to set the DAVINCI MUX register from a table in mux.h + * + * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> + * + * Based on linux/arch/arm/plat-omap/mux.c: + * Copyright (C) 2003 - 2005 Nokia Corporation + * + * Written by Tony Lindgren + * + * 2007 (c) MontaVista Software, Inc. + * + * Copyright (C) 2008 Texas Instruments. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include <linux/io.h> +#include <linux/module.h> +#include <linux/spinlock.h> + +#include "mux.h" +#include "common.h" + +static void __iomem *pinmux_base; + +/* + * Sets the DAVINCI MUX register based on the table + */ +int davinci_cfg_reg(const unsigned long index) +{ + static DEFINE_SPINLOCK(mux_spin_lock); + struct davinci_soc_info *soc_info = &davinci_soc_info; + unsigned long flags; + const struct mux_config *cfg; + unsigned int reg_orig = 0, reg = 0; + unsigned int mask, warn = 0; + + if (WARN_ON(!soc_info->pinmux_pins)) + return -ENODEV; + + if (!pinmux_base) { + pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K); + if (WARN_ON(!pinmux_base)) + return -ENOMEM; + } + + if (index >= soc_info->pinmux_pins_num) { + pr_err("Invalid pin mux index: %lu (%lu)\n", + index, soc_info->pinmux_pins_num); + dump_stack(); + return -ENODEV; + } + + cfg = &soc_info->pinmux_pins[index]; + + if (cfg->name == NULL) { + pr_err("No entry for the specified index\n"); + return -ENODEV; + } + + /* Update the mux register in question */ + if (cfg->mask) { + unsigned tmp1, tmp2; + + spin_lock_irqsave(&mux_spin_lock, flags); + reg_orig = __raw_readl(pinmux_base + cfg->mux_reg); + + mask = (cfg->mask << cfg->mask_offset); + tmp1 = reg_orig & mask; + reg = reg_orig & ~mask; + + tmp2 = (cfg->mode << cfg->mask_offset); + reg |= tmp2; + + if (tmp1 != tmp2) + warn = 1; + + __raw_writel(reg, pinmux_base + cfg->mux_reg); + spin_unlock_irqrestore(&mux_spin_lock, flags); + } + + if (warn) { +#ifdef CONFIG_DAVINCI_MUX_WARNINGS + pr_warn("initialized %s\n", cfg->name); +#endif + } + +#ifdef CONFIG_DAVINCI_MUX_DEBUG + if (cfg->debug || warn) { + pr_warn("Setting register %s\n", cfg->name); + pr_warn(" %s (0x%08x) = 0x%08x -> 0x%08x\n", + cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); + } +#endif + + return 0; +} diff --git a/arch/arm/mach-davinci/mux.h b/arch/arm/mach-davinci/mux.h new file mode 100644 index 0000000000..38f0e42729 --- /dev/null +++ b/arch/arm/mach-davinci/mux.h @@ -0,0 +1,701 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Pin-multiplex helper macros for TI DaVinci family devices + * + * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. + * + * Copyright (C) 2008 Texas Instruments. + */ +#ifndef _MACH_DAVINCI_MUX_H_ +#define _MACH_DAVINCI_MUX_H_ + +struct mux_config { + const char *name; + const char *mux_reg_name; + const unsigned char mux_reg; + const unsigned char mask_offset; + const unsigned char mask; + const unsigned char mode; + bool debug; +}; + +enum da830_index { + DA830_GPIO7_14, + DA830_RTCK, + DA830_GPIO7_15, + DA830_EMU_0, + DA830_EMB_SDCKE, + DA830_EMB_CLK_GLUE, + DA830_EMB_CLK, + DA830_NEMB_CS_0, + DA830_NEMB_CAS, + DA830_NEMB_RAS, + DA830_NEMB_WE, + DA830_EMB_BA_1, + DA830_EMB_BA_0, + DA830_EMB_A_0, + DA830_EMB_A_1, + DA830_EMB_A_2, + DA830_EMB_A_3, + DA830_EMB_A_4, + DA830_EMB_A_5, + DA830_GPIO7_0, + DA830_GPIO7_1, + DA830_GPIO7_2, + DA830_GPIO7_3, + DA830_GPIO7_4, + DA830_GPIO7_5, + DA830_GPIO7_6, + DA830_GPIO7_7, + DA830_EMB_A_6, + DA830_EMB_A_7, + DA830_EMB_A_8, + DA830_EMB_A_9, + DA830_EMB_A_10, + DA830_EMB_A_11, + DA830_EMB_A_12, + DA830_EMB_D_31, + DA830_GPIO7_8, + DA830_GPIO7_9, + DA830_GPIO7_10, + DA830_GPIO7_11, + DA830_GPIO7_12, + DA830_GPIO7_13, + DA830_GPIO3_13, + DA830_EMB_D_30, + DA830_EMB_D_29, + DA830_EMB_D_28, + DA830_EMB_D_27, + DA830_EMB_D_26, + DA830_EMB_D_25, + DA830_EMB_D_24, + DA830_EMB_D_23, + DA830_EMB_D_22, + DA830_EMB_D_21, + DA830_EMB_D_20, + DA830_EMB_D_19, + DA830_EMB_D_18, + DA830_EMB_D_17, + DA830_EMB_D_16, + DA830_NEMB_WE_DQM_3, + DA830_NEMB_WE_DQM_2, + DA830_EMB_D_0, + DA830_EMB_D_1, + DA830_EMB_D_2, + DA830_EMB_D_3, + DA830_EMB_D_4, + DA830_EMB_D_5, + DA830_EMB_D_6, + DA830_GPIO6_0, + DA830_GPIO6_1, + DA830_GPIO6_2, + DA830_GPIO6_3, + DA830_GPIO6_4, + DA830_GPIO6_5, + DA830_GPIO6_6, + DA830_EMB_D_7, + DA830_EMB_D_8, + DA830_EMB_D_9, + DA830_EMB_D_10, + DA830_EMB_D_11, + DA830_EMB_D_12, + DA830_EMB_D_13, + DA830_EMB_D_14, + DA830_GPIO6_7, + DA830_GPIO6_8, + DA830_GPIO6_9, + DA830_GPIO6_10, + DA830_GPIO6_11, + DA830_GPIO6_12, + DA830_GPIO6_13, + DA830_GPIO6_14, + DA830_EMB_D_15, + DA830_NEMB_WE_DQM_1, + DA830_NEMB_WE_DQM_0, + DA830_SPI0_SOMI_0, + DA830_SPI0_SIMO_0, + DA830_SPI0_CLK, + DA830_NSPI0_ENA, + DA830_NSPI0_SCS_0, + DA830_EQEP0I, + DA830_EQEP0S, + DA830_EQEP1I, + DA830_NUART0_CTS, + DA830_NUART0_RTS, + DA830_EQEP0A, + DA830_EQEP0B, + DA830_GPIO6_15, + DA830_GPIO5_14, + DA830_GPIO5_15, + DA830_GPIO5_0, + DA830_GPIO5_1, + DA830_GPIO5_2, + DA830_GPIO5_3, + DA830_GPIO5_4, + DA830_SPI1_SOMI_0, + DA830_SPI1_SIMO_0, + DA830_SPI1_CLK, + DA830_UART0_RXD, + DA830_UART0_TXD, + DA830_AXR1_10, + DA830_AXR1_11, + DA830_NSPI1_ENA, + DA830_I2C1_SCL, + DA830_I2C1_SDA, + DA830_EQEP1S, + DA830_I2C0_SDA, + DA830_I2C0_SCL, + DA830_UART2_RXD, + DA830_TM64P0_IN12, + DA830_TM64P0_OUT12, + DA830_GPIO5_5, + DA830_GPIO5_6, + DA830_GPIO5_7, + DA830_GPIO5_8, + DA830_GPIO5_9, + DA830_GPIO5_10, + DA830_GPIO5_11, + DA830_GPIO5_12, + DA830_NSPI1_SCS_0, + DA830_USB0_DRVVBUS, + DA830_AHCLKX0, + DA830_ACLKX0, + DA830_AFSX0, + DA830_AHCLKR0, + DA830_ACLKR0, + DA830_AFSR0, + DA830_UART2_TXD, + DA830_AHCLKX2, + DA830_ECAP0_APWM0, + DA830_RMII_MHZ_50_CLK, + DA830_ECAP1_APWM1, + DA830_USB_REFCLKIN, + DA830_GPIO5_13, + DA830_GPIO4_15, + DA830_GPIO2_11, + DA830_GPIO2_12, + DA830_GPIO2_13, + DA830_GPIO2_14, + DA830_GPIO2_15, + DA830_GPIO3_12, + DA830_AMUTE0, + DA830_AXR0_0, + DA830_AXR0_1, + DA830_AXR0_2, + DA830_AXR0_3, + DA830_AXR0_4, + DA830_AXR0_5, + DA830_AXR0_6, + DA830_RMII_TXD_0, + DA830_RMII_TXD_1, + DA830_RMII_TXEN, + DA830_RMII_CRS_DV, + DA830_RMII_RXD_0, + DA830_RMII_RXD_1, + DA830_RMII_RXER, + DA830_AFSR2, + DA830_ACLKX2, + DA830_AXR2_3, + DA830_AXR2_2, + DA830_AXR2_1, + DA830_AFSX2, + DA830_ACLKR2, + DA830_NRESETOUT, + DA830_GPIO3_0, + DA830_GPIO3_1, + DA830_GPIO3_2, + DA830_GPIO3_3, + DA830_GPIO3_4, + DA830_GPIO3_5, + DA830_GPIO3_6, + DA830_AXR0_7, + DA830_AXR0_8, + DA830_UART1_RXD, + DA830_UART1_TXD, + DA830_AXR0_11, + DA830_AHCLKX1, + DA830_ACLKX1, + DA830_AFSX1, + DA830_MDIO_CLK, + DA830_MDIO_D, + DA830_AXR0_9, + DA830_AXR0_10, + DA830_EPWM0B, + DA830_EPWM0A, + DA830_EPWMSYNCI, + DA830_AXR2_0, + DA830_EPWMSYNC0, + DA830_GPIO3_7, + DA830_GPIO3_8, + DA830_GPIO3_9, + DA830_GPIO3_10, + DA830_GPIO3_11, + DA830_GPIO3_14, + DA830_GPIO3_15, + DA830_GPIO4_10, + DA830_AHCLKR1, + DA830_ACLKR1, + DA830_AFSR1, + DA830_AMUTE1, + DA830_AXR1_0, + DA830_AXR1_1, + DA830_AXR1_2, + DA830_AXR1_3, + DA830_ECAP2_APWM2, + DA830_EHRPWMGLUETZ, + DA830_EQEP1A, + DA830_GPIO4_11, + DA830_GPIO4_12, + DA830_GPIO4_13, + DA830_GPIO4_14, + DA830_GPIO4_0, + DA830_GPIO4_1, + DA830_GPIO4_2, + DA830_GPIO4_3, + DA830_AXR1_4, + DA830_AXR1_5, + DA830_AXR1_6, + DA830_AXR1_7, + DA830_AXR1_8, + DA830_AXR1_9, + DA830_EMA_D_0, + DA830_EMA_D_1, + DA830_EQEP1B, + DA830_EPWM2B, + DA830_EPWM2A, + DA830_EPWM1B, + DA830_EPWM1A, + DA830_MMCSD_DAT_0, + DA830_MMCSD_DAT_1, + DA830_UHPI_HD_0, + DA830_UHPI_HD_1, + DA830_GPIO4_4, + DA830_GPIO4_5, + DA830_GPIO4_6, + DA830_GPIO4_7, + DA830_GPIO4_8, + DA830_GPIO4_9, + DA830_GPIO0_0, + DA830_GPIO0_1, + DA830_EMA_D_2, + DA830_EMA_D_3, + DA830_EMA_D_4, + DA830_EMA_D_5, + DA830_EMA_D_6, + DA830_EMA_D_7, + DA830_EMA_D_8, + DA830_EMA_D_9, + DA830_MMCSD_DAT_2, + DA830_MMCSD_DAT_3, + DA830_MMCSD_DAT_4, + DA830_MMCSD_DAT_5, + DA830_MMCSD_DAT_6, + DA830_MMCSD_DAT_7, + DA830_UHPI_HD_8, + DA830_UHPI_HD_9, + DA830_UHPI_HD_2, + DA830_UHPI_HD_3, + DA830_UHPI_HD_4, + DA830_UHPI_HD_5, + DA830_UHPI_HD_6, + DA830_UHPI_HD_7, + DA830_LCD_D_8, + DA830_LCD_D_9, + DA830_GPIO0_2, + DA830_GPIO0_3, + DA830_GPIO0_4, + DA830_GPIO0_5, + DA830_GPIO0_6, + DA830_GPIO0_7, + DA830_GPIO0_8, + DA830_GPIO0_9, + DA830_EMA_D_10, + DA830_EMA_D_11, + DA830_EMA_D_12, + DA830_EMA_D_13, + DA830_EMA_D_14, + DA830_EMA_D_15, + DA830_EMA_A_0, + DA830_EMA_A_1, + DA830_UHPI_HD_10, + DA830_UHPI_HD_11, + DA830_UHPI_HD_12, + DA830_UHPI_HD_13, + DA830_UHPI_HD_14, + DA830_UHPI_HD_15, + DA830_LCD_D_7, + DA830_MMCSD_CLK, + DA830_LCD_D_10, + DA830_LCD_D_11, + DA830_LCD_D_12, + DA830_LCD_D_13, + DA830_LCD_D_14, + DA830_LCD_D_15, + DA830_UHPI_HCNTL0, + DA830_GPIO0_10, + DA830_GPIO0_11, + DA830_GPIO0_12, + DA830_GPIO0_13, + DA830_GPIO0_14, + DA830_GPIO0_15, + DA830_GPIO1_0, + DA830_GPIO1_1, + DA830_EMA_A_2, + DA830_EMA_A_3, + DA830_EMA_A_4, + DA830_EMA_A_5, + DA830_EMA_A_6, + DA830_EMA_A_7, + DA830_EMA_A_8, + DA830_EMA_A_9, + DA830_MMCSD_CMD, + DA830_LCD_D_6, + DA830_LCD_D_3, + DA830_LCD_D_2, + DA830_LCD_D_1, + DA830_LCD_D_0, + DA830_LCD_PCLK, + DA830_LCD_HSYNC, + DA830_UHPI_HCNTL1, + DA830_GPIO1_2, + DA830_GPIO1_3, + DA830_GPIO1_4, + DA830_GPIO1_5, + DA830_GPIO1_6, + DA830_GPIO1_7, + DA830_GPIO1_8, + DA830_GPIO1_9, + DA830_EMA_A_10, + DA830_EMA_A_11, + DA830_EMA_A_12, + DA830_EMA_BA_1, + DA830_EMA_BA_0, + DA830_EMA_CLK, + DA830_EMA_SDCKE, + DA830_NEMA_CAS, + DA830_LCD_VSYNC, + DA830_NLCD_AC_ENB_CS, + DA830_LCD_MCLK, + DA830_LCD_D_5, + DA830_LCD_D_4, + DA830_OBSCLK, + DA830_NEMA_CS_4, + DA830_UHPI_HHWIL, + DA830_AHCLKR2, + DA830_GPIO1_10, + DA830_GPIO1_11, + DA830_GPIO1_12, + DA830_GPIO1_13, + DA830_GPIO1_14, + DA830_GPIO1_15, + DA830_GPIO2_0, + DA830_GPIO2_1, + DA830_NEMA_RAS, + DA830_NEMA_WE, + DA830_NEMA_CS_0, + DA830_NEMA_CS_2, + DA830_NEMA_CS_3, + DA830_NEMA_OE, + DA830_NEMA_WE_DQM_1, + DA830_NEMA_WE_DQM_0, + DA830_NEMA_CS_5, + DA830_UHPI_HRNW, + DA830_NUHPI_HAS, + DA830_NUHPI_HCS, + DA830_NUHPI_HDS1, + DA830_NUHPI_HDS2, + DA830_NUHPI_HINT, + DA830_AXR0_12, + DA830_AMUTE2, + DA830_AXR0_13, + DA830_AXR0_14, + DA830_AXR0_15, + DA830_GPIO2_2, + DA830_GPIO2_3, + DA830_GPIO2_4, + DA830_GPIO2_5, + DA830_GPIO2_6, + DA830_GPIO2_7, + DA830_GPIO2_8, + DA830_GPIO2_9, + DA830_EMA_WAIT_0, + DA830_NUHPI_HRDY, + DA830_GPIO2_10, +}; + +enum davinci_da850_index { + /* UART0 function */ + DA850_NUART0_CTS, + DA850_NUART0_RTS, + DA850_UART0_RXD, + DA850_UART0_TXD, + + /* UART1 function */ + DA850_NUART1_CTS, + DA850_NUART1_RTS, + DA850_UART1_RXD, + DA850_UART1_TXD, + + /* UART2 function */ + DA850_NUART2_CTS, + DA850_NUART2_RTS, + DA850_UART2_RXD, + DA850_UART2_TXD, + + /* I2C1 function */ + DA850_I2C1_SCL, + DA850_I2C1_SDA, + + /* I2C0 function */ + DA850_I2C0_SDA, + DA850_I2C0_SCL, + + /* EMAC function */ + DA850_MII_TXEN, + DA850_MII_TXCLK, + DA850_MII_COL, + DA850_MII_TXD_3, + DA850_MII_TXD_2, + DA850_MII_TXD_1, + DA850_MII_TXD_0, + DA850_MII_RXER, + DA850_MII_CRS, + DA850_MII_RXCLK, + DA850_MII_RXDV, + DA850_MII_RXD_3, + DA850_MII_RXD_2, + DA850_MII_RXD_1, + DA850_MII_RXD_0, + DA850_MDIO_CLK, + DA850_MDIO_D, + DA850_RMII_TXD_0, + DA850_RMII_TXD_1, + DA850_RMII_TXEN, + DA850_RMII_CRS_DV, + DA850_RMII_RXD_0, + DA850_RMII_RXD_1, + DA850_RMII_RXER, + DA850_RMII_MHZ_50_CLK, + + /* McASP function */ + DA850_ACLKR, + DA850_ACLKX, + DA850_AFSR, + DA850_AFSX, + DA850_AHCLKR, + DA850_AHCLKX, + DA850_AMUTE, + DA850_AXR_15, + DA850_AXR_14, + DA850_AXR_13, + DA850_AXR_12, + DA850_AXR_11, + DA850_AXR_10, + DA850_AXR_9, + DA850_AXR_8, + DA850_AXR_7, + DA850_AXR_6, + DA850_AXR_5, + DA850_AXR_4, + DA850_AXR_3, + DA850_AXR_2, + DA850_AXR_1, + DA850_AXR_0, + + /* LCD function */ + DA850_LCD_D_7, + DA850_LCD_D_6, + DA850_LCD_D_5, + DA850_LCD_D_4, + DA850_LCD_D_3, + DA850_LCD_D_2, + DA850_LCD_D_1, + DA850_LCD_D_0, + DA850_LCD_D_15, + DA850_LCD_D_14, + DA850_LCD_D_13, + DA850_LCD_D_12, + DA850_LCD_D_11, + DA850_LCD_D_10, + DA850_LCD_D_9, + DA850_LCD_D_8, + DA850_LCD_PCLK, + DA850_LCD_HSYNC, + DA850_LCD_VSYNC, + DA850_NLCD_AC_ENB_CS, + + /* MMC/SD0 function */ + DA850_MMCSD0_DAT_0, + DA850_MMCSD0_DAT_1, + DA850_MMCSD0_DAT_2, + DA850_MMCSD0_DAT_3, + DA850_MMCSD0_CLK, + DA850_MMCSD0_CMD, + + /* MMC/SD1 function */ + DA850_MMCSD1_DAT_0, + DA850_MMCSD1_DAT_1, + DA850_MMCSD1_DAT_2, + DA850_MMCSD1_DAT_3, + DA850_MMCSD1_CLK, + DA850_MMCSD1_CMD, + + /* EMIF2.5/EMIFA function */ + DA850_EMA_D_7, + DA850_EMA_D_6, + DA850_EMA_D_5, + DA850_EMA_D_4, + DA850_EMA_D_3, + DA850_EMA_D_2, + DA850_EMA_D_1, + DA850_EMA_D_0, + DA850_EMA_A_1, + DA850_EMA_A_2, + DA850_NEMA_CS_3, + DA850_NEMA_CS_4, + DA850_NEMA_WE, + DA850_NEMA_OE, + DA850_EMA_D_15, + DA850_EMA_D_14, + DA850_EMA_D_13, + DA850_EMA_D_12, + DA850_EMA_D_11, + DA850_EMA_D_10, + DA850_EMA_D_9, + DA850_EMA_D_8, + DA850_EMA_A_0, + DA850_EMA_A_3, + DA850_EMA_A_4, + DA850_EMA_A_5, + DA850_EMA_A_6, + DA850_EMA_A_7, + DA850_EMA_A_8, + DA850_EMA_A_9, + DA850_EMA_A_10, + DA850_EMA_A_11, + DA850_EMA_A_12, + DA850_EMA_A_13, + DA850_EMA_A_14, + DA850_EMA_A_15, + DA850_EMA_A_16, + DA850_EMA_A_17, + DA850_EMA_A_18, + DA850_EMA_A_19, + DA850_EMA_A_20, + DA850_EMA_A_21, + DA850_EMA_A_22, + DA850_EMA_A_23, + DA850_EMA_BA_1, + DA850_EMA_CLK, + DA850_EMA_WAIT_1, + DA850_NEMA_CS_2, + + /* GPIO function */ + DA850_GPIO2_4, + DA850_GPIO2_6, + DA850_GPIO2_8, + DA850_GPIO2_15, + DA850_GPIO3_12, + DA850_GPIO3_13, + DA850_GPIO4_0, + DA850_GPIO4_1, + DA850_GPIO6_9, + DA850_GPIO6_10, + DA850_GPIO6_13, + DA850_RTC_ALARM, + + /* VPIF Capture */ + DA850_VPIF_DIN0, + DA850_VPIF_DIN1, + DA850_VPIF_DIN2, + DA850_VPIF_DIN3, + DA850_VPIF_DIN4, + DA850_VPIF_DIN5, + DA850_VPIF_DIN6, + DA850_VPIF_DIN7, + DA850_VPIF_DIN8, + DA850_VPIF_DIN9, + DA850_VPIF_DIN10, + DA850_VPIF_DIN11, + DA850_VPIF_DIN12, + DA850_VPIF_DIN13, + DA850_VPIF_DIN14, + DA850_VPIF_DIN15, + DA850_VPIF_CLKIN0, + DA850_VPIF_CLKIN1, + DA850_VPIF_CLKIN2, + DA850_VPIF_CLKIN3, + + /* VPIF Display */ + DA850_VPIF_DOUT0, + DA850_VPIF_DOUT1, + DA850_VPIF_DOUT2, + DA850_VPIF_DOUT3, + DA850_VPIF_DOUT4, + DA850_VPIF_DOUT5, + DA850_VPIF_DOUT6, + DA850_VPIF_DOUT7, + DA850_VPIF_DOUT8, + DA850_VPIF_DOUT9, + DA850_VPIF_DOUT10, + DA850_VPIF_DOUT11, + DA850_VPIF_DOUT12, + DA850_VPIF_DOUT13, + DA850_VPIF_DOUT14, + DA850_VPIF_DOUT15, + DA850_VPIF_CLKO2, + DA850_VPIF_CLKO3, +}; + +#define PINMUX(x) (4 * (x)) + +#ifdef CONFIG_DAVINCI_MUX +/* setup pin muxing */ +extern int davinci_cfg_reg(unsigned long reg_cfg); +extern int davinci_cfg_reg_list(const short pins[]); +#else +/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */ +static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; } +static inline int davinci_cfg_reg_list(const short pins[]) +{ + return 0; +} +#endif + + +#define MUX_CFG(soc, desc, muxreg, mode_offset, mode_mask, mux_mode, dbg)\ +[soc##_##desc] = { \ + .name = #desc, \ + .debug = dbg, \ + .mux_reg_name = "PINMUX"#muxreg, \ + .mux_reg = PINMUX(muxreg), \ + .mask_offset = mode_offset, \ + .mask = mode_mask, \ + .mode = mux_mode, \ + }, + +#define INT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \ +[soc##_##desc] = { \ + .name = #desc, \ + .debug = dbg, \ + .mux_reg_name = "INTMUX", \ + .mux_reg = INTMUX, \ + .mask_offset = mode_offset, \ + .mask = mode_mask, \ + .mode = mux_mode, \ + }, + +#define EVT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \ +[soc##_##desc] = { \ + .name = #desc, \ + .debug = dbg, \ + .mux_reg_name = "EVTMUX", \ + .mux_reg = EVTMUX, \ + .mask_offset = mode_offset, \ + .mask = mode_mask, \ + .mode = mux_mode, \ + }, + +#endif /* _MACH_DAVINCI_MUX_H */ diff --git a/arch/arm/mach-davinci/pdata-quirks.c b/arch/arm/mach-davinci/pdata-quirks.c new file mode 100644 index 0000000000..b5b5c7bda6 --- /dev/null +++ b/arch/arm/mach-davinci/pdata-quirks.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Legacy platform_data quirks + * + * Copyright (C) 2016 BayLibre, Inc + */ +#include <linux/kernel.h> +#include <linux/of.h> + +#include <media/i2c/tvp514x.h> +#include <media/i2c/adv7343.h> + +#include "common.h" +#include "da8xx.h" + +struct pdata_init { + const char *compatible; + void (*fn)(void); +}; + +#define TVP5147_CH0 "tvp514x-0" +#define TVP5147_CH1 "tvp514x-1" + +/* VPIF capture configuration */ +static struct tvp514x_platform_data tvp5146_pdata = { + .clk_polarity = 0, + .hs_polarity = 1, + .vs_polarity = 1, +}; + +#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) + +static struct vpif_input da850_ch0_inputs[] = { + { + .input = { + .index = 0, + .name = "Composite", + .type = V4L2_INPUT_TYPE_CAMERA, + .capabilities = V4L2_IN_CAP_STD, + .std = TVP514X_STD_ALL, + }, + .input_route = INPUT_CVBS_VI2B, + .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC, + .subdev_name = TVP5147_CH0, + }, +}; + +static struct vpif_input da850_ch1_inputs[] = { + { + .input = { + .index = 0, + .name = "S-Video", + .type = V4L2_INPUT_TYPE_CAMERA, + .capabilities = V4L2_IN_CAP_STD, + .std = TVP514X_STD_ALL, + }, + .input_route = INPUT_SVIDEO_VI2C_VI1C, + .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC, + .subdev_name = TVP5147_CH1, + }, +}; + +static struct vpif_subdev_info da850_vpif_capture_sdev_info[] = { + { + .name = TVP5147_CH0, + .board_info = { + I2C_BOARD_INFO("tvp5146", 0x5d), + .platform_data = &tvp5146_pdata, + }, + }, + { + .name = TVP5147_CH1, + .board_info = { + I2C_BOARD_INFO("tvp5146", 0x5c), + .platform_data = &tvp5146_pdata, + }, + }, +}; + +static struct vpif_capture_config da850_vpif_capture_config = { + .subdev_info = da850_vpif_capture_sdev_info, + .subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info), + .chan_config[0] = { + .inputs = da850_ch0_inputs, + .input_count = ARRAY_SIZE(da850_ch0_inputs), + .vpif_if = { + .if_type = VPIF_IF_BT656, + .hd_pol = 1, + .vd_pol = 1, + .fid_pol = 0, + }, + }, + .chan_config[1] = { + .inputs = da850_ch1_inputs, + .input_count = ARRAY_SIZE(da850_ch1_inputs), + .vpif_if = { + .if_type = VPIF_IF_BT656, + .hd_pol = 1, + .vd_pol = 1, + .fid_pol = 0, + }, + }, + .card_name = "DA850/OMAP-L138 Video Capture", +}; + +static void __init da850_vpif_legacy_register_capture(void) +{ + int ret; + + ret = da850_register_vpif_capture(&da850_vpif_capture_config); + if (ret) + pr_warn("%s: VPIF capture setup failed: %d\n", + __func__, ret); +} + +static void __init da850_vpif_capture_legacy_init_lcdk(void) +{ + da850_vpif_capture_config.subdev_count = 1; + da850_vpif_legacy_register_capture(); +} + +static void __init da850_vpif_capture_legacy_init_evm(void) +{ + da850_vpif_legacy_register_capture(); +} + +static struct adv7343_platform_data adv7343_pdata = { + .mode_config = { + .dac = { 1, 1, 1 }, + }, + .sd_config = { + .sd_dac_out = { 1 }, + }, +}; + +static struct vpif_subdev_info da850_vpif_subdev[] = { + { + .name = "adv7343", + .board_info = { + I2C_BOARD_INFO("adv7343", 0x2a), + .platform_data = &adv7343_pdata, + }, + }, +}; + +static const struct vpif_output da850_ch0_outputs[] = { + { + .output = { + .index = 0, + .name = "Composite", + .type = V4L2_OUTPUT_TYPE_ANALOG, + .capabilities = V4L2_OUT_CAP_STD, + .std = V4L2_STD_ALL, + }, + .subdev_name = "adv7343", + .output_route = ADV7343_COMPOSITE_ID, + }, + { + .output = { + .index = 1, + .name = "S-Video", + .type = V4L2_OUTPUT_TYPE_ANALOG, + .capabilities = V4L2_OUT_CAP_STD, + .std = V4L2_STD_ALL, + }, + .subdev_name = "adv7343", + .output_route = ADV7343_SVIDEO_ID, + }, +}; + +static struct vpif_display_config da850_vpif_display_config = { + .subdevinfo = da850_vpif_subdev, + .subdev_count = ARRAY_SIZE(da850_vpif_subdev), + .chan_config[0] = { + .outputs = da850_ch0_outputs, + .output_count = ARRAY_SIZE(da850_ch0_outputs), + }, + .card_name = "DA850/OMAP-L138 Video Display", +}; + +static void __init da850_vpif_display_legacy_init_evm(void) +{ + int ret; + + ret = da850_register_vpif_display(&da850_vpif_display_config); + if (ret) + pr_warn("%s: VPIF display setup failed: %d\n", + __func__, ret); +} + +static void pdata_quirks_check(struct pdata_init *quirks) +{ + while (quirks->compatible) { + if (of_machine_is_compatible(quirks->compatible)) { + if (quirks->fn) + quirks->fn(); + } + quirks++; + } +} + +static struct pdata_init pdata_quirks[] __initdata = { + { "ti,da850-lcdk", da850_vpif_capture_legacy_init_lcdk, }, + { "ti,da850-evm", da850_vpif_display_legacy_init_evm, }, + { "ti,da850-evm", da850_vpif_capture_legacy_init_evm, }, + { /* sentinel */ }, +}; + +void __init pdata_quirks_init(void) +{ + pdata_quirks_check(pdata_quirks); +} diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c new file mode 100644 index 0000000000..8aa39db095 --- /dev/null +++ b/arch/arm/mach-davinci/pm.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * DaVinci Power Management Routines + * + * Copyright (C) 2009 Texas Instruments, Inc. https://www.ti.com/ + */ + +#include <linux/pm.h> +#include <linux/suspend.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/spinlock.h> + +#include <asm/cacheflush.h> +#include <asm/delay.h> +#include <asm/io.h> + +#include "common.h" +#include "da8xx.h" +#include "mux.h" +#include "pm.h" +#include "clock.h" +#include "psc.h" +#include "sram.h" + +#define DA850_PLL1_BASE 0x01e1a000 +#define DEEPSLEEP_SLEEPCOUNT_MASK 0xFFFF +#define DEEPSLEEP_SLEEPCOUNT 128 + +static void (*davinci_sram_suspend) (struct davinci_pm_config *); +static struct davinci_pm_config pm_config = { + .sleepcount = DEEPSLEEP_SLEEPCOUNT, + .ddrpsc_num = DA8XX_LPSC1_EMIF3C, +}; + +static void davinci_sram_push(void *dest, void *src, unsigned int size) +{ + memcpy(dest, src, size); + flush_icache_range((unsigned long)dest, (unsigned long)(dest + size)); +} + +static void davinci_pm_suspend(void) +{ + unsigned val; + + if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) { + + /* Switch CPU PLL to bypass mode */ + val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); + val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); + __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); + + udelay(PLL_BYPASS_TIME); + + /* Powerdown CPU PLL */ + val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); + val |= PLLCTL_PLLPWRDN; + __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); + } + + /* Configure sleep count in deep sleep register */ + val = __raw_readl(pm_config.deepsleep_reg); + val &= ~DEEPSLEEP_SLEEPCOUNT_MASK, + val |= pm_config.sleepcount; + __raw_writel(val, pm_config.deepsleep_reg); + + /* System goes to sleep in this call */ + davinci_sram_suspend(&pm_config); + + if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) { + + /* put CPU PLL in reset */ + val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); + val &= ~PLLCTL_PLLRST; + __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); + + /* put CPU PLL in power down */ + val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); + val &= ~PLLCTL_PLLPWRDN; + __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); + + /* wait for CPU PLL reset */ + udelay(PLL_RESET_TIME); + + /* bring CPU PLL out of reset */ + val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); + val |= PLLCTL_PLLRST; + __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); + + /* Wait for CPU PLL to lock */ + udelay(PLL_LOCK_TIME); + + /* Remove CPU PLL from bypass mode */ + val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); + val &= ~PLLCTL_PLLENSRC; + val |= PLLCTL_PLLEN; + __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); + } +} + +static int davinci_pm_enter(suspend_state_t state) +{ + int ret = 0; + + switch (state) { + case PM_SUSPEND_MEM: + davinci_pm_suspend(); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct platform_suspend_ops davinci_pm_ops = { + .enter = davinci_pm_enter, + .valid = suspend_valid_only_mem, +}; + +int __init davinci_pm_init(void) +{ + int ret; + + ret = davinci_cfg_reg(DA850_RTC_ALARM); + if (ret) + return ret; + + pm_config.ddr2_ctlr_base = da8xx_get_mem_ctlr(); + pm_config.deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG); + + pm_config.cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K); + if (!pm_config.cpupll_reg_base) + return -ENOMEM; + + pm_config.ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K); + if (!pm_config.ddrpll_reg_base) { + ret = -ENOMEM; + goto no_ddrpll_mem; + } + + pm_config.ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K); + if (!pm_config.ddrpsc_reg_base) { + ret = -ENOMEM; + goto no_ddrpsc_mem; + } + + davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL); + if (!davinci_sram_suspend) { + pr_err("PM: cannot allocate SRAM memory\n"); + ret = -ENOMEM; + goto no_sram_mem; + } + + davinci_sram_push(davinci_sram_suspend, davinci_cpu_suspend, + davinci_cpu_suspend_sz); + + suspend_set_ops(&davinci_pm_ops); + + return 0; + +no_sram_mem: + iounmap(pm_config.ddrpsc_reg_base); +no_ddrpsc_mem: + iounmap(pm_config.ddrpll_reg_base); +no_ddrpll_mem: + iounmap(pm_config.cpupll_reg_base); + return ret; +} diff --git a/arch/arm/mach-davinci/pm.h b/arch/arm/mach-davinci/pm.h new file mode 100644 index 0000000000..6f50d6eb8d --- /dev/null +++ b/arch/arm/mach-davinci/pm.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * TI DaVinci platform support for power management. + * + * Copyright (C) 2009 Texas Instruments, Inc. https://www.ti.com/ + */ +#ifndef _MACH_DAVINCI_PM_H +#define _MACH_DAVINCI_PM_H + +/* + * Caution: Assembly code in sleep.S makes assumtion on the order + * of the members of this structure. + */ +struct davinci_pm_config { + void __iomem *ddr2_ctlr_base; + void __iomem *ddrpsc_reg_base; + int ddrpsc_num; + void __iomem *ddrpll_reg_base; + void __iomem *deepsleep_reg; + void __iomem *cpupll_reg_base; + /* + * Note on SLEEPCOUNT: + * The SLEEPCOUNT feature is mainly intended for cases in which + * the internal oscillator is used. The internal oscillator is + * fully disabled in deep sleep mode. When you exist deep sleep + * mode, the oscillator will be turned on and will generate very + * small oscillations which will not be detected by the deep sleep + * counter. Eventually those oscillations will grow to an amplitude + * large enough to start incrementing the deep sleep counter. + * In this case recommendation from hardware engineers is that the + * SLEEPCOUNT be set to 4096. This means that 4096 valid clock cycles + * must be detected before the clock is passed to the rest of the + * system. + * In the case that the internal oscillator is not used and the + * clock is generated externally, the SLEEPCOUNT value can be very + * small since the clock input is assumed to be stable before SoC + * is taken out of deepsleep mode. A value of 128 would be more than + * adequate. + */ + int sleepcount; +}; + +extern unsigned int davinci_cpu_suspend_sz; +extern void davinci_cpu_suspend(struct davinci_pm_config *); + +#endif diff --git a/arch/arm/mach-davinci/pm_domain.c b/arch/arm/mach-davinci/pm_domain.c new file mode 100644 index 0000000000..6b21d5bd99 --- /dev/null +++ b/arch/arm/mach-davinci/pm_domain.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Runtime PM support code for DaVinci + * + * Author: Kevin Hilman + * + * Copyright (C) 2012 Texas Instruments, Inc. + */ +#include <linux/init.h> +#include <linux/pm_runtime.h> +#include <linux/pm_clock.h> +#include <linux/platform_device.h> +#include <linux/of.h> + +static struct dev_pm_domain davinci_pm_domain = { + .ops = { + USE_PM_CLK_RUNTIME_OPS + USE_PLATFORM_PM_SLEEP_OPS + }, +}; + +static struct pm_clk_notifier_block platform_bus_notifier = { + .pm_domain = &davinci_pm_domain, + .con_ids = { "fck", "master", "slave", NULL }, +}; + +static int __init davinci_pm_runtime_init(void) +{ + if (of_have_populated_dt()) + return 0; + + /* Use pm_clk as fallback if we're not using genpd. */ + pm_clk_add_notifier(&platform_bus_type, &platform_bus_notifier); + + return 0; +} +core_initcall(davinci_pm_runtime_init); diff --git a/arch/arm/mach-davinci/psc.h b/arch/arm/mach-davinci/psc.h new file mode 100644 index 0000000000..acfef06329 --- /dev/null +++ b/arch/arm/mach-davinci/psc.h @@ -0,0 +1,143 @@ +/* + * DaVinci Power & Sleep Controller (PSC) defines + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#ifndef __ASM_ARCH_PSC_H +#define __ASM_ARCH_PSC_H + +/* Power and Sleep Controller (PSC) Domains */ +#define DAVINCI_GPSC_ARMDOMAIN 0 +#define DAVINCI_GPSC_DSPDOMAIN 1 + +#define DAVINCI_LPSC_VPSSMSTR 0 +#define DAVINCI_LPSC_VPSSSLV 1 +#define DAVINCI_LPSC_TPCC 2 +#define DAVINCI_LPSC_TPTC0 3 +#define DAVINCI_LPSC_TPTC1 4 +#define DAVINCI_LPSC_EMAC 5 +#define DAVINCI_LPSC_EMAC_WRAPPER 6 +#define DAVINCI_LPSC_USB 9 +#define DAVINCI_LPSC_ATA 10 +#define DAVINCI_LPSC_VLYNQ 11 +#define DAVINCI_LPSC_UHPI 12 +#define DAVINCI_LPSC_DDR_EMIF 13 +#define DAVINCI_LPSC_AEMIF 14 +#define DAVINCI_LPSC_MMC_SD 15 +#define DAVINCI_LPSC_McBSP 17 +#define DAVINCI_LPSC_I2C 18 +#define DAVINCI_LPSC_UART0 19 +#define DAVINCI_LPSC_UART1 20 +#define DAVINCI_LPSC_UART2 21 +#define DAVINCI_LPSC_SPI 22 +#define DAVINCI_LPSC_PWM0 23 +#define DAVINCI_LPSC_PWM1 24 +#define DAVINCI_LPSC_PWM2 25 +#define DAVINCI_LPSC_GPIO 26 +#define DAVINCI_LPSC_TIMER0 27 +#define DAVINCI_LPSC_TIMER1 28 +#define DAVINCI_LPSC_TIMER2 29 +#define DAVINCI_LPSC_SYSTEM_SUBSYS 30 +#define DAVINCI_LPSC_ARM 31 +#define DAVINCI_LPSC_SCR2 32 +#define DAVINCI_LPSC_SCR3 33 +#define DAVINCI_LPSC_SCR4 34 +#define DAVINCI_LPSC_CROSSBAR 35 +#define DAVINCI_LPSC_CFG27 36 +#define DAVINCI_LPSC_CFG3 37 +#define DAVINCI_LPSC_CFG5 38 +#define DAVINCI_LPSC_GEM 39 +#define DAVINCI_LPSC_IMCOP 40 + +/* PSC0 defines */ +#define DA8XX_LPSC0_TPCC 0 +#define DA8XX_LPSC0_TPTC0 1 +#define DA8XX_LPSC0_TPTC1 2 +#define DA8XX_LPSC0_EMIF25 3 +#define DA8XX_LPSC0_SPI0 4 +#define DA8XX_LPSC0_MMC_SD 5 +#define DA8XX_LPSC0_AINTC 6 +#define DA8XX_LPSC0_ARM_RAM_ROM 7 +#define DA8XX_LPSC0_SECU_MGR 8 +#define DA8XX_LPSC0_UART0 9 +#define DA8XX_LPSC0_SCR0_SS 10 +#define DA8XX_LPSC0_SCR1_SS 11 +#define DA8XX_LPSC0_SCR2_SS 12 +#define DA8XX_LPSC0_PRUSS 13 +#define DA8XX_LPSC0_ARM 14 +#define DA8XX_LPSC0_GEM 15 + +/* PSC1 defines */ +#define DA850_LPSC1_TPCC1 0 +#define DA8XX_LPSC1_USB20 1 +#define DA8XX_LPSC1_USB11 2 +#define DA8XX_LPSC1_GPIO 3 +#define DA8XX_LPSC1_UHPI 4 +#define DA8XX_LPSC1_CPGMAC 5 +#define DA8XX_LPSC1_EMIF3C 6 +#define DA8XX_LPSC1_McASP0 7 +#define DA830_LPSC1_McASP1 8 +#define DA850_LPSC1_SATA 8 +#define DA830_LPSC1_McASP2 9 +#define DA850_LPSC1_VPIF 9 +#define DA8XX_LPSC1_SPI1 10 +#define DA8XX_LPSC1_I2C 11 +#define DA8XX_LPSC1_UART1 12 +#define DA8XX_LPSC1_UART2 13 +#define DA850_LPSC1_McBSP0 14 +#define DA850_LPSC1_McBSP1 15 +#define DA8XX_LPSC1_LCDC 16 +#define DA8XX_LPSC1_PWM 17 +#define DA850_LPSC1_MMC_SD1 18 +#define DA8XX_LPSC1_ECAP 20 +#define DA830_LPSC1_EQEP 21 +#define DA850_LPSC1_TPTC2 21 +#define DA8XX_LPSC1_SCR_P0_SS 24 +#define DA8XX_LPSC1_SCR_P1_SS 25 +#define DA8XX_LPSC1_CR_P3_SS 26 +#define DA8XX_LPSC1_L3_CBA_RAM 31 + +/* PSC register offsets */ +#define EPCPR 0x070 +#define PTCMD 0x120 +#define PTSTAT 0x128 +#define PDSTAT 0x200 +#define PDCTL 0x300 +#define MDSTAT 0x800 +#define MDCTL 0xA00 + +/* PSC module states */ +#define PSC_STATE_SWRSTDISABLE 0 +#define PSC_STATE_SYNCRST 1 +#define PSC_STATE_DISABLE 2 +#define PSC_STATE_ENABLE 3 + +#define MDSTAT_STATE_MASK 0x3f +#define PDSTAT_STATE_MASK 0x1f +#define MDCTL_LRST BIT(8) +#define MDCTL_FORCE BIT(31) +#define PDCTL_NEXT BIT(0) +#define PDCTL_EPCGOOD BIT(8) + +#endif /* __ASM_ARCH_PSC_H */ diff --git a/arch/arm/mach-davinci/sleep.S b/arch/arm/mach-davinci/sleep.S new file mode 100644 index 0000000000..d5affab439 --- /dev/null +++ b/arch/arm/mach-davinci/sleep.S @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * (C) Copyright 2009, Texas Instruments, Inc. https://www.ti.com/ + */ + +/* replicated define because linux/bitops.h cannot be included in assembly */ +#define BIT(nr) (1 << (nr)) + +#include <linux/linkage.h> +#include <asm/assembler.h> +#include "psc.h" +#include "ddr2.h" + +#include "clock.h" + +/* Arbitrary, hardware currently does not update PHYRDY correctly */ +#define PHYRDY_CYCLES 0x1000 + +/* Assume 25 MHz speed for the cycle conversions since PLLs are bypassed */ +#define PLL_BYPASS_CYCLES (PLL_BYPASS_TIME * 25) +#define PLL_RESET_CYCLES (PLL_RESET_TIME * 25) +#define PLL_LOCK_CYCLES (PLL_LOCK_TIME * 25) + +#define DEEPSLEEP_SLEEPENABLE_BIT BIT(31) + + .text + .arch armv5te +/* + * Move DaVinci into deep sleep state + * + * Note: This code is copied to internal SRAM by PM code. When the DaVinci + * wakes up it continues execution at the point it went to sleep. + * Register Usage: + * r0: contains virtual base for DDR2 controller + * r1: contains virtual base for DDR2 Power and Sleep controller (PSC) + * r2: contains PSC number for DDR2 + * r3: contains virtual base DDR2 PLL controller + * r4: contains virtual address of the DEEPSLEEP register + */ +ENTRY(davinci_cpu_suspend) + stmfd sp!, {r0-r12, lr} @ save registers on stack + + ldr ip, CACHE_FLUSH + blx ip + + ldmia r0, {r0-r4} + + /* + * Switch DDR to self-refresh mode. + */ + + /* calculate SDRCR address */ + ldr ip, [r0, #DDR2_SDRCR_OFFSET] + bic ip, ip, #DDR2_SRPD_BIT + orr ip, ip, #DDR2_LPMODEN_BIT + str ip, [r0, #DDR2_SDRCR_OFFSET] + + ldr ip, [r0, #DDR2_SDRCR_OFFSET] + orr ip, ip, #DDR2_MCLKSTOPEN_BIT + str ip, [r0, #DDR2_SDRCR_OFFSET] + + mov ip, #PHYRDY_CYCLES +1: subs ip, ip, #0x1 + bne 1b + + /* Disable DDR2 LPSC */ + mov r7, r0 + mov r0, #0x2 + bl davinci_ddr_psc_config + mov r0, r7 + + /* Disable clock to DDR PHY */ + ldr ip, [r3, #PLLDIV1] + bic ip, ip, #PLLDIV_EN + str ip, [r3, #PLLDIV1] + + /* Put the DDR PLL in bypass and power down */ + ldr ip, [r3, #PLLCTL] + bic ip, ip, #PLLCTL_PLLENSRC + bic ip, ip, #PLLCTL_PLLEN + str ip, [r3, #PLLCTL] + + /* Wait for PLL to switch to bypass */ + mov ip, #PLL_BYPASS_CYCLES +2: subs ip, ip, #0x1 + bne 2b + + /* Power down the PLL */ + ldr ip, [r3, #PLLCTL] + orr ip, ip, #PLLCTL_PLLPWRDN + str ip, [r3, #PLLCTL] + + /* Go to deep sleep */ + ldr ip, [r4] + orr ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT + /* System goes to sleep beyond after this instruction */ + str ip, [r4] + + /* Wake up from sleep */ + + /* Clear sleep enable */ + ldr ip, [r4] + bic ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT + str ip, [r4] + + /* initialize the DDR PLL controller */ + + /* Put PLL in reset */ + ldr ip, [r3, #PLLCTL] + bic ip, ip, #PLLCTL_PLLRST + str ip, [r3, #PLLCTL] + + /* Clear PLL power down */ + ldr ip, [r3, #PLLCTL] + bic ip, ip, #PLLCTL_PLLPWRDN + str ip, [r3, #PLLCTL] + + mov ip, #PLL_RESET_CYCLES +3: subs ip, ip, #0x1 + bne 3b + + /* Bring PLL out of reset */ + ldr ip, [r3, #PLLCTL] + orr ip, ip, #PLLCTL_PLLRST + str ip, [r3, #PLLCTL] + + /* Wait for PLL to lock (assume prediv = 1, 25MHz OSCIN) */ + mov ip, #PLL_LOCK_CYCLES +4: subs ip, ip, #0x1 + bne 4b + + /* Remove PLL from bypass mode */ + ldr ip, [r3, #PLLCTL] + bic ip, ip, #PLLCTL_PLLENSRC + orr ip, ip, #PLLCTL_PLLEN + str ip, [r3, #PLLCTL] + + /* Start 2x clock to DDR2 */ + + ldr ip, [r3, #PLLDIV1] + orr ip, ip, #PLLDIV_EN + str ip, [r3, #PLLDIV1] + + /* Enable VCLK */ + + /* Enable DDR2 LPSC */ + mov r7, r0 + mov r0, #0x3 + bl davinci_ddr_psc_config + mov r0, r7 + + /* clear MCLKSTOPEN */ + + ldr ip, [r0, #DDR2_SDRCR_OFFSET] + bic ip, ip, #DDR2_MCLKSTOPEN_BIT + str ip, [r0, #DDR2_SDRCR_OFFSET] + + ldr ip, [r0, #DDR2_SDRCR_OFFSET] + bic ip, ip, #DDR2_LPMODEN_BIT + str ip, [r0, #DDR2_SDRCR_OFFSET] + + /* Restore registers and return */ + ldmfd sp!, {r0-r12, pc} + +ENDPROC(davinci_cpu_suspend) + +/* + * Disables or Enables DDR2 LPSC + * Register Usage: + * r0: Enable or Disable LPSC r0 = 0x3 => Enable, r0 = 0x2 => Disable LPSC + * r1: contains virtual base for DDR2 Power and Sleep controller (PSC) + * r2: contains PSC number for DDR2 + */ +ENTRY(davinci_ddr_psc_config) + /* Set next state in mdctl for DDR2 */ + mov r6, #MDCTL + add r6, r6, r2, lsl #2 + ldr ip, [r1, r6] + bic ip, ip, #MDSTAT_STATE_MASK + orr ip, ip, r0 + str ip, [r1, r6] + + /* Enable the Power Domain Transition Command */ + ldr ip, [r1, #PTCMD] + orr ip, ip, #0x1 + str ip, [r1, #PTCMD] + + /* Check for Transition Complete (PTSTAT) */ +ptstat_done: + ldr ip, [r1, #PTSTAT] + and ip, ip, #0x1 + cmp ip, #0x0 + bne ptstat_done + + /* Check for DDR2 clock disable completion; */ + mov r6, #MDSTAT + add r6, r6, r2, lsl #2 +ddr2clk_stop_done: + ldr ip, [r1, r6] + and ip, ip, #MDSTAT_STATE_MASK + cmp ip, r0 + bne ddr2clk_stop_done + + ret lr +ENDPROC(davinci_ddr_psc_config) + +CACHE_FLUSH: +#ifdef CONFIG_CPU_V6 + .word v6_flush_kern_cache_all +#else + .word arm926_flush_kern_cache_all +#endif + +ENTRY(davinci_cpu_suspend_sz) + .word . - davinci_cpu_suspend +ENDPROC(davinci_cpu_suspend_sz) diff --git a/arch/arm/mach-davinci/sram.c b/arch/arm/mach-davinci/sram.c new file mode 100644 index 0000000000..d04f39fc84 --- /dev/null +++ b/arch/arm/mach-davinci/sram.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * mach-davinci/sram.c - DaVinci simple SRAM allocator + * + * Copyright (C) 2009 David Brownell + */ +#include <linux/module.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/genalloc.h> + +#include "common.h" +#include "sram.h" + +static struct gen_pool *sram_pool; + +struct gen_pool *sram_get_gen_pool(void) +{ + return sram_pool; +} + +void *sram_alloc(size_t len, dma_addr_t *dma) +{ + dma_addr_t dma_base = davinci_soc_info.sram_dma; + + if (dma) + *dma = 0; + if (!sram_pool || (dma && !dma_base)) + return NULL; + + return gen_pool_dma_alloc(sram_pool, len, dma); + +} +EXPORT_SYMBOL(sram_alloc); + +void sram_free(void *addr, size_t len) +{ + gen_pool_free(sram_pool, (unsigned long) addr, len); +} +EXPORT_SYMBOL(sram_free); + + +/* + * REVISIT This supports CPU and DMA access to/from SRAM, but it + * doesn't (yet?) support some other notable uses of SRAM: as TCM + * for data and/or instructions; and holding code needed to enter + * and exit suspend states (while DRAM can't be used). + */ +static int __init sram_init(void) +{ + phys_addr_t phys = davinci_soc_info.sram_dma; + unsigned len = davinci_soc_info.sram_len; + int status = 0; + void __iomem *addr; + + if (len) { + len = min_t(unsigned, len, SRAM_SIZE); + sram_pool = gen_pool_create(ilog2(SRAM_GRANULARITY), -1); + if (!sram_pool) + status = -ENOMEM; + } + + if (sram_pool) { + addr = ioremap(phys, len); + if (!addr) + return -ENOMEM; + status = gen_pool_add_virt(sram_pool, (unsigned long) addr, + phys, len, -1); + if (status < 0) + iounmap(addr); + } + + WARN_ON(status < 0); + return status; +} +core_initcall(sram_init); + diff --git a/arch/arm/mach-davinci/sram.h b/arch/arm/mach-davinci/sram.h new file mode 100644 index 0000000000..7ef8d1d3c3 --- /dev/null +++ b/arch/arm/mach-davinci/sram.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * mach/sram.h - DaVinci simple SRAM allocator + * + * Copyright (C) 2009 David Brownell + */ +#ifndef __MACH_SRAM_H +#define __MACH_SRAM_H + +/* ARBITRARY: SRAM allocations are multiples of this 2^N size */ +#define SRAM_GRANULARITY 512 + +/* + * SRAM allocations return a CPU virtual address, or NULL on error. + * If a DMA address is requested and the SRAM supports DMA, its + * mapped address is also returned. + * + * Errors include SRAM memory not being available, and requesting + * DMA mapped SRAM on systems which don't allow that. + */ +extern void *sram_alloc(size_t len, dma_addr_t *dma); +extern void sram_free(void *addr, size_t len); + +/* Get the struct gen_pool * for use in platform data */ +extern struct gen_pool *sram_get_gen_pool(void); + +#endif /* __MACH_SRAM_H */ |