diff options
Diffstat (limited to 'arch/arm/mach-mmp')
| -rw-r--r-- | arch/arm/mach-mmp/Kconfig | 79 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/Makefile | 14 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/addr-map.h | 48 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/common.c | 60 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/common.h | 7 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/mmp-dt.c | 45 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/mmp2-dt.c | 34 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/mmp3.c | 25 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/platsmp.c | 32 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/regs-timers.h | 34 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/time.c | 221 |
11 files changed, 599 insertions, 0 deletions
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig new file mode 100644 index 0000000000..8c1d4402fd --- /dev/null +++ b/arch/arm/mach-mmp/Kconfig @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0-only +menuconfig ARCH_MMP + bool "Marvell PXA168/910/MMP2/MMP3" + depends on (CPU_LITTLE_ENDIAN && ARCH_MULTI_V5) || ARCH_MULTI_V7 + select GPIO_PXA + select GPIOLIB + select PINCTRL + select PLAT_PXA + help + Support for Marvell's PXA168/PXA910(MMP), MMP2, and MMP3 processor lines. + +if ARCH_MMP + +menu "Marvell PXA168/910/MMP2 Implementations" + +config MACH_MMP_DT + bool "Support MMP (ARMv5) platforms from device tree" + depends on ARCH_MULTI_V5 + select PINCTRL + select PINCTRL_SINGLE + select ARCH_HAS_RESET_CONTROLLER + select CPU_MOHAWK + help + Include support for Marvell MMP2 based platforms using + the device tree. Needn't select any other machine while + MACH_MMP_DT is enabled. + +config MACH_MMP2_DT + bool "Support MMP2 (ARMv7) platforms from device tree" + depends on ARCH_MULTI_V7 + select PINCTRL + select PINCTRL_SINGLE + select ARCH_HAS_RESET_CONTROLLER + select CPU_PJ4 + select PM_GENERIC_DOMAINS if PM + select PM_GENERIC_DOMAINS_OF if PM && OF + help + Include support for Marvell MMP2 based platforms using + the device tree. + +config MACH_MMP3_DT + bool "Support MMP3 (ARMv7) platforms" + depends on ARCH_MULTI_V7 + select ARM_GIC + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if SMP + select CACHE_L2X0 + select PINCTRL + select PINCTRL_SINGLE + select ARCH_HAS_RESET_CONTROLLER + select CPU_PJ4B + select PM_GENERIC_DOMAINS if PM + select PM_GENERIC_DOMAINS_OF if PM && OF + help + Say 'Y' here if you want to include support for platforms + with Marvell MMP3 processor, also known as PXA2128 or + Armada 620. + +endmenu + +config CPU_PXA168 + bool + select CPU_MOHAWK + help + Select code specific to PXA168 + +config CPU_PXA910 + bool + select CPU_MOHAWK + help + Select code specific to PXA910 + +config CPU_MMP2 + bool + select CPU_PJ4 + help + Select code specific to MMP2. MMP2 is ARMv7 compatible. + +endif diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile new file mode 100644 index 0000000000..5d4a1a4a48 --- /dev/null +++ b/arch/arm/mach-mmp/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for Marvell's PXA168 processors line +# +obj-y += common.o time.o + +ifeq ($(CONFIG_SMP),y) +obj-$(CONFIG_MACH_MMP3_DT) += platsmp.o +endif + +# board support +obj-$(CONFIG_MACH_MMP_DT) += mmp-dt.o +obj-$(CONFIG_MACH_MMP2_DT) += mmp2-dt.o +obj-$(CONFIG_MACH_MMP3_DT) += mmp3.o diff --git a/arch/arm/mach-mmp/addr-map.h b/arch/arm/mach-mmp/addr-map.h new file mode 100644 index 0000000000..3dc2f0b0ec --- /dev/null +++ b/arch/arm/mach-mmp/addr-map.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Common address map definitions + */ + +#ifndef __ASM_MACH_ADDR_MAP_H +#define __ASM_MACH_ADDR_MAP_H + +/* APB - Application Subsystem Peripheral Bus + * + * NOTE: the DMA controller registers are actually on the AXI fabric #1 + * slave port to AHB/APB bridge, due to its close relationship to those + * peripherals on APB, let's count it into the ABP mapping area. + */ +#define APB_PHYS_BASE 0xd4000000 +#define APB_VIRT_BASE IOMEM(0xfe000000) +#define APB_PHYS_SIZE 0x00200000 + +#define AXI_PHYS_BASE 0xd4200000 +#define AXI_VIRT_BASE IOMEM(0xfe200000) +#define AXI_PHYS_SIZE 0x00200000 + +#define PGU_PHYS_BASE 0xe0000000 +#define PGU_VIRT_BASE IOMEM(0xfe400000) +#define PGU_PHYS_SIZE 0x00100000 + +/* Static Memory Controller - Chip Select 0 and 1 */ +#define SMC_CS0_PHYS_BASE 0x80000000 +#define SMC_CS0_PHYS_SIZE 0x10000000 +#define SMC_CS1_PHYS_BASE 0x90000000 +#define SMC_CS1_PHYS_SIZE 0x10000000 + +#define APMU_VIRT_BASE (AXI_VIRT_BASE + 0x82800) +#define APMU_REG(x) (APMU_VIRT_BASE + (x)) + +#define APBC_VIRT_BASE (APB_VIRT_BASE + 0x015000) +#define APBC_REG(x) (APBC_VIRT_BASE + (x)) + +#define MPMU_VIRT_BASE (APB_VIRT_BASE + 0x50000) +#define MPMU_REG(x) (MPMU_VIRT_BASE + (x)) + +#define CIU_VIRT_BASE (AXI_VIRT_BASE + 0x82c00) +#define CIU_REG(x) (CIU_VIRT_BASE + (x)) + +#define SCU_VIRT_BASE (PGU_VIRT_BASE) +#define SCU_REG(x) (SCU_VIRT_BASE + (x)) + +#endif /* __ASM_MACH_ADDR_MAP_H */ diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c new file mode 100644 index 0000000000..b3c1a248db --- /dev/null +++ b/arch/arm/mach-mmp/common.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/arch/arm/mach-mmp/common.c + * + * Code common to PXA168 processor lines + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> + +#include <asm/page.h> +#include <asm/mach/map.h> +#include <asm/system_misc.h> +#include "addr-map.h" +#include <linux/soc/mmp/cputype.h> + +#include "common.h" + +#define MMP_CHIPID CIU_REG(0x00) + +unsigned int mmp_chip_id; +EXPORT_SYMBOL(mmp_chip_id); + +static struct map_desc standard_io_desc[] __initdata = { + { + .pfn = __phys_to_pfn(APB_PHYS_BASE), + .virtual = (unsigned long)APB_VIRT_BASE, + .length = APB_PHYS_SIZE, + .type = MT_DEVICE, + }, { + .pfn = __phys_to_pfn(AXI_PHYS_BASE), + .virtual = (unsigned long)AXI_VIRT_BASE, + .length = AXI_PHYS_SIZE, + .type = MT_DEVICE, + }, +}; + +static struct map_desc mmp2_io_desc[] __initdata = { + { + .pfn = __phys_to_pfn(PGU_PHYS_BASE), + .virtual = (unsigned long)PGU_VIRT_BASE, + .length = PGU_PHYS_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init mmp_map_io(void) +{ + iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); + + /* this is early, initialize mmp_chip_id here */ + mmp_chip_id = __raw_readl(MMP_CHIPID); +} + +void __init mmp2_map_io(void) +{ + mmp_map_io(); + iotable_init(mmp2_io_desc, ARRAY_SIZE(mmp2_io_desc)); +} diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h new file mode 100644 index 0000000000..e18f05d5d6 --- /dev/null +++ b/arch/arm/mach-mmp/common.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include <linux/reboot.h> + +extern void mmp_timer_init(int irq, unsigned long rate); + +extern void __init mmp_map_io(void); +extern void __init mmp2_map_io(void); diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c new file mode 100644 index 0000000000..8479996a8f --- /dev/null +++ b/arch/arm/mach-mmp/mmp-dt.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/arch/arm/mach-mmp/mmp-dt.c + * + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Author: Haojian Zhuang <haojian.zhuang@marvell.com> + */ + +#include <linux/of_clk.h> +#include <linux/clocksource.h> +#include <asm/mach/arch.h> +#include <asm/hardware/cache-tauros2.h> + +#include "common.h" + +static const char *const pxa168_dt_board_compat[] __initconst = { + "mrvl,pxa168-aspenite", + NULL, +}; + +static const char *const pxa910_dt_board_compat[] __initconst = { + "mrvl,pxa910-dkb", + NULL, +}; + +static void __init mmp_init_time(void) +{ +#ifdef CONFIG_CACHE_TAUROS2 + tauros2_init(0); +#endif + of_clk_init(NULL); + timer_probe(); +} + +DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)") + .map_io = mmp_map_io, + .init_time = mmp_init_time, + .dt_compat = pxa168_dt_board_compat, +MACHINE_END + +DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)") + .map_io = mmp_map_io, + .init_time = mmp_init_time, + .dt_compat = pxa910_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c new file mode 100644 index 0000000000..e5ddc32765 --- /dev/null +++ b/arch/arm/mach-mmp/mmp2-dt.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/arch/arm/mach-mmp/mmp2-dt.c + * + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Author: Haojian Zhuang <haojian.zhuang@marvell.com> + */ + +#include <linux/of_clk.h> +#include <linux/clocksource.h> +#include <asm/mach/arch.h> +#include <asm/hardware/cache-tauros2.h> + +#include "common.h" + +static void __init mmp_init_time(void) +{ +#ifdef CONFIG_CACHE_TAUROS2 + tauros2_init(0); +#endif + of_clk_init(NULL); + timer_probe(); +} + +static const char *const mmp2_dt_board_compat[] __initconst = { + "mrvl,mmp2", + NULL, +}; + +DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)") + .map_io = mmp2_map_io, + .init_time = mmp_init_time, + .dt_compat = mmp2_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-mmp/mmp3.c b/arch/arm/mach-mmp/mmp3.c new file mode 100644 index 0000000000..073a4ee219 --- /dev/null +++ b/arch/arm/mach-mmp/mmp3.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Marvell MMP3 aka PXA2128 aka 88AP2128 support + * + * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk> + */ + +#include <asm/mach/arch.h> +#include <asm/hardware/cache-l2x0.h> + +#include "common.h" + +static const char *const mmp3_dt_board_compat[] __initconst = { + "marvell,mmp3", + NULL, +}; + +DT_MACHINE_START(MMP2_DT, "Marvell MMP3") + .map_io = mmp2_map_io, + .dt_compat = mmp3_dt_board_compat, + .l2c_aux_val = 1 << L310_AUX_CTRL_FWA_SHIFT | + L310_AUX_CTRL_DATA_PREFETCH | + L310_AUX_CTRL_INSTR_PREFETCH, + .l2c_aux_mask = 0xc20fffff, +MACHINE_END diff --git a/arch/arm/mach-mmp/platsmp.c b/arch/arm/mach-mmp/platsmp.c new file mode 100644 index 0000000000..c99405469b --- /dev/null +++ b/arch/arm/mach-mmp/platsmp.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk> + */ +#include <linux/io.h> +#include <asm/smp_scu.h> +#include <asm/smp.h> +#include "addr-map.h" + +#define SW_BRANCH_VIRT_ADDR CIU_REG(0x24) + +static int mmp3_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + /* + * Apparently, the boot ROM on the second core spins on this + * register becoming non-zero and then jumps to the address written + * there. No IPIs involved. + */ + __raw_writel(__pa_symbol(secondary_startup), SW_BRANCH_VIRT_ADDR); + return 0; +} + +static void mmp3_smp_prepare_cpus(unsigned int max_cpus) +{ + scu_enable(SCU_VIRT_BASE); +} + +static const struct smp_operations mmp3_smp_ops __initconst = { + .smp_prepare_cpus = mmp3_smp_prepare_cpus, + .smp_boot_secondary = mmp3_boot_secondary, +}; +CPU_METHOD_OF_DECLARE(mmp3_smp, "marvell,mmp3-smp", &mmp3_smp_ops); diff --git a/arch/arm/mach-mmp/regs-timers.h b/arch/arm/mach-mmp/regs-timers.h new file mode 100644 index 0000000000..0cc4aca40e --- /dev/null +++ b/arch/arm/mach-mmp/regs-timers.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Timers Module + */ + +#ifndef __ASM_MACH_REGS_TIMERS_H +#define __ASM_MACH_REGS_TIMERS_H + +#define TMR_CCR (0x0000) +#define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2)) +#define TMR_CR(n) (0x0028 + ((n) << 2)) +#define TMR_SR(n) (0x0034 + ((n) << 2)) +#define TMR_IER(n) (0x0040 + ((n) << 2)) +#define TMR_PLVR(n) (0x004c + ((n) << 2)) +#define TMR_PLCR(n) (0x0058 + ((n) << 2)) +#define TMR_WMER (0x0064) +#define TMR_WMR (0x0068) +#define TMR_WVR (0x006c) +#define TMR_WSR (0x0070) +#define TMR_ICR(n) (0x0074 + ((n) << 2)) +#define TMR_WICR (0x0080) +#define TMR_CER (0x0084) +#define TMR_CMR (0x0088) +#define TMR_ILR(n) (0x008c + ((n) << 2)) +#define TMR_WCR (0x0098) +#define TMR_WFAR (0x009c) +#define TMR_WSAR (0x00A0) +#define TMR_CVWR(n) (0x00A4 + ((n) << 2)) + +#define TMR_CCR_CS_0(x) (((x) & 0x3) << 0) +#define TMR_CCR_CS_1(x) (((x) & 0x7) << 2) +#define TMR_CCR_CS_2(x) (((x) & 0x3) << 5) + +#endif /* __ASM_MACH_REGS_TIMERS_H */ diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c new file mode 100644 index 0000000000..fcb190826d --- /dev/null +++ b/arch/arm/mach-mmp/time.c @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/arch/arm/mach-mmp/time.c + * + * Support for clocksource and clockevents + * + * Copyright (C) 2008 Marvell International Ltd. + * All rights reserved. + * + * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com> + * 2008-10-08: Bin Yang <bin.yang@marvell.com> + * + * The timers module actually includes three timers, each timer with up to + * three match comparators. Timer #0 is used here in free-running mode as + * the clock source, and match comparator #1 used as clock event device. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/clockchips.h> +#include <linux/clk.h> + +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/sched_clock.h> +#include <asm/mach/time.h> + +#include "regs-timers.h" +#include <linux/soc/mmp/cputype.h> + +#define MAX_DELTA (0xfffffffe) +#define MIN_DELTA (16) + +static void __iomem *mmp_timer_base; + +/* + * Read the timer through the CVWR register. Delay is required after requesting + * a read. The CR register cannot be directly read due to metastability issues + * documented in the PXA168 software manual. + */ +static inline uint32_t timer_read(void) +{ + uint32_t val; + int delay = 3; + + __raw_writel(1, mmp_timer_base + TMR_CVWR(1)); + + while (delay--) + val = __raw_readl(mmp_timer_base + TMR_CVWR(1)); + + return val; +} + +static u64 notrace mmp_read_sched_clock(void) +{ + return timer_read(); +} + +static irqreturn_t timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *c = dev_id; + + /* + * Clear pending interrupt status. + */ + __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); + + /* + * Disable timer 0. + */ + __raw_writel(0x02, mmp_timer_base + TMR_CER); + + c->event_handler(c); + + return IRQ_HANDLED; +} + +static int timer_set_next_event(unsigned long delta, + struct clock_event_device *dev) +{ + unsigned long flags; + + local_irq_save(flags); + + /* + * Disable timer 0. + */ + __raw_writel(0x02, mmp_timer_base + TMR_CER); + + /* + * Clear and enable timer match 0 interrupt. + */ + __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); + __raw_writel(0x01, mmp_timer_base + TMR_IER(0)); + + /* + * Setup new clockevent timer value. + */ + __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0)); + + /* + * Enable timer 0. + */ + __raw_writel(0x03, mmp_timer_base + TMR_CER); + + local_irq_restore(flags); + + return 0; +} + +static int timer_set_shutdown(struct clock_event_device *evt) +{ + unsigned long flags; + + local_irq_save(flags); + /* disable the matching interrupt */ + __raw_writel(0x00, mmp_timer_base + TMR_IER(0)); + local_irq_restore(flags); + + return 0; +} + +static struct clock_event_device ckevt = { + .name = "clockevent", + .features = CLOCK_EVT_FEAT_ONESHOT, + .rating = 200, + .set_next_event = timer_set_next_event, + .set_state_shutdown = timer_set_shutdown, + .set_state_oneshot = timer_set_shutdown, +}; + +static u64 clksrc_read(struct clocksource *cs) +{ + return timer_read(); +} + +static struct clocksource cksrc = { + .name = "clocksource", + .rating = 200, + .read = clksrc_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void __init timer_config(void) +{ + uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR); + + __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */ + + ccr &= (cpu_is_mmp2() || cpu_is_mmp3()) ? + (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) : + (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3)); + __raw_writel(ccr, mmp_timer_base + TMR_CCR); + + /* set timer 0 to periodic mode, and timer 1 to free-running mode */ + __raw_writel(0x2, mmp_timer_base + TMR_CMR); + + __raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */ + __raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */ + __raw_writel(0x0, mmp_timer_base + TMR_IER(0)); + + __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */ + __raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */ + __raw_writel(0x0, mmp_timer_base + TMR_IER(1)); + + /* enable timer 1 counter */ + __raw_writel(0x2, mmp_timer_base + TMR_CER); +} + +static void __init mmp_timer_init(int irq, unsigned long rate) +{ + timer_config(); + + sched_clock_register(mmp_read_sched_clock, 32, rate); + + ckevt.cpumask = cpumask_of(0); + + if (request_irq(irq, timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, + "timer", &ckevt)) + pr_err("Failed to request irq %d (timer)\n", irq); + + clocksource_register_hz(&cksrc, rate); + clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA); +} + +static int __init mmp_dt_init_timer(struct device_node *np) +{ + struct clk *clk; + int irq, ret; + unsigned long rate; + + clk = of_clk_get(np, 0); + if (!IS_ERR(clk)) { + ret = clk_prepare_enable(clk); + if (ret) + return ret; + rate = clk_get_rate(clk); + } else if (cpu_is_pj4()) { + rate = 6500000; + } else { + rate = 3250000; + } + + irq = irq_of_parse_and_map(np, 0); + if (!irq) + return -EINVAL; + + mmp_timer_base = of_iomap(np, 0); + if (!mmp_timer_base) + return -ENOMEM; + + mmp_timer_init(irq, rate); + return 0; +} + +TIMER_OF_DECLARE(mmp_timer, "mrvl,mmp-timer", mmp_dt_init_timer); |