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-rw-r--r--arch/arm64/boot/dts/amazon/alpine-v2.dtsi35
-rw-r--r--arch/arm64/boot/dts/amazon/alpine-v3.dtsi12
2 files changed, 24 insertions, 23 deletions
diff --git a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi
index dbf2dce8d1..da9de49866 100644
--- a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi
+++ b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi
@@ -39,6 +39,7 @@
/ {
model = "Annapurna Labs Alpine v2";
compatible = "al,alpine-v2";
+ interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
@@ -89,6 +90,22 @@
clock-frequency = <1000000>;
};
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a57-pmu";
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -97,22 +114,6 @@
interrupt-parent = <&gic>;
ranges;
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
- };
-
- pmu {
- compatible = "arm,armv8-pmuv3";
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- };
-
gic: interrupt-controller@f0200000 {
compatible = "arm,gic-v3";
reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */
@@ -150,7 +151,7 @@
al,msi-num-spis = <160>;
};
- io-fabric {
+ io-fabric@fc000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi
index 3ea178acdd..8b6156b5af 100644
--- a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi
+++ b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi
@@ -244,7 +244,7 @@
next-level-cache = <&cluster3_l2>;
};
- cluster0_l2: cache@0 {
+ cluster0_l2: cache-0 {
compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
@@ -253,7 +253,7 @@
cache-unified;
};
- cluster1_l2: cache@100 {
+ cluster1_l2: cache-100 {
compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
@@ -262,7 +262,7 @@
cache-unified;
};
- cluster2_l2: cache@200 {
+ cluster2_l2: cache-200 {
compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
@@ -271,7 +271,7 @@
cache-unified;
};
- cluster3_l2: cache@300 {
+ cluster3_l2: cache-300 {
compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
@@ -318,7 +318,7 @@
#size-cells = <2>;
ranges;
- gic: interrupt-controller@f0000000 {
+ gic: interrupt-controller@f0800000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
@@ -361,7 +361,7 @@
interrupt-parent = <&gic>;
};
- io-fabric {
+ io-fabric@fc000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;