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Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi26
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
index cd96f9f75d..aa9f28c443 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
@@ -17,6 +17,32 @@
power-domains = <&pd IMX_SC_R_UART_4>;
};
+ i2c4: i2c@5a840000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x5a840000 0x4000>;
+ interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&i2c4_lpcg 0>,
+ <&i2c4_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_I2C_4>;
+ status = "disabled";
+ };
+
+ i2c4_lpcg: clock-controller@5ac40000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac40000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "i2c4_lpcg_clk",
+ "i2c4_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_4>;
+ };
+
can1_lpcg: clock-controller@5ace0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ace0000 0x10000>;