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-rw-r--r--arch/sh/boards/mach-se/7343/Makefile6
-rw-r--r--arch/sh/boards/mach-se/7343/irq.c123
-rw-r--r--arch/sh/boards/mach-se/7343/setup.c182
3 files changed, 311 insertions, 0 deletions
diff --git a/arch/sh/boards/mach-se/7343/Makefile b/arch/sh/boards/mach-se/7343/Makefile
new file mode 100644
index 0000000000..e058661091
--- /dev/null
+++ b/arch/sh/boards/mach-se/7343/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the 7343 SolutionEngine specific parts of the kernel
+#
+
+obj-y := setup.o irq.o
diff --git a/arch/sh/boards/mach-se/7343/irq.c b/arch/sh/boards/mach-se/7343/irq.c
new file mode 100644
index 0000000000..f9f3b14f70
--- /dev/null
+++ b/arch/sh/boards/mach-se/7343/irq.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Hitachi UL SolutionEngine 7343 FPGA IRQ Support.
+ *
+ * Copyright (C) 2008 Yoshihiro Shimoda
+ * Copyright (C) 2012 Paul Mundt
+ *
+ * Based on linux/arch/sh/boards/se/7343/irq.c
+ * Copyright (C) 2007 Nobuhiro Iwamatsu
+ */
+#define DRV_NAME "SE7343-FPGA"
+#define pr_fmt(fmt) DRV_NAME ": " fmt
+
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/irqdomain.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <mach-se/mach/se7343.h>
+
+#define PA_CPLD_BASE_ADDR 0x11400000
+#define PA_CPLD_ST_REG 0x08 /* CPLD Interrupt status register */
+#define PA_CPLD_IMSK_REG 0x0a /* CPLD Interrupt mask register */
+
+static void __iomem *se7343_irq_regs;
+struct irq_domain *se7343_irq_domain;
+
+static void se7343_irq_demux(struct irq_desc *desc)
+{
+ struct irq_data *data = irq_desc_get_irq_data(desc);
+ struct irq_chip *chip = irq_data_get_irq_chip(data);
+ unsigned long mask;
+ int bit;
+
+ chip->irq_mask_ack(data);
+
+ mask = ioread16(se7343_irq_regs + PA_CPLD_ST_REG);
+
+ for_each_set_bit(bit, &mask, SE7343_FPGA_IRQ_NR)
+ generic_handle_domain_irq(se7343_irq_domain, bit);
+
+ chip->irq_unmask(data);
+}
+
+static void __init se7343_domain_init(void)
+{
+ int i;
+
+ se7343_irq_domain = irq_domain_add_linear(NULL, SE7343_FPGA_IRQ_NR,
+ &irq_domain_simple_ops, NULL);
+ if (unlikely(!se7343_irq_domain)) {
+ printk("Failed to get IRQ domain\n");
+ return;
+ }
+
+ for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {
+ int irq = irq_create_mapping(se7343_irq_domain, i);
+
+ if (unlikely(irq == 0)) {
+ printk("Failed to allocate IRQ %d\n", i);
+ return;
+ }
+ }
+}
+
+static void __init se7343_gc_init(void)
+{
+ struct irq_chip_generic *gc;
+ struct irq_chip_type *ct;
+ unsigned int irq_base;
+
+ irq_base = irq_linear_revmap(se7343_irq_domain, 0);
+
+ gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7343_irq_regs,
+ handle_level_irq);
+ if (unlikely(!gc))
+ return;
+
+ ct = gc->chip_types;
+ ct->chip.irq_mask = irq_gc_mask_set_bit;
+ ct->chip.irq_unmask = irq_gc_mask_clr_bit;
+
+ ct->regs.mask = PA_CPLD_IMSK_REG;
+
+ irq_setup_generic_chip(gc, IRQ_MSK(SE7343_FPGA_IRQ_NR),
+ IRQ_GC_INIT_MASK_CACHE,
+ IRQ_NOREQUEST | IRQ_NOPROBE, 0);
+
+ irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux);
+ irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
+
+ irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux);
+ irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
+
+ irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux);
+ irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
+
+ irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux);
+ irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
+}
+
+/*
+ * Initialize IRQ setting
+ */
+void __init init_7343se_IRQ(void)
+{
+ se7343_irq_regs = ioremap(PA_CPLD_BASE_ADDR, SZ_16);
+ if (unlikely(!se7343_irq_regs)) {
+ pr_err("Failed to remap CPLD\n");
+ return;
+ }
+
+ /*
+ * All FPGA IRQs disabled by default
+ */
+ iowrite16(0, se7343_irq_regs + PA_CPLD_IMSK_REG);
+
+ __raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
+
+ se7343_domain_init();
+ se7343_gc_init();
+}
diff --git a/arch/sh/boards/mach-se/7343/setup.c b/arch/sh/boards/mach-se/7343/setup.c
new file mode 100644
index 0000000000..fe0e550601
--- /dev/null
+++ b/arch/sh/boards/mach-se/7343/setup.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/serial_8250.h>
+#include <linux/serial_reg.h>
+#include <linux/usb/isp116x.h>
+#include <linux/delay.h>
+#include <linux/irqdomain.h>
+#include <asm/machvec.h>
+#include <mach-se/mach/se7343.h>
+#include <asm/heartbeat.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+static struct resource heartbeat_resource = {
+ .start = PA_LED,
+ .end = PA_LED,
+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
+};
+
+static struct platform_device heartbeat_device = {
+ .name = "heartbeat",
+ .id = -1,
+ .num_resources = 1,
+ .resource = &heartbeat_resource,
+};
+
+static struct mtd_partition nor_flash_partitions[] = {
+ {
+ .name = "loader",
+ .offset = 0x00000000,
+ .size = 128 * 1024,
+ },
+ {
+ .name = "rootfs",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 31 * 1024 * 1024,
+ },
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+static struct physmap_flash_data nor_flash_data = {
+ .width = 2,
+ .parts = nor_flash_partitions,
+ .nr_parts = ARRAY_SIZE(nor_flash_partitions),
+};
+
+static struct resource nor_flash_resources[] = {
+ [0] = {
+ .start = 0x00000000,
+ .end = 0x01ffffff,
+ .flags = IORESOURCE_MEM,
+ }
+};
+
+static struct platform_device nor_flash_device = {
+ .name = "physmap-flash",
+ .dev = {
+ .platform_data = &nor_flash_data,
+ },
+ .num_resources = ARRAY_SIZE(nor_flash_resources),
+ .resource = nor_flash_resources,
+};
+
+#define ST16C2550C_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP)
+
+static struct plat_serial8250_port serial_platform_data[] = {
+ [0] = {
+ .iotype = UPIO_MEM,
+ .mapbase = 0x16000000,
+ .regshift = 1,
+ .flags = ST16C2550C_FLAGS,
+ .uartclk = 7372800,
+ },
+ [1] = {
+ .iotype = UPIO_MEM,
+ .mapbase = 0x17000000,
+ .regshift = 1,
+ .flags = ST16C2550C_FLAGS,
+ .uartclk = 7372800,
+ },
+ { },
+};
+
+static struct platform_device uart_device = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM,
+ .dev = {
+ .platform_data = serial_platform_data,
+ },
+};
+
+static void isp116x_delay(struct device *dev, int delay)
+{
+ ndelay(delay);
+}
+
+static struct resource usb_resources[] = {
+ [0] = {
+ .start = 0x11800000,
+ .end = 0x11800001,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 0x11800002,
+ .end = 0x11800003,
+ .flags = IORESOURCE_MEM,
+ },
+ [2] = {
+ /* Filled in later */
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct isp116x_platform_data usb_platform_data = {
+ .sel15Kres = 1,
+ .oc_enable = 1,
+ .int_act_high = 0,
+ .int_edge_triggered = 0,
+ .remote_wakeup_enable = 0,
+ .delay = isp116x_delay,
+};
+
+static struct platform_device usb_device = {
+ .name = "isp116x-hcd",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(usb_resources),
+ .resource = usb_resources,
+ .dev = {
+ .platform_data = &usb_platform_data,
+ },
+
+};
+
+static struct platform_device *sh7343se_platform_devices[] __initdata = {
+ &heartbeat_device,
+ &nor_flash_device,
+ &uart_device,
+ &usb_device,
+};
+
+static int __init sh7343se_devices_setup(void)
+{
+ /* Wire-up dynamic vectors */
+ serial_platform_data[0].irq = irq_find_mapping(se7343_irq_domain,
+ SE7343_FPGA_IRQ_UARTA);
+ serial_platform_data[1].irq = irq_find_mapping(se7343_irq_domain,
+ SE7343_FPGA_IRQ_UARTB);
+ usb_resources[2].start = usb_resources[2].end =
+ irq_find_mapping(se7343_irq_domain, SE7343_FPGA_IRQ_USB);
+
+ return platform_add_devices(sh7343se_platform_devices,
+ ARRAY_SIZE(sh7343se_platform_devices));
+}
+device_initcall(sh7343se_devices_setup);
+
+/*
+ * Initialize the board
+ */
+static void __init sh7343se_setup(char **cmdline_p)
+{
+ __raw_writew(0xf900, FPGA_OUT); /* FPGA */
+
+ __raw_writew(0x0002, PORT_PECR); /* PORT E 1 = IRQ5 */
+ __raw_writew(0x0020, PORT_PSELD);
+
+ printk(KERN_INFO "MS7343CP01 Setup...done\n");
+}
+
+/*
+ * The Machine Vector
+ */
+static struct sh_machine_vector mv_7343se __initmv = {
+ .mv_name = "SolutionEngine 7343",
+ .mv_setup = sh7343se_setup,
+ .mv_init_irq = init_7343se_IRQ,
+};
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-17 04:47:52 +0000