diff options
Diffstat (limited to 'debian/patches/bugfix/x86/platform-x86-p2sb-On-Goldmont-only-cache-P2SB-and-SP.patch')
| -rw-r--r-- | debian/patches/bugfix/x86/platform-x86-p2sb-On-Goldmont-only-cache-P2SB-and-SP.patch | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/debian/patches/bugfix/x86/platform-x86-p2sb-On-Goldmont-only-cache-P2SB-and-SP.patch b/debian/patches/bugfix/x86/platform-x86-p2sb-On-Goldmont-only-cache-P2SB-and-SP.patch new file mode 100644 index 0000000000..50e5f8dc5d --- /dev/null +++ b/debian/patches/bugfix/x86/platform-x86-p2sb-On-Goldmont-only-cache-P2SB-and-SP.patch @@ -0,0 +1,77 @@ +From: Hans de Goede <hdegoede@redhat.com> +Date: Mon, 4 Mar 2024 14:43:55 +0100 +Subject: platform/x86: p2sb: On Goldmont only cache P2SB and SPI devfn BAR +Origin: https://git.kernel.org/linus/aec7d25b497ce4a8d044e9496de0aa433f7f8f06 +Bug-Debian: https://bugs.debian.org/1065320 + +On Goldmont p2sb_bar() only ever gets called for 2 devices, the actual P2SB +devfn 13,0 and the SPI controller which is part of the P2SB, devfn 13,2. + +But the current p2sb code tries to cache BAR0 info for all of +devfn 13,0 to 13,7 . This involves calling pci_scan_single_device() +for device 13 functions 0-7 and the hw does not seem to like +pci_scan_single_device() getting called for some of the other hidden +devices. E.g. on an ASUS VivoBook D540NV-GQ065T this leads to continuous +ACPI errors leading to high CPU usage. + +Fix this by only caching BAR0 info and thus only calling +pci_scan_single_device() for the P2SB and the SPI controller. + +Fixes: 5913320eb0b3 ("platform/x86: p2sb: Allow p2sb_bar() calls during PCI device probe") +Reported-by: Danil Rybakov <danilrybakov249@gmail.com> +Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218531 +Tested-by: Danil Rybakov <danilrybakov249@gmail.com> +Signed-off-by: Hans de Goede <hdegoede@redhat.com> +Link: https://lore.kernel.org/r/20240304134356.305375-2-hdegoede@redhat.com +--- + drivers/platform/x86/p2sb.c | 25 +++++++++---------------- + 1 file changed, 9 insertions(+), 16 deletions(-) + +diff --git a/drivers/platform/x86/p2sb.c b/drivers/platform/x86/p2sb.c +index 6bd14d0132db..3d66e1d4eb1f 100644 +--- a/drivers/platform/x86/p2sb.c ++++ b/drivers/platform/x86/p2sb.c +@@ -20,9 +20,11 @@ + #define P2SBC_HIDE BIT(8) + + #define P2SB_DEVFN_DEFAULT PCI_DEVFN(31, 1) ++#define P2SB_DEVFN_GOLDMONT PCI_DEVFN(13, 0) ++#define SPI_DEVFN_GOLDMONT PCI_DEVFN(13, 2) + + static const struct x86_cpu_id p2sb_cpu_ids[] = { +- X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, PCI_DEVFN(13, 0)), ++ X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, P2SB_DEVFN_GOLDMONT), + {} + }; + +@@ -98,21 +100,12 @@ static void p2sb_scan_and_cache_devfn(struct pci_bus *bus, unsigned int devfn) + + static int p2sb_scan_and_cache(struct pci_bus *bus, unsigned int devfn) + { +- unsigned int slot, fn; +- +- if (PCI_FUNC(devfn) == 0) { +- /* +- * When function number of the P2SB device is zero, scan it and +- * other function numbers, and if devices are available, cache +- * their BAR0s. +- */ +- slot = PCI_SLOT(devfn); +- for (fn = 0; fn < NR_P2SB_RES_CACHE; fn++) +- p2sb_scan_and_cache_devfn(bus, PCI_DEVFN(slot, fn)); +- } else { +- /* Scan the P2SB device and cache its BAR0 */ +- p2sb_scan_and_cache_devfn(bus, devfn); +- } ++ /* Scan the P2SB device and cache its BAR0 */ ++ p2sb_scan_and_cache_devfn(bus, devfn); ++ ++ /* On Goldmont p2sb_bar() also gets called for the SPI controller */ ++ if (devfn == P2SB_DEVFN_GOLDMONT) ++ p2sb_scan_and_cache_devfn(bus, SPI_DEVFN_GOLDMONT); + + if (!p2sb_valid_resource(&p2sb_resources[PCI_FUNC(devfn)].res)) + return -ENOENT; +-- +2.43.0 + |