diff options
Diffstat (limited to 'drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_b_regs.h')
-rw-r--r-- | drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_b_regs.h | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_b_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_b_regs.h new file mode 100644 index 0000000000..a2a2ba454d --- /dev/null +++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_b_regs.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_TENSOR_B + * (Prototype: MME_TENSOR) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_0 0x40CB098 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_1 0x40CB09C + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_2 0x40CB0A0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_3 0x40CB0A4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_4 0x40CB0A8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_0 0x40CB0AC + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_1 0x40CB0B0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_2 0x40CB0B4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_3 0x40CB0B8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_4 0x40CB0BC + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_0 0x40CB0C0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_1 0x40CB0C4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_2 0x40CB0C8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_3 0x40CB0CC + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_0 0x40CB0D0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_1 0x40CB0D4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_2 0x40CB0D8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_3 0x40CB0DC + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_0 0x40CB0E0 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_1 0x40CB0E4 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_2 0x40CB0E8 + +#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_3 0x40CB0EC + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_REGS_H_ */ |