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path: root/drivers/clk/imx/clk-imx6sx.c
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Diffstat (limited to 'drivers/clk/imx/clk-imx6sx.c')
-rw-r--r--drivers/clk/imx/clk-imx6sx.c14
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c
index 3f1502933e..69f8f6f9ca 100644
--- a/drivers/clk/imx/clk-imx6sx.c
+++ b/drivers/clk/imx/clk-imx6sx.c
@@ -121,6 +121,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
{
struct device_node *np;
void __iomem *base;
+ bool lcdif1_assigned_clk;
clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
IMX6SX_CLK_CLK_END), GFP_KERNEL);
@@ -498,9 +499,16 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
clk_set_parent(hws[IMX6SX_CLK_EIM_SLOW_SEL]->clk, hws[IMX6SX_CLK_PLL2_PFD2]->clk);
clk_set_rate(hws[IMX6SX_CLK_EIM_SLOW]->clk, 132000000);
- /* set parent clock for LCDIF1 pixel clock */
- clk_set_parent(hws[IMX6SX_CLK_LCDIF1_PRE_SEL]->clk, hws[IMX6SX_CLK_PLL5_VIDEO_DIV]->clk);
- clk_set_parent(hws[IMX6SX_CLK_LCDIF1_SEL]->clk, hws[IMX6SX_CLK_LCDIF1_PODF]->clk);
+ np = of_find_node_by_path("/soc/bus@2200000/spba-bus@2240000/lcdif@2220000");
+ lcdif1_assigned_clk = of_find_property(np, "assigned-clock-parents", NULL);
+
+ /* Set parent clock for LCDIF1 pixel clock if not done via devicetree */
+ if (!lcdif1_assigned_clk) {
+ clk_set_parent(hws[IMX6SX_CLK_LCDIF1_PRE_SEL]->clk,
+ hws[IMX6SX_CLK_PLL5_VIDEO_DIV]->clk);
+ clk_set_parent(hws[IMX6SX_CLK_LCDIF1_SEL]->clk,
+ hws[IMX6SX_CLK_LCDIF1_PODF]->clk);
+ }
/* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */
if (clk_set_parent(hws[IMX6SX_CLK_LVDS1_SEL]->clk, hws[IMX6SX_CLK_PCIE_REF_125M]->clk))