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-rw-r--r--drivers/clk/renesas/clk-r8a73a4.c2
-rw-r--r--drivers/clk/renesas/clk-r8a7740.c27
-rw-r--r--drivers/clk/renesas/clk-sh73a0.c2
-rw-r--r--drivers/clk/renesas/r8a779h0-cpg-mssr.c21
-rw-r--r--drivers/clk/renesas/r9a07g043-cpg.c4
-rw-r--r--drivers/clk/renesas/r9a07g044-cpg.c2
-rw-r--r--drivers/clk/renesas/r9a08g045-cpg.c41
-rw-r--r--drivers/clk/renesas/rzg2l-cpg.c199
-rw-r--r--drivers/clk/renesas/rzg2l-cpg.h67
9 files changed, 329 insertions, 36 deletions
diff --git a/drivers/clk/renesas/clk-r8a73a4.c b/drivers/clk/renesas/clk-r8a73a4.c
index f45c2c4580..4b1815147f 100644
--- a/drivers/clk/renesas/clk-r8a73a4.c
+++ b/drivers/clk/renesas/clk-r8a73a4.c
@@ -30,8 +30,6 @@ struct r8a73a4_cpg {
#define CPG_PLL2HCR 0xe4
#define CPG_PLL2SCR 0xf4
-#define CLK_ENABLE_ON_INIT BIT(0)
-
struct div4_clk {
const char *name;
unsigned int reg;
diff --git a/drivers/clk/renesas/clk-r8a7740.c b/drivers/clk/renesas/clk-r8a7740.c
index 3ee3f57e4e..22e9be7240 100644
--- a/drivers/clk/renesas/clk-r8a7740.c
+++ b/drivers/clk/renesas/clk-r8a7740.c
@@ -26,28 +26,25 @@ struct r8a7740_cpg {
#define CPG_USBCKCR 0x8c
#define CPG_FRQCRC 0xe0
-#define CLK_ENABLE_ON_INIT BIT(0)
-
struct div4_clk {
const char *name;
unsigned int reg;
unsigned int shift;
- int flags;
};
static struct div4_clk div4_clks[] = {
- { "i", CPG_FRQCRA, 20, CLK_ENABLE_ON_INIT },
- { "zg", CPG_FRQCRA, 16, CLK_ENABLE_ON_INIT },
- { "b", CPG_FRQCRA, 8, CLK_ENABLE_ON_INIT },
- { "m1", CPG_FRQCRA, 4, CLK_ENABLE_ON_INIT },
- { "hp", CPG_FRQCRB, 4, 0 },
- { "hpp", CPG_FRQCRC, 20, 0 },
- { "usbp", CPG_FRQCRC, 16, 0 },
- { "s", CPG_FRQCRC, 12, 0 },
- { "zb", CPG_FRQCRC, 8, 0 },
- { "m3", CPG_FRQCRC, 4, 0 },
- { "cp", CPG_FRQCRC, 0, 0 },
- { NULL, 0, 0, 0 },
+ { "i", CPG_FRQCRA, 20 },
+ { "zg", CPG_FRQCRA, 16 },
+ { "b", CPG_FRQCRA, 8 },
+ { "m1", CPG_FRQCRA, 4 },
+ { "hp", CPG_FRQCRB, 4 },
+ { "hpp", CPG_FRQCRC, 20 },
+ { "usbp", CPG_FRQCRC, 16 },
+ { "s", CPG_FRQCRC, 12 },
+ { "zb", CPG_FRQCRC, 8 },
+ { "m3", CPG_FRQCRC, 4 },
+ { "cp", CPG_FRQCRC, 0 },
+ { NULL, 0, 0 },
};
static const struct clk_div_table div4_div_table[] = {
diff --git a/drivers/clk/renesas/clk-sh73a0.c b/drivers/clk/renesas/clk-sh73a0.c
index 8c51090f13..47fc99ccd2 100644
--- a/drivers/clk/renesas/clk-sh73a0.c
+++ b/drivers/clk/renesas/clk-sh73a0.c
@@ -34,8 +34,6 @@ struct sh73a0_cpg {
#define CPG_DSI0PHYCR 0x6c
#define CPG_DSI1PHYCR 0x70
-#define CLK_ENABLE_ON_INIT BIT(0)
-
struct div4_clk {
const char *name;
const char *parent;
diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
index 71f67a1c86..079b55b30b 100644
--- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
@@ -184,14 +184,35 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
DEF_MOD("i2c1", 519, R8A779H0_CLK_S0D6_PER),
DEF_MOD("i2c2", 520, R8A779H0_CLK_S0D6_PER),
DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER),
+ DEF_MOD("irqc", 611, R8A779H0_CLK_CL16M),
+ DEF_MOD("msi0", 618, R8A779H0_CLK_MSO),
+ DEF_MOD("msi1", 619, R8A779H0_CLK_MSO),
+ DEF_MOD("msi2", 620, R8A779H0_CLK_MSO),
+ DEF_MOD("msi3", 621, R8A779H0_CLK_MSO),
+ DEF_MOD("msi4", 622, R8A779H0_CLK_MSO),
+ DEF_MOD("msi5", 623, R8A779H0_CLK_MSO),
DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2),
+ DEF_MOD("scif0", 702, R8A779H0_CLK_SASYNCPERD4),
+ DEF_MOD("scif1", 703, R8A779H0_CLK_SASYNCPERD4),
+ DEF_MOD("scif3", 704, R8A779H0_CLK_SASYNCPERD4),
+ DEF_MOD("scif4", 705, R8A779H0_CLK_SASYNCPERD4),
DEF_MOD("sdhi0", 706, R8A779H0_CLK_SD0),
DEF_MOD("sydm1", 709, R8A779H0_CLK_S0D6_PER),
DEF_MOD("sydm2", 710, R8A779H0_CLK_S0D6_PER),
+ DEF_MOD("tmu0", 713, R8A779H0_CLK_SASYNCRT),
+ DEF_MOD("tmu1", 714, R8A779H0_CLK_SASYNCPERD2),
+ DEF_MOD("tmu2", 715, R8A779H0_CLK_SASYNCPERD2),
+ DEF_MOD("tmu3", 716, R8A779H0_CLK_SASYNCPERD2),
+ DEF_MOD("tmu4", 717, R8A779H0_CLK_SASYNCPERD2),
DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R),
+ DEF_MOD("cmt0", 910, R8A779H0_CLK_R),
+ DEF_MOD("cmt1", 911, R8A779H0_CLK_R),
+ DEF_MOD("cmt2", 912, R8A779H0_CLK_R),
+ DEF_MOD("cmt3", 913, R8A779H0_CLK_R),
DEF_MOD("pfc0", 915, R8A779H0_CLK_CP),
DEF_MOD("pfc1", 916, R8A779H0_CLK_CP),
DEF_MOD("pfc2", 917, R8A779H0_CLK_CP),
+ DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M),
};
/*
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 26b71547fd..16acc95f3c 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -149,7 +149,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
#endif
};
-static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
+static const struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
#ifdef CONFIG_ARM64
DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,
0x514, 0),
@@ -286,7 +286,7 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
#endif
};
-static struct rzg2l_reset r9a07g043_resets[] = {
+static const struct rzg2l_reset r9a07g043_resets[] = {
#ifdef CONFIG_ARM64
DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 48404cafea..f6df3f7a31 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -368,7 +368,7 @@ static const struct {
#endif
};
-static struct rzg2l_reset r9a07g044_resets[] = {
+static const struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index c3e6da2de1..b068733b14 100644
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -240,6 +240,43 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
};
+static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
+ /* Keep always-on domain on the first position for proper domains registration. */
+ DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON,
+ DEF_REG_CONF(0, 0),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("gic", R9A08G045_PD_GIC,
+ DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("ia55", R9A08G045_PD_IA55,
+ DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("dmac", R9A08G045_PD_DMAC,
+ DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("wdt0", R9A08G045_PD_WDT0,
+ DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("sdhi0", R9A08G045_PD_SDHI0,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("sdhi1", R9A08G045_PD_SDHI1,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("sdhi2", R9A08G045_PD_SDHI2,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("eth0", R9A08G045_PD_ETHER0,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("eth1", R9A08G045_PD_ETHER1,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("scif0", R9A08G045_PD_SCIF0,
+ DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),
+ RZG2L_PD_F_NONE),
+};
+
const struct rzg2l_cpg_info r9a08g045_cpg_info = {
/* Core Clocks */
.core_clks = r9a08g045_core_clks,
@@ -260,5 +297,9 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info = {
.resets = r9a08g045_resets,
.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
+ /* Power domains */
+ .pm_domains = r9a08g045_pm_domains,
+ .num_pm_domains = ARRAY_SIZE(r9a08g045_pm_domains),
+
.has_clk_mon_regs = true,
};
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 3d2daa4ba2..04b78064d4 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -139,7 +139,6 @@ struct rzg2l_pll5_mux_dsi_div_param {
* @num_resets: Number of Module Resets in info->resets[]
* @last_dt_core_clk: ID of the last Core Clock exported to DT
* @info: Pointer to platform data
- * @genpd: PM domain
* @mux_dsi_div_params: pll5 mux and dsi div parameters
*/
struct rzg2l_cpg_priv {
@@ -156,8 +155,6 @@ struct rzg2l_cpg_priv {
const struct rzg2l_cpg_info *info;
- struct generic_pm_domain genpd;
-
struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
};
@@ -1559,9 +1556,34 @@ static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
return true;
}
+/**
+ * struct rzg2l_cpg_pm_domains - RZ/G2L PM domains data structure
+ * @onecell_data: cell data
+ * @domains: generic PM domains
+ */
+struct rzg2l_cpg_pm_domains {
+ struct genpd_onecell_data onecell_data;
+ struct generic_pm_domain *domains[];
+};
+
+/**
+ * struct rzg2l_cpg_pd - RZ/G2L power domain data structure
+ * @genpd: generic PM domain
+ * @priv: pointer to CPG private data structure
+ * @conf: CPG PM domain configuration info
+ * @id: RZ/G2L power domain ID
+ */
+struct rzg2l_cpg_pd {
+ struct generic_pm_domain genpd;
+ struct rzg2l_cpg_priv *priv;
+ struct rzg2l_cpg_pm_domain_conf conf;
+ u16 id;
+};
+
static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
{
- struct rzg2l_cpg_priv *priv = container_of(domain, struct rzg2l_cpg_priv, genpd);
+ struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
+ struct rzg2l_cpg_priv *priv = pd->priv;
struct device_node *np = dev->of_node;
struct of_phandle_args clkspec;
bool once = true;
@@ -1618,30 +1640,179 @@ static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device
static void rzg2l_cpg_genpd_remove(void *data)
{
+ struct genpd_onecell_data *celldata = data;
+
+ for (unsigned int i = 0; i < celldata->num_domains; i++)
+ pm_genpd_remove(celldata->domains[i]);
+}
+
+static void rzg2l_cpg_genpd_remove_simple(void *data)
+{
pm_genpd_remove(data);
}
+static int rzg2l_cpg_power_on(struct generic_pm_domain *domain)
+{
+ struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
+ struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
+ struct rzg2l_cpg_priv *priv = pd->priv;
+
+ /* Set MSTOP. */
+ if (mstop.mask)
+ writel(mstop.mask << 16, priv->base + mstop.off);
+
+ return 0;
+}
+
+static int rzg2l_cpg_power_off(struct generic_pm_domain *domain)
+{
+ struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
+ struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
+ struct rzg2l_cpg_priv *priv = pd->priv;
+
+ /* Set MSTOP. */
+ if (mstop.mask)
+ writel(mstop.mask | (mstop.mask << 16), priv->base + mstop.off);
+
+ return 0;
+}
+
+static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on)
+{
+ struct dev_power_governor *governor;
+
+ pd->genpd.flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
+ pd->genpd.attach_dev = rzg2l_cpg_attach_dev;
+ pd->genpd.detach_dev = rzg2l_cpg_detach_dev;
+ if (always_on) {
+ pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON;
+ governor = &pm_domain_always_on_gov;
+ } else {
+ pd->genpd.power_on = rzg2l_cpg_power_on;
+ pd->genpd.power_off = rzg2l_cpg_power_off;
+ governor = &simple_qos_governor;
+ }
+
+ return pm_genpd_init(&pd->genpd, governor, !always_on);
+}
+
static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv)
{
struct device *dev = priv->dev;
struct device_node *np = dev->of_node;
- struct generic_pm_domain *genpd = &priv->genpd;
+ struct rzg2l_cpg_pd *pd;
+ int ret;
+
+ pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
+ if (!pd)
+ return -ENOMEM;
+
+ pd->genpd.name = np->name;
+ pd->priv = priv;
+ ret = rzg2l_cpg_pd_setup(pd, true);
+ if (ret)
+ return ret;
+
+ ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove_simple, &pd->genpd);
+ if (ret)
+ return ret;
+
+ return of_genpd_add_provider_simple(np, &pd->genpd);
+}
+
+static struct generic_pm_domain *
+rzg2l_cpg_pm_domain_xlate(const struct of_phandle_args *spec, void *data)
+{
+ struct generic_pm_domain *domain = ERR_PTR(-ENOENT);
+ struct genpd_onecell_data *genpd = data;
+
+ if (spec->args_count != 1)
+ return ERR_PTR(-EINVAL);
+
+ for (unsigned int i = 0; i < genpd->num_domains; i++) {
+ struct rzg2l_cpg_pd *pd = container_of(genpd->domains[i], struct rzg2l_cpg_pd,
+ genpd);
+
+ if (pd->id == spec->args[0]) {
+ domain = &pd->genpd;
+ break;
+ }
+ }
+
+ return domain;
+}
+
+static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv)
+{
+ const struct rzg2l_cpg_info *info = priv->info;
+ struct device *dev = priv->dev;
+ struct device_node *np = dev->of_node;
+ struct rzg2l_cpg_pm_domains *domains;
+ struct generic_pm_domain *parent;
+ u32 ncells;
int ret;
- genpd->name = np->name;
- genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
- GENPD_FLAG_ACTIVE_WAKEUP;
- genpd->attach_dev = rzg2l_cpg_attach_dev;
- genpd->detach_dev = rzg2l_cpg_detach_dev;
- ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
+ ret = of_property_read_u32(np, "#power-domain-cells", &ncells);
+ if (ret)
+ return ret;
+
+ /* For backward compatibility. */
+ if (!ncells)
+ return rzg2l_cpg_add_clk_domain(priv);
+
+ domains = devm_kzalloc(dev, struct_size(domains, domains, info->num_pm_domains),
+ GFP_KERNEL);
+ if (!domains)
+ return -ENOMEM;
+
+ domains->onecell_data.domains = domains->domains;
+ domains->onecell_data.num_domains = info->num_pm_domains;
+ domains->onecell_data.xlate = rzg2l_cpg_pm_domain_xlate;
+
+ ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, &domains->onecell_data);
if (ret)
return ret;
- ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, genpd);
+ for (unsigned int i = 0; i < info->num_pm_domains; i++) {
+ bool always_on = !!(info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON);
+ struct rzg2l_cpg_pd *pd;
+
+ pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
+ if (!pd)
+ return -ENOMEM;
+
+ pd->genpd.name = info->pm_domains[i].name;
+ pd->conf = info->pm_domains[i].conf;
+ pd->id = info->pm_domains[i].id;
+ pd->priv = priv;
+
+ ret = rzg2l_cpg_pd_setup(pd, always_on);
+ if (ret)
+ return ret;
+
+ if (always_on) {
+ ret = rzg2l_cpg_power_on(&pd->genpd);
+ if (ret)
+ return ret;
+ }
+
+ domains->domains[i] = &pd->genpd;
+ /* Parent should be on the very first entry of info->pm_domains[]. */
+ if (!i) {
+ parent = &pd->genpd;
+ continue;
+ }
+
+ ret = pm_genpd_add_subdomain(parent, &pd->genpd);
+ if (ret)
+ return ret;
+ }
+
+ ret = of_genpd_add_provider_onecell(np, &domains->onecell_data);
if (ret)
return ret;
- return of_genpd_add_provider_simple(np, genpd);
+ return 0;
}
static int __init rzg2l_cpg_probe(struct platform_device *pdev)
@@ -1697,7 +1868,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
if (error)
return error;
- error = rzg2l_cpg_add_clk_domain(priv);
+ error = rzg2l_cpg_add_pm_domains(priv);
if (error)
return error;
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 6e38c8fc88..ecfe7e7ea8 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -27,6 +27,18 @@
#define CPG_PL6_ETH_SSEL (0x418)
#define CPG_PL5_SDIV (0x420)
#define CPG_RST_MON (0x680)
+#define CPG_BUS_ACPU_MSTOP (0xB60)
+#define CPG_BUS_MCPU1_MSTOP (0xB64)
+#define CPG_BUS_MCPU2_MSTOP (0xB68)
+#define CPG_BUS_PERI_COM_MSTOP (0xB6C)
+#define CPG_BUS_PERI_CPU_MSTOP (0xB70)
+#define CPG_BUS_PERI_DDR_MSTOP (0xB74)
+#define CPG_BUS_REG0_MSTOP (0xB7C)
+#define CPG_BUS_REG1_MSTOP (0xB80)
+#define CPG_BUS_TZCDDR_MSTOP (0xB84)
+#define CPG_MHU_MSTOP (0xB88)
+#define CPG_BUS_MCPU3_MSTOP (0xB90)
+#define CPG_BUS_PERI_CPU2_MSTOP (0xB94)
#define CPG_OTHERFUNC1_REG (0xBE8)
#define CPG_SIPLL5_STBY_RESETB BIT(0)
@@ -235,6 +247,55 @@ struct rzg2l_reset {
DEF_RST_MON(_id, _off, _bit, -1)
/**
+ * struct rzg2l_cpg_reg_conf - RZ/G2L register configuration data structure
+ * @off: register offset
+ * @mask: register mask
+ */
+struct rzg2l_cpg_reg_conf {
+ u16 off;
+ u16 mask;
+};
+
+#define DEF_REG_CONF(_off, _mask) ((struct rzg2l_cpg_reg_conf) { .off = (_off), .mask = (_mask) })
+
+/**
+ * struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure
+ * @mstop: MSTOP register configuration
+ */
+struct rzg2l_cpg_pm_domain_conf {
+ struct rzg2l_cpg_reg_conf mstop;
+};
+
+/**
+ * struct rzg2l_cpg_pm_domain_init_data - PM domain init data
+ * @name: PM domain name
+ * @conf: PM domain configuration
+ * @flags: RZG2L PM domain flags (see RZG2L_PD_F_*)
+ * @id: PM domain ID (similar to the ones defined in
+ * include/dt-bindings/clock/<soc-id>-cpg.h)
+ */
+struct rzg2l_cpg_pm_domain_init_data {
+ const char * const name;
+ struct rzg2l_cpg_pm_domain_conf conf;
+ u32 flags;
+ u16 id;
+};
+
+#define DEF_PD(_name, _id, _mstop_conf, _flags) \
+ { \
+ .name = (_name), \
+ .id = (_id), \
+ .conf = { \
+ .mstop = (_mstop_conf), \
+ }, \
+ .flags = (_flags), \
+ }
+
+/* Power domain flags. */
+#define RZG2L_PD_F_ALWAYS_ON BIT(0)
+#define RZG2L_PD_F_NONE (0)
+
+/**
* struct rzg2l_cpg_info - SoC-specific CPG Description
*
* @core_clks: Array of Core Clock definitions
@@ -252,6 +313,8 @@ struct rzg2l_reset {
* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
* should not be disabled without a knowledgeable driver
* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
+ * @pm_domains: PM domains init data array
+ * @num_pm_domains: Number of PM domains
* @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
*/
struct rzg2l_cpg_info {
@@ -278,6 +341,10 @@ struct rzg2l_cpg_info {
const unsigned int *crit_mod_clks;
unsigned int num_crit_mod_clks;
+ /* Power domain. */
+ const struct rzg2l_cpg_pm_domain_init_data *pm_domains;
+ unsigned int num_pm_domains;
+
bool has_clk_mon_regs;
};