diff options
Diffstat (limited to 'drivers/clk/samsung/clk-cpu.h')
| -rw-r--r-- | drivers/clk/samsung/clk-cpu.h | 53 |
1 files changed, 18 insertions, 35 deletions
diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h index 0164bd9ad..892843611 100644 --- a/drivers/clk/samsung/clk-cpu.h +++ b/drivers/clk/samsung/clk-cpu.h @@ -8,7 +8,24 @@ #ifndef __SAMSUNG_CLK_CPU_H #define __SAMSUNG_CLK_CPU_H -#include "clk.h" +/* The CPU clock registers have DIV1 configuration register */ +#define CLK_CPU_HAS_DIV1 BIT(0) +/* When ALT parent is active, debug clocks need safe divider values */ +#define CLK_CPU_NEEDS_DEBUG_ALT_DIV BIT(1) + +/** + * enum exynos_cpuclk_layout - CPU clock registers layout compatibility + * @CPUCLK_LAYOUT_E4210: Exynos4210 compatible layout + * @CPUCLK_LAYOUT_E5433: Exynos5433 compatible layout + * @CPUCLK_LAYOUT_E850_CL0: Exynos850 cluster 0 compatible layout + * @CPUCLK_LAYOUT_E850_CL1: Exynos850 cluster 1 compatible layout + */ +enum exynos_cpuclk_layout { + CPUCLK_LAYOUT_E4210, + CPUCLK_LAYOUT_E5433, + CPUCLK_LAYOUT_E850_CL0, + CPUCLK_LAYOUT_E850_CL1, +}; /** * struct exynos_cpuclk_cfg_data - config data to setup cpu clocks @@ -28,38 +45,4 @@ struct exynos_cpuclk_cfg_data { unsigned long div1; }; -/** - * struct exynos_cpuclk - information about clock supplied to a CPU core - * @hw: handle between CCF and CPU clock - * @alt_parent: alternate parent clock to use when switching the speed - * of the primary parent clock - * @ctrl_base: base address of the clock controller - * @lock: cpu clock domain register access lock - * @cfg: cpu clock rate configuration data - * @num_cfgs: number of array elements in @cfg array - * @clk_nb: clock notifier registered for changes in clock speed of the - * primary parent clock - * @flags: configuration flags for the CPU clock - * - * This structure holds information required for programming the CPU clock for - * various clock speeds. - */ -struct exynos_cpuclk { - struct clk_hw hw; - const struct clk_hw *alt_parent; - void __iomem *ctrl_base; - spinlock_t *lock; - const struct exynos_cpuclk_cfg_data *cfg; - const unsigned long num_cfgs; - struct notifier_block clk_nb; - unsigned long flags; - -/* The CPU clock registers have DIV1 configuration register */ -#define CLK_CPU_HAS_DIV1 (1 << 0) -/* When ALT parent is active, debug clocks need safe divider values */ -#define CLK_CPU_NEEDS_DEBUG_ALT_DIV (1 << 1) -/* The CPU clock registers have Exynos5433-compatible layout */ -#define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2) -}; - #endif /* __SAMSUNG_CLK_CPU_H */ |