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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index 3e2f0f64c..6b44557fc 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -56,6 +56,13 @@ enum dentist_dispclk_change_mode {
DISPCLK_CHANGE_MODE_RAMPING,
};
+struct dp_dto_params {
+ int otg_inst;
+ enum signal_type signal;
+ long long pixclk_hz;
+ long long refclk_hz;
+};
+
enum pixel_rate_div {
PIXEL_RATE_DIV_BY_1 = 0,
PIXEL_RATE_DIV_BY_2 = 1,
@@ -134,6 +141,11 @@ struct dccg_funcs {
enum physymclk_clock_source clk_src,
bool force_enable);
+ void (*set_physymclk_root_clock_gating)(
+ struct dccg *dccg,
+ int phy_inst,
+ bool enable);
+
void (*set_dtbclk_dto)(
struct dccg *dccg,
const struct dtbclk_dto_params *params);
@@ -182,6 +194,17 @@ struct dccg_funcs {
struct dccg *dccg,
uint32_t stream_enc_inst,
uint32_t link_enc_inst);
+ void (*set_dp_dto)(
+ struct dccg *dccg,
+ const struct dp_dto_params *params);
+ void (*set_dtbclk_p_src)(
+ struct dccg *dccg,
+ enum streamclk_source src,
+ uint32_t otg_inst);
+ void (*set_dto_dscclk)(
+ struct dccg *dccg,
+ uint32_t dsc_inst);
+ void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst);
};
#endif //__DAL_DCCG_H__