diff options
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_hdmi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_hdmi.c | 96 |
1 files changed, 56 insertions, 40 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 90d2236fed..5f6deceaf8 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -114,6 +114,8 @@ static u32 g4x_infoframe_enable(unsigned int type) return VIDEO_DIP_ENABLE_GAMUT; case DP_SDP_VSC: return 0; + case DP_SDP_ADAPTIVE_SYNC: + return 0; case HDMI_INFOFRAME_TYPE_AVI: return VIDEO_DIP_ENABLE_AVI; case HDMI_INFOFRAME_TYPE_SPD: @@ -137,6 +139,8 @@ static u32 hsw_infoframe_enable(unsigned int type) return VIDEO_DIP_ENABLE_GMP_HSW; case DP_SDP_VSC: return VIDEO_DIP_ENABLE_VSC_HSW; + case DP_SDP_ADAPTIVE_SYNC: + return VIDEO_DIP_ENABLE_AS_ADL; case DP_SDP_PPS: return VDIP_ENABLE_PPS; case HDMI_INFOFRAME_TYPE_AVI: @@ -164,6 +168,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); case DP_SDP_VSC: return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); + case DP_SDP_ADAPTIVE_SYNC: + return ADL_TVIDEO_DIP_AS_SDP_DATA(cpu_transcoder, i); case DP_SDP_PPS: return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_AVI: @@ -186,6 +192,8 @@ static int hsw_dip_data_size(struct drm_i915_private *dev_priv, switch (type) { case DP_SDP_VSC: return VIDEO_DIP_VSC_DATA_SIZE; + case DP_SDP_ADAPTIVE_SYNC: + return VIDEO_DIP_ASYNC_DATA_SIZE; case DP_SDP_PPS: return VIDEO_DIP_PPS_DATA_SIZE; case HDMI_PACKET_TYPE_GAMUT_METADATA: @@ -563,6 +571,9 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, if (DISPLAY_VER(dev_priv) >= 10) mask |= VIDEO_DIP_ENABLE_DRM_GLK; + if (HAS_AS_SDP(dev_priv)) + mask |= VIDEO_DIP_ENABLE_AS_ADL; + return val & mask; } @@ -570,6 +581,7 @@ static const u8 infoframe_type_to_idx[] = { HDMI_PACKET_TYPE_GENERAL_CONTROL, HDMI_PACKET_TYPE_GAMUT_METADATA, DP_SDP_VSC, + DP_SDP_ADAPTIVE_SYNC, HDMI_INFOFRAME_TYPE_AVI, HDMI_INFOFRAME_TYPE_SPD, HDMI_INFOFRAME_TYPE_VENDOR, @@ -1212,7 +1224,7 @@ static void hsw_set_infoframes(struct intel_encoder *encoder, val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | - VIDEO_DIP_ENABLE_DRM_GLK); + VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_AS_ADL); if (!enable) { intel_de_write(dev_priv, reg, val); @@ -1832,7 +1844,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, bool has_hdmi_sink) { struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); - enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port); + struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; if (clock < 25000) return MODE_CLOCK_LOW; @@ -1854,11 +1866,11 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, return MODE_CLOCK_RANGE; /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ - if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200) + if (intel_encoder_is_combo(encoder) && clock > 500000 && clock < 533200) return MODE_CLOCK_RANGE; /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ - if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800) + if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800) return MODE_CLOCK_RANGE; /* @@ -1981,7 +1993,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector, struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); enum drm_mode_status status; int clock = mode->clock; - int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; + int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq; bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); bool ycbcr_420_only; enum intel_output_format sink_format; @@ -2664,8 +2676,9 @@ bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, drm_scdc_set_scrambling(connector, scrambling); } -static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) +static u8 chv_encoder_to_ddc_pin(struct intel_encoder *encoder) { + enum port port = encoder->port; u8 ddc_pin; switch (port) { @@ -2686,8 +2699,9 @@ static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) return ddc_pin; } -static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) +static u8 bxt_encoder_to_ddc_pin(struct intel_encoder *encoder) { + enum port port = encoder->port; u8 ddc_pin; switch (port) { @@ -2705,9 +2719,9 @@ static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) return ddc_pin; } -static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, - enum port port) +static u8 cnp_encoder_to_ddc_pin(struct intel_encoder *encoder) { + enum port port = encoder->port; u8 ddc_pin; switch (port) { @@ -2731,22 +2745,23 @@ static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, return ddc_pin; } -static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) +static u8 icl_encoder_to_ddc_pin(struct intel_encoder *encoder) { - enum phy phy = intel_port_to_phy(dev_priv, port); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + enum port port = encoder->port; - if (intel_phy_is_combo(dev_priv, phy)) + if (intel_encoder_is_combo(encoder)) return GMBUS_PIN_1_BXT + port; - else if (intel_phy_is_tc(dev_priv, phy)) - return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port); + else if (intel_encoder_is_tc(encoder)) + return GMBUS_PIN_9_TC1_ICP + intel_encoder_to_tc(encoder); drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port)); return GMBUS_PIN_2_BXT; } -static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) +static u8 mcc_encoder_to_ddc_pin(struct intel_encoder *encoder) { - enum phy phy = intel_port_to_phy(dev_priv, port); + enum phy phy = intel_encoder_to_phy(encoder); u8 ddc_pin; switch (phy) { @@ -2767,11 +2782,12 @@ static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) return ddc_pin; } -static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) +static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder) { - enum phy phy = intel_port_to_phy(dev_priv, port); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + enum phy phy = intel_encoder_to_phy(encoder); - WARN_ON(port == PORT_C); + WARN_ON(encoder->port == PORT_C); /* * Pin mapping for RKL depends on which PCH is present. With TGP, the @@ -2785,11 +2801,12 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) return GMBUS_PIN_1_BXT + phy; } -static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port) +static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder) { - enum phy phy = intel_port_to_phy(i915, port); + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum phy phy = intel_encoder_to_phy(encoder); - drm_WARN_ON(&i915->drm, port == PORT_A); + drm_WARN_ON(&i915->drm, encoder->port == PORT_A); /* * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, @@ -2803,16 +2820,16 @@ static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port po return GMBUS_PIN_1_BXT + phy; } -static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) +static u8 dg1_encoder_to_ddc_pin(struct intel_encoder *encoder) { - return intel_port_to_phy(dev_priv, port) + 1; + return intel_encoder_to_phy(encoder) + 1; } -static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) +static u8 adls_encoder_to_ddc_pin(struct intel_encoder *encoder) { - enum phy phy = intel_port_to_phy(dev_priv, port); + enum phy phy = intel_encoder_to_phy(encoder); - WARN_ON(port == PORT_B || port == PORT_C); + WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C); /* * Pin mapping for ADL-S requires TC pins for all combo phy outputs @@ -2824,9 +2841,9 @@ static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; } -static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, - enum port port) +static u8 g4x_encoder_to_ddc_pin(struct intel_encoder *encoder) { + enum port port = encoder->port; u8 ddc_pin; switch (port) { @@ -2850,30 +2867,29 @@ static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, static u8 intel_hdmi_default_ddc_pin(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum port port = encoder->port; u8 ddc_pin; if (IS_ALDERLAKE_S(dev_priv)) - ddc_pin = adls_port_to_ddc_pin(dev_priv, port); + ddc_pin = adls_encoder_to_ddc_pin(encoder); else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) - ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); + ddc_pin = dg1_encoder_to_ddc_pin(encoder); else if (IS_ROCKETLAKE(dev_priv)) - ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); + ddc_pin = rkl_encoder_to_ddc_pin(encoder); else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv)) - ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port); + ddc_pin = gen9bc_tgp_encoder_to_ddc_pin(encoder); else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && HAS_PCH_TGP(dev_priv)) - ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); + ddc_pin = mcc_encoder_to_ddc_pin(encoder); else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) - ddc_pin = icl_port_to_ddc_pin(dev_priv, port); + ddc_pin = icl_encoder_to_ddc_pin(encoder); else if (HAS_PCH_CNP(dev_priv)) - ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); + ddc_pin = cnp_encoder_to_ddc_pin(encoder); else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) - ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); + ddc_pin = bxt_encoder_to_ddc_pin(encoder); else if (IS_CHERRYVIEW(dev_priv)) - ddc_pin = chv_port_to_ddc_pin(dev_priv, port); + ddc_pin = chv_encoder_to_ddc_pin(encoder); else - ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); + ddc_pin = g4x_encoder_to_ddc_pin(encoder); return ddc_pin; } |