diff options
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h')
-rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 48 |
1 files changed, 16 insertions, 32 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 7bed819dfc..69b80af656 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -24,16 +24,6 @@ static const struct dpu_mdp_cfg sm8550_mdp = { .base = 0, .len = 0x494, .features = BIT(DPU_MDP_PERIPH_0_REMOVED), .clk_ctrls = { - [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 }, - [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 }, - [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 }, - [DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 }, - [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 }, - [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 }, - [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 }, - [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 }, - [DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 }, - [DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 }, [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, }, }; @@ -81,7 +71,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sm8550_vig_sblk_0, .xin_id = 0, .type = SSPP_TYPE_VIG, - .clk_ctrl = DPU_CLK_CTRL_VIG0, }, { .name = "sspp_1", .id = SSPP_VIG1, .base = 0x6000, .len = 0x344, @@ -89,7 +78,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sm8550_vig_sblk_1, .xin_id = 4, .type = SSPP_TYPE_VIG, - .clk_ctrl = DPU_CLK_CTRL_VIG1, }, { .name = "sspp_2", .id = SSPP_VIG2, .base = 0x8000, .len = 0x344, @@ -97,7 +85,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sm8550_vig_sblk_2, .xin_id = 8, .type = SSPP_TYPE_VIG, - .clk_ctrl = DPU_CLK_CTRL_VIG2, }, { .name = "sspp_3", .id = SSPP_VIG3, .base = 0xa000, .len = 0x344, @@ -105,7 +92,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sm8550_vig_sblk_3, .xin_id = 12, .type = SSPP_TYPE_VIG, - .clk_ctrl = DPU_CLK_CTRL_VIG3, }, { .name = "sspp_8", .id = SSPP_DMA0, .base = 0x24000, .len = 0x344, @@ -113,7 +99,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sdm845_dma_sblk_0, .xin_id = 1, .type = SSPP_TYPE_DMA, - .clk_ctrl = DPU_CLK_CTRL_DMA0, }, { .name = "sspp_9", .id = SSPP_DMA1, .base = 0x26000, .len = 0x344, @@ -121,7 +106,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sdm845_dma_sblk_1, .xin_id = 5, .type = SSPP_TYPE_DMA, - .clk_ctrl = DPU_CLK_CTRL_DMA1, }, { .name = "sspp_10", .id = SSPP_DMA2, .base = 0x28000, .len = 0x344, @@ -129,7 +113,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sdm845_dma_sblk_2, .xin_id = 9, .type = SSPP_TYPE_DMA, - .clk_ctrl = DPU_CLK_CTRL_DMA2, }, { .name = "sspp_11", .id = SSPP_DMA3, .base = 0x2a000, .len = 0x344, @@ -137,7 +120,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sdm845_dma_sblk_3, .xin_id = 13, .type = SSPP_TYPE_DMA, - .clk_ctrl = DPU_CLK_CTRL_DMA3, }, { .name = "sspp_12", .id = SSPP_DMA4, .base = 0x2c000, .len = 0x344, @@ -145,7 +127,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sm8550_dma_sblk_4, .xin_id = 14, .type = SSPP_TYPE_DMA, - .clk_ctrl = DPU_CLK_CTRL_DMA4, }, { .name = "sspp_13", .id = SSPP_DMA5, .base = 0x2e000, .len = 0x344, @@ -153,7 +134,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sm8550_dma_sblk_5, .xin_id = 15, .type = SSPP_TYPE_DMA, - .clk_ctrl = DPU_CLK_CTRL_DMA5, }, }; @@ -236,7 +216,6 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = { .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_0, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - .intr_rdptr = -1, }, { .name = "pingpong_1", .id = PINGPONG_1, .base = 0x6a000, .len = 0, @@ -244,7 +223,6 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = { .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_0, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), - .intr_rdptr = -1, }, { .name = "pingpong_2", .id = PINGPONG_2, .base = 0x6b000, .len = 0, @@ -252,7 +230,6 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = { .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_1, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), - .intr_rdptr = -1, }, { .name = "pingpong_3", .id = PINGPONG_3, .base = 0x6c000, .len = 0, @@ -260,7 +237,6 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = { .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_1, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), - .intr_rdptr = -1, }, { .name = "pingpong_4", .id = PINGPONG_4, .base = 0x6d000, .len = 0, @@ -268,7 +244,6 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = { .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_2, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), - .intr_rdptr = -1, }, { .name = "pingpong_5", .id = PINGPONG_5, .base = 0x6e000, .len = 0, @@ -276,23 +251,18 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = { .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_2, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), - .intr_rdptr = -1, }, { .name = "pingpong_6", .id = PINGPONG_6, .base = 0x66000, .len = 0, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_3, - .intr_done = -1, - .intr_rdptr = -1, }, { .name = "pingpong_7", .id = PINGPONG_7, .base = 0x66400, .len = 0, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_3, - .intr_done = -1, - .intr_rdptr = -1, }, }; @@ -341,6 +311,20 @@ static const struct dpu_dsc_cfg sm8550_dsc[] = { }, }; +static const struct dpu_wb_cfg sm8550_wb[] = { + { + .name = "wb_2", .id = WB_2, + .base = 0x65000, .len = 0x2c8, + .features = WB_SM8250_MASK, + .format_list = wb2_formats, + .num_formats = ARRAY_SIZE(wb2_formats), + .xin_id = 6, + .vbif_idx = VBIF_RT, + .maxlinewidth = 4096, + .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, +}; + static const struct dpu_intf_cfg sm8550_intf[] = { { .name = "intf_0", .id = INTF_0, @@ -351,7 +335,6 @@ static const struct dpu_intf_cfg sm8550_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), - .intr_tear_rd_ptr = -1, }, { .name = "intf_1", .id = INTF_1, .base = 0x35000, .len = 0x300, @@ -381,7 +364,6 @@ static const struct dpu_intf_cfg sm8550_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), - .intr_tear_rd_ptr = -1, }, }; @@ -438,6 +420,8 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = { .dsc = sm8550_dsc, .merge_3d_count = ARRAY_SIZE(sm8550_merge_3d), .merge_3d = sm8550_merge_3d, + .wb_count = ARRAY_SIZE(sm8550_wb), + .wb = sm8550_wb, .intf_count = ARRAY_SIZE(sm8550_intf), .intf = sm8550_intf, .vbif_count = ARRAY_SIZE(sm8550_vbif), |