diff options
Diffstat (limited to 'drivers/gpu/drm/msm/dp/dp_catalog.c')
| -rw-r--r-- | drivers/gpu/drm/msm/dp/dp_catalog.c | 271 |
1 files changed, 219 insertions, 52 deletions
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 5142aeb70..3e7c84cde 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -7,8 +7,7 @@ #include <linux/delay.h> #include <linux/iopoll.h> -#include <linux/phy/phy.h> -#include <linux/phy/phy-dp.h> +#include <linux/platform_device.h> #include <linux/rational.h> #include <drm/display/drm_dp_helper.h> #include <drm/drm_print.h> @@ -55,10 +54,31 @@ (PSR_UPDATE_MASK | PSR_CAPTURE_MASK | PSR_EXIT_MASK | \ PSR_UPDATE_ERROR_MASK | PSR_WAKE_ERROR_MASK) +#define DP_DEFAULT_AHB_OFFSET 0x0000 +#define DP_DEFAULT_AHB_SIZE 0x0200 +#define DP_DEFAULT_AUX_OFFSET 0x0200 +#define DP_DEFAULT_AUX_SIZE 0x0200 +#define DP_DEFAULT_LINK_OFFSET 0x0400 +#define DP_DEFAULT_LINK_SIZE 0x0C00 +#define DP_DEFAULT_P0_OFFSET 0x1000 +#define DP_DEFAULT_P0_SIZE 0x0400 + +struct dss_io_region { + size_t len; + void __iomem *base; +}; + +struct dss_io_data { + struct dss_io_region ahb; + struct dss_io_region aux; + struct dss_io_region link; + struct dss_io_region p0; +}; + struct dp_catalog_private { struct device *dev; struct drm_device *drm_dev; - struct dp_io *io; + struct dss_io_data io; u32 (*audio_map)[DP_AUDIO_SDP_HEADER_MAX]; struct dp_catalog dp_catalog; u8 aux_lut_cfg_index[PHY_AUX_CFG_MAX]; @@ -68,7 +88,7 @@ void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *d { struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); - struct dss_io_data *dss = &catalog->io->dp_controller; + struct dss_io_data *dss = &catalog->io; msm_disp_snapshot_add_block(disp_state, dss->ahb.len, dss->ahb.base, "dp_ahb"); msm_disp_snapshot_add_block(disp_state, dss->aux.len, dss->aux.base, "dp_aux"); @@ -78,7 +98,7 @@ void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *d static inline u32 dp_read_aux(struct dp_catalog_private *catalog, u32 offset) { - return readl_relaxed(catalog->io->dp_controller.aux.base + offset); + return readl_relaxed(catalog->io.aux.base + offset); } static inline void dp_write_aux(struct dp_catalog_private *catalog, @@ -88,12 +108,12 @@ static inline void dp_write_aux(struct dp_catalog_private *catalog, * To make sure aux reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.aux.base + offset); + writel(data, catalog->io.aux.base + offset); } static inline u32 dp_read_ahb(const struct dp_catalog_private *catalog, u32 offset) { - return readl_relaxed(catalog->io->dp_controller.ahb.base + offset); + return readl_relaxed(catalog->io.ahb.base + offset); } static inline void dp_write_ahb(struct dp_catalog_private *catalog, @@ -103,7 +123,7 @@ static inline void dp_write_ahb(struct dp_catalog_private *catalog, * To make sure phy reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.ahb.base + offset); + writel(data, catalog->io.ahb.base + offset); } static inline void dp_write_p0(struct dp_catalog_private *catalog, @@ -113,7 +133,7 @@ static inline void dp_write_p0(struct dp_catalog_private *catalog, * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.p0.base + offset); + writel(data, catalog->io.p0.base + offset); } static inline u32 dp_read_p0(struct dp_catalog_private *catalog, @@ -123,12 +143,12 @@ static inline u32 dp_read_p0(struct dp_catalog_private *catalog, * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - return readl_relaxed(catalog->io->dp_controller.p0.base + offset); + return readl_relaxed(catalog->io.p0.base + offset); } static inline u32 dp_read_link(struct dp_catalog_private *catalog, u32 offset) { - return readl_relaxed(catalog->io->dp_controller.link.base + offset); + return readl_relaxed(catalog->io.link.base + offset); } static inline void dp_write_link(struct dp_catalog_private *catalog, @@ -138,7 +158,7 @@ static inline void dp_write_link(struct dp_catalog_private *catalog, * To make sure link reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.link.base + offset); + writel(data, catalog->io.link.base + offset); } /* aux related catalog functions */ @@ -243,16 +263,6 @@ void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable) dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl); } -void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog) -{ - struct dp_catalog_private *catalog = container_of(dp_catalog, - struct dp_catalog_private, dp_catalog); - struct dp_io *dp_io = catalog->io; - struct phy *phy = dp_io->phy; - - phy_calibrate(phy); -} - int dp_catalog_aux_wait_for_hpd_connect_state(struct dp_catalog *dp_catalog) { u32 state; @@ -260,7 +270,7 @@ int dp_catalog_aux_wait_for_hpd_connect_state(struct dp_catalog *dp_catalog) struct dp_catalog_private, dp_catalog); /* poll for hpd connected status every 2ms and timeout after 500ms */ - return readl_poll_timeout(catalog->io->dp_controller.aux.base + + return readl_poll_timeout(catalog->io.aux.base + REG_DP_DP_HPD_INT_STATUS, state, state & DP_DP_HPD_STATE_STATUS_CONNECTED, 2000, 500000); @@ -288,7 +298,7 @@ void dp_catalog_dump_regs(struct dp_catalog *dp_catalog) { struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); - struct dss_io_data *io = &catalog->io->dp_controller; + struct dss_io_data *io = &catalog->io; pr_info("AHB regs\n"); dump_regs(io->ahb.base, io->ahb.len); @@ -440,9 +450,26 @@ void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, dp_write_link(catalog, REG_DP_MISC1_MISC0, misc_val); } +void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog) +{ + u32 mainlink_ctrl, hw_revision; + struct dp_catalog_private *catalog = container_of(dp_catalog, + struct dp_catalog_private, dp_catalog); + + mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + + hw_revision = dp_catalog_hw_revision(dp_catalog); + if (hw_revision >= DP_HW_VERSION_1_2) + mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE; + else + mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; + + dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); +} + void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate, u32 stream_rate_khz, - bool fixed_nvid) + bool fixed_nvid, bool is_ycbcr_420) { u32 pixel_m, pixel_n; u32 mvid, nvid, pixel_div = 0, dispcc_input_rate; @@ -485,6 +512,9 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, nvid = temp; } + if (is_ycbcr_420) + mvid /= 2; + if (link_rate_hbr2 == rate) nvid *= 2; @@ -512,7 +542,7 @@ int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, bit = BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; /* Poll for mainlink ready status */ - ret = readx_poll_timeout(readl, catalog->io->dp_controller.link.base + + ret = readx_poll_timeout(readl, catalog->io.link.base + REG_DP_MAINLINK_READY, data, data & bit, POLLING_SLEEP_US, POLLING_TIMEOUT_US); @@ -575,7 +605,7 @@ bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog) struct dp_catalog_private, dp_catalog); /* Poll for mainlink ready status */ - ret = readl_poll_timeout(catalog->io->dp_controller.link.base + + ret = readl_poll_timeout(catalog->io.link.base + REG_DP_MAINLINK_READY, data, data & DP_MAINLINK_READY_FOR_VIDEO, POLLING_SLEEP_US, POLLING_TIMEOUT_US); @@ -765,25 +795,6 @@ void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog) dp_write_ahb(catalog, REG_DP_PHY_CTRL, 0x0); } -int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, - u8 v_level, u8 p_level) -{ - struct dp_catalog_private *catalog = container_of(dp_catalog, - struct dp_catalog_private, dp_catalog); - struct dp_io *dp_io = catalog->io; - struct phy *phy = dp_io->phy; - struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; - - /* TODO: Update for all lanes instead of just first one */ - opts_dp->voltage[0] = v_level; - opts_dp->pre[0] = p_level; - opts_dp->set_voltages = 1; - phy_configure(phy, &dp_io->phy_opts); - opts_dp->set_voltages = 0; - - return 0; -} - void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog *dp_catalog, u32 pattern) { @@ -898,6 +909,99 @@ int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog) return 0; } +static void dp_catalog_panel_send_vsc_sdp(struct dp_catalog *dp_catalog, struct dp_sdp *vsc_sdp) +{ + struct dp_catalog_private *catalog; + u32 header[2]; + u32 val; + int i; + + catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); + + dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); + + dp_write_link(catalog, MMSS_DP_GENERIC0_0, header[0]); + dp_write_link(catalog, MMSS_DP_GENERIC0_1, header[1]); + + for (i = 0; i < sizeof(vsc_sdp->db); i += 4) { + val = ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i + 2] << 16) | + (vsc_sdp->db[i + 3] << 24)); + dp_write_link(catalog, MMSS_DP_GENERIC0_2 + i, val); + } +} + +static void dp_catalog_panel_update_sdp(struct dp_catalog *dp_catalog) +{ + struct dp_catalog_private *catalog; + u32 hw_revision; + + catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); + + hw_revision = dp_catalog_hw_revision(dp_catalog); + if (hw_revision < DP_HW_VERSION_1_2 && hw_revision >= DP_HW_VERSION_1_0) { + dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x01); + dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x00); + } +} + +void dp_catalog_panel_enable_vsc_sdp(struct dp_catalog *dp_catalog, struct dp_sdp *vsc_sdp) +{ + struct dp_catalog_private *catalog; + u32 cfg, cfg2, misc; + + catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); + + cfg = dp_read_link(catalog, MMSS_DP_SDP_CFG); + cfg2 = dp_read_link(catalog, MMSS_DP_SDP_CFG2); + misc = dp_read_link(catalog, REG_DP_MISC1_MISC0); + + cfg |= GEN0_SDP_EN; + dp_write_link(catalog, MMSS_DP_SDP_CFG, cfg); + + cfg2 |= GENERIC0_SDPSIZE_VALID; + dp_write_link(catalog, MMSS_DP_SDP_CFG2, cfg2); + + dp_catalog_panel_send_vsc_sdp(dp_catalog, vsc_sdp); + + /* indicates presence of VSC (BIT(6) of MISC1) */ + misc |= DP_MISC1_VSC_SDP; + + drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=1\n"); + + pr_debug("misc settings = 0x%x\n", misc); + dp_write_link(catalog, REG_DP_MISC1_MISC0, misc); + + dp_catalog_panel_update_sdp(dp_catalog); +} + +void dp_catalog_panel_disable_vsc_sdp(struct dp_catalog *dp_catalog) +{ + struct dp_catalog_private *catalog; + u32 cfg, cfg2, misc; + + catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); + + cfg = dp_read_link(catalog, MMSS_DP_SDP_CFG); + cfg2 = dp_read_link(catalog, MMSS_DP_SDP_CFG2); + misc = dp_read_link(catalog, REG_DP_MISC1_MISC0); + + cfg &= ~GEN0_SDP_EN; + dp_write_link(catalog, MMSS_DP_SDP_CFG, cfg); + + cfg2 &= ~GENERIC0_SDPSIZE_VALID; + dp_write_link(catalog, MMSS_DP_SDP_CFG2, cfg2); + + /* switch back to MSA */ + misc &= ~DP_MISC1_VSC_SDP; + + drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=0\n"); + + pr_debug("misc settings = 0x%x\n", misc); + dp_write_link(catalog, REG_DP_MISC1_MISC0, misc); + + dp_catalog_panel_update_sdp(dp_catalog); +} + void dp_catalog_panel_tpg_enable(struct dp_catalog *dp_catalog, struct drm_display_mode *drm_mode) { @@ -976,21 +1080,84 @@ void dp_catalog_panel_tpg_disable(struct dp_catalog *dp_catalog) dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0); } -struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_io *io) +static void __iomem *dp_ioremap(struct platform_device *pdev, int idx, size_t *len) { - struct dp_catalog_private *catalog; + struct resource *res; + void __iomem *base; + + base = devm_platform_get_and_ioremap_resource(pdev, idx, &res); + if (!IS_ERR(base)) + *len = resource_size(res); + + return base; +} + +static int dp_catalog_get_io(struct dp_catalog_private *catalog) +{ + struct platform_device *pdev = to_platform_device(catalog->dev); + struct dss_io_data *dss = &catalog->io; + + dss->ahb.base = dp_ioremap(pdev, 0, &dss->ahb.len); + if (IS_ERR(dss->ahb.base)) + return PTR_ERR(dss->ahb.base); - if (!io) { - DRM_ERROR("invalid input\n"); - return ERR_PTR(-EINVAL); + dss->aux.base = dp_ioremap(pdev, 1, &dss->aux.len); + if (IS_ERR(dss->aux.base)) { + /* + * The initial binding had a single reg, but in order to + * support variation in the sub-region sizes this was split. + * dp_ioremap() will fail with -EINVAL here if only a single + * reg is specified, so fill in the sub-region offsets and + * lengths based on this single region. + */ + if (PTR_ERR(dss->aux.base) == -EINVAL) { + if (dss->ahb.len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) { + DRM_ERROR("legacy memory region not large enough\n"); + return -EINVAL; + } + + dss->ahb.len = DP_DEFAULT_AHB_SIZE; + dss->aux.base = dss->ahb.base + DP_DEFAULT_AUX_OFFSET; + dss->aux.len = DP_DEFAULT_AUX_SIZE; + dss->link.base = dss->ahb.base + DP_DEFAULT_LINK_OFFSET; + dss->link.len = DP_DEFAULT_LINK_SIZE; + dss->p0.base = dss->ahb.base + DP_DEFAULT_P0_OFFSET; + dss->p0.len = DP_DEFAULT_P0_SIZE; + } else { + DRM_ERROR("unable to remap aux region: %pe\n", dss->aux.base); + return PTR_ERR(dss->aux.base); + } + } else { + dss->link.base = dp_ioremap(pdev, 2, &dss->link.len); + if (IS_ERR(dss->link.base)) { + DRM_ERROR("unable to remap link region: %pe\n", dss->link.base); + return PTR_ERR(dss->link.base); + } + + dss->p0.base = dp_ioremap(pdev, 3, &dss->p0.len); + if (IS_ERR(dss->p0.base)) { + DRM_ERROR("unable to remap p0 region: %pe\n", dss->p0.base); + return PTR_ERR(dss->p0.base); + } } + return 0; +} + +struct dp_catalog *dp_catalog_get(struct device *dev) +{ + struct dp_catalog_private *catalog; + int ret; + catalog = devm_kzalloc(dev, sizeof(*catalog), GFP_KERNEL); if (!catalog) return ERR_PTR(-ENOMEM); catalog->dev = dev; - catalog->io = io; + + ret = dp_catalog_get_io(catalog); + if (ret) + return ERR_PTR(ret); return &catalog->dp_catalog; } |