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-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/cl0080.h3
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/class.h21
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/conn.h20
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/if0011.h21
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/if0012.h249
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/outp.h96
6 files changed, 348 insertions, 62 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl0080.h b/drivers/gpu/drm/nouveau/include/nvif/cl0080.h
index 8b5a240d5..fa161b74d 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/cl0080.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/cl0080.h
@@ -35,6 +35,7 @@ struct nv_device_info_v0 {
#define NV_DEVICE_INFO_V0_VOLTA 0x0b
#define NV_DEVICE_INFO_V0_TURING 0x0c
#define NV_DEVICE_INFO_V0_AMPERE 0x0d
+#define NV_DEVICE_INFO_V0_ADA 0x0e
__u8 family;
__u8 pad06[2];
__u64 ram_size;
@@ -90,6 +91,8 @@ struct nv_device_time_v0 {
#define NV_DEVICE_HOST_RUNLIST_ENGINES_SEC2 0x00004000
#define NV_DEVICE_HOST_RUNLIST_ENGINES_NVDEC 0x00008000
#define NV_DEVICE_HOST_RUNLIST_ENGINES_NVENC 0x00010000
+#define NV_DEVICE_HOST_RUNLIST_ENGINES_NVJPG 0x00020000
+#define NV_DEVICE_HOST_RUNLIST_ENGINES_OFA 0x00040000
/* Returns the number of available channels on runlist(data). */
#define NV_DEVICE_HOST_RUNLIST_CHANNELS NV_DEVICE_HOST(0x00000101)
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h
index ad1e5de84..e668ab166 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/class.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/class.h
@@ -104,6 +104,7 @@
#define GV100_DISP /* if0010.h */ 0x0000c370
#define TU102_DISP /* if0010.h */ 0x0000c570
#define GA102_DISP /* if0010.h */ 0x0000c670
+#define AD102_DISP /* if0010.h */ 0x0000c770
#define GV100_DISP_CAPS 0x0000c373
@@ -154,6 +155,7 @@
#define GV100_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c37d
#define TU102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c57d
#define GA102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c67d
+#define AD102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c77d
#define NV50_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000507e
#define G82_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000827e
@@ -192,8 +194,15 @@
#define AMPERE_B /* cl9097.h */ 0x0000c797
+#define ADA_A /* cl9097.h */ 0x0000c997
+
#define NV74_BSP 0x000074b0
+#define NVC4B0_VIDEO_DECODER 0x0000c4b0
+#define NVC6B0_VIDEO_DECODER 0x0000c6b0
+#define NVC7B0_VIDEO_DECODER 0x0000c7b0
+#define NVC9B0_VIDEO_DECODER 0x0000c9b0
+
#define GT212_MSVLD 0x000085b1
#define IGT21A_MSVLD 0x000086b1
#define G98_MSVLD 0x000088b1
@@ -222,6 +231,10 @@
#define AMPERE_DMA_COPY_A 0x0000c6b5
#define AMPERE_DMA_COPY_B 0x0000c7b5
+#define NVC4B7_VIDEO_ENCODER 0x0000c4b7
+#define NVC7B7_VIDEO_ENCODER 0x0000c7b7
+#define NVC9B7_VIDEO_ENCODER 0x0000c9b7
+
#define FERMI_DECOMPRESS 0x000090b8
#define NV50_COMPUTE 0x000050c0
@@ -237,6 +250,14 @@
#define VOLTA_COMPUTE_A 0x0000c3c0
#define TURING_COMPUTE_A 0x0000c5c0
#define AMPERE_COMPUTE_B 0x0000c7c0
+#define ADA_COMPUTE_A 0x0000c9c0
#define NV74_CIPHER 0x000074c1
+
+#define NVC4D1_VIDEO_NVJPG 0x0000c4d1
+#define NVC9D1_VIDEO_NVJPG 0x0000c9d1
+
+#define NVC6FA_VIDEO_OFA 0x0000c6fa
+#define NVC7FA_VIDEO_OFA 0x0000c7fa
+#define NVC9FA_VIDEO_OFA 0x0000c9fa
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/conn.h b/drivers/gpu/drm/nouveau/include/nvif/conn.h
index dc355e1df..406c12a11 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/conn.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/conn.h
@@ -7,6 +7,21 @@ struct nvif_disp;
struct nvif_conn {
struct nvif_object object;
+ u32 id;
+
+ struct {
+ enum {
+ NVIF_CONN_VGA,
+ NVIF_CONN_TV,
+ NVIF_CONN_DVI_I,
+ NVIF_CONN_DVI_D,
+ NVIF_CONN_LVDS,
+ NVIF_CONN_LVDS_SPWG,
+ NVIF_CONN_HDMI,
+ NVIF_CONN_DP,
+ NVIF_CONN_EDP,
+ } type;
+ } info;
};
int nvif_conn_ctor(struct nvif_disp *, const char *name, int id, struct nvif_conn *);
@@ -18,11 +33,6 @@ nvif_conn_id(struct nvif_conn *conn)
return conn->object.handle;
}
-#define NVIF_CONN_HPD_STATUS_UNSUPPORTED 0 /* negative if query fails */
-#define NVIF_CONN_HPD_STATUS_NOT_PRESENT 1
-#define NVIF_CONN_HPD_STATUS_PRESENT 2
-int nvif_conn_hpd_status(struct nvif_conn *);
-
int nvif_conn_event_ctor(struct nvif_conn *, const char *name, nvif_event_func, u8 types,
struct nvif_event *);
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0011.h b/drivers/gpu/drm/nouveau/include/nvif/if0011.h
index 69b0b779f..3ed0ddd75 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/if0011.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/if0011.h
@@ -7,6 +7,16 @@ union nvif_conn_args {
__u8 version;
__u8 id; /* DCB connector table index. */
__u8 pad02[6];
+#define NVIF_CONN_V0_VGA 0x00
+#define NVIF_CONN_V0_TV 0x01
+#define NVIF_CONN_V0_DVI_I 0x02
+#define NVIF_CONN_V0_DVI_D 0x03
+#define NVIF_CONN_V0_LVDS 0x04
+#define NVIF_CONN_V0_LVDS_SPWG 0x05
+#define NVIF_CONN_V0_HDMI 0x06
+#define NVIF_CONN_V0_DP 0x07
+#define NVIF_CONN_V0_EDP 0x08
+ __u8 type;
} v0;
};
@@ -20,15 +30,4 @@ union nvif_conn_event_args {
__u8 pad02[6];
} v0;
};
-
-#define NVIF_CONN_V0_HPD_STATUS 0x00000000
-
-union nvif_conn_hpd_status_args {
- struct nvif_conn_hpd_status_v0 {
- __u8 version;
- __u8 support;
- __u8 present;
- __u8 pad03[5];
- } v0;
-};
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0012.h b/drivers/gpu/drm/nouveau/include/nvif/if0012.h
index 16d4ad502..bde9bfae8 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/if0012.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/if0012.h
@@ -8,18 +8,86 @@ union nvif_outp_args {
struct nvif_outp_v0 {
__u8 version;
__u8 id; /* DCB device index. */
- __u8 pad02[6];
+#define NVIF_OUTP_V0_TYPE_DAC 0x00
+#define NVIF_OUTP_V0_TYPE_SOR 0x01
+#define NVIF_OUTP_V0_TYPE_PIOR 0x02
+ __u8 type;
+#define NVIF_OUTP_V0_PROTO_RGB_CRT 0x00
+#define NVIF_OUTP_V0_PROTO_TMDS 0x01
+#define NVIF_OUTP_V0_PROTO_LVDS 0x02
+#define NVIF_OUTP_V0_PROTO_DP 0x03
+ __u8 proto;
+ __u8 heads;
+ __u8 ddc;
+ __u8 conn;
+ union {
+ struct {
+ __u32 freq_max;
+ } rgb_crt;
+ struct {
+ __u8 dual;
+ } tmds;
+ struct {
+ __u8 acpi_edid;
+ } lvds;
+ struct {
+ __u8 aux;
+ __u8 mst;
+ __u8 increased_wm;
+ __u8 link_nr;
+ __u32 link_bw;
+ } dp;
+ };
} v0;
};
-#define NVIF_OUTP_V0_LOAD_DETECT 0x00
-#define NVIF_OUTP_V0_ACQUIRE 0x01
-#define NVIF_OUTP_V0_RELEASE 0x02
-#define NVIF_OUTP_V0_INFOFRAME 0x03
-#define NVIF_OUTP_V0_HDA_ELD 0x04
-#define NVIF_OUTP_V0_DP_AUX_PWR 0x05
-#define NVIF_OUTP_V0_DP_RETRAIN 0x06
-#define NVIF_OUTP_V0_DP_MST_VCPI 0x07
+#define NVIF_OUTP_V0_DETECT 0x00
+#define NVIF_OUTP_V0_EDID_GET 0x01
+
+#define NVIF_OUTP_V0_INHERIT 0x10
+#define NVIF_OUTP_V0_ACQUIRE 0x11
+#define NVIF_OUTP_V0_RELEASE 0x12
+
+#define NVIF_OUTP_V0_LOAD_DETECT 0x20
+
+#define NVIF_OUTP_V0_BL_GET 0x30
+#define NVIF_OUTP_V0_BL_SET 0x31
+
+#define NVIF_OUTP_V0_LVDS 0x40
+
+#define NVIF_OUTP_V0_HDMI 0x50
+
+#define NVIF_OUTP_V0_INFOFRAME 0x60
+#define NVIF_OUTP_V0_HDA_ELD 0x61
+
+#define NVIF_OUTP_V0_DP_AUX_PWR 0x70
+#define NVIF_OUTP_V0_DP_AUX_XFER 0x71
+#define NVIF_OUTP_V0_DP_RATES 0x72
+#define NVIF_OUTP_V0_DP_TRAIN 0x73
+#define NVIF_OUTP_V0_DP_DRIVE 0x74
+#define NVIF_OUTP_V0_DP_SST 0x75
+#define NVIF_OUTP_V0_DP_MST_ID_GET 0x76
+#define NVIF_OUTP_V0_DP_MST_ID_PUT 0x77
+#define NVIF_OUTP_V0_DP_MST_VCPI 0x78
+
+union nvif_outp_detect_args {
+ struct nvif_outp_detect_v0 {
+ __u8 version;
+#define NVIF_OUTP_DETECT_V0_NOT_PRESENT 0x00
+#define NVIF_OUTP_DETECT_V0_PRESENT 0x01
+#define NVIF_OUTP_DETECT_V0_UNKNOWN 0x02
+ __u8 status;
+ } v0;
+};
+
+union nvif_outp_edid_get_args {
+ struct nvif_outp_edid_get_v0 {
+ __u8 version;
+ __u8 pad01;
+ __u16 size;
+ __u8 data[2048];
+ } v0;
+};
union nvif_outp_load_detect_args {
struct nvif_outp_load_detect_v0 {
@@ -33,40 +101,39 @@ union nvif_outp_load_detect_args {
union nvif_outp_acquire_args {
struct nvif_outp_acquire_v0 {
__u8 version;
-#define NVIF_OUTP_ACQUIRE_V0_RGB_CRT 0x00
-#define NVIF_OUTP_ACQUIRE_V0_TV 0x01
-#define NVIF_OUTP_ACQUIRE_V0_TMDS 0x02
-#define NVIF_OUTP_ACQUIRE_V0_LVDS 0x03
-#define NVIF_OUTP_ACQUIRE_V0_DP 0x04
- __u8 proto;
+#define NVIF_OUTP_ACQUIRE_V0_DAC 0x00
+#define NVIF_OUTP_ACQUIRE_V0_SOR 0x01
+#define NVIF_OUTP_ACQUIRE_V0_PIOR 0x02
+ __u8 type;
__u8 or;
__u8 link;
__u8 pad04[4];
union {
struct {
- __u8 head;
- __u8 hdmi;
- __u8 hdmi_max_ac_packet;
- __u8 hdmi_rekey;
-#define NVIF_OUTP_ACQUIRE_V0_TMDS_HDMI_SCDC_SCRAMBLE (1 << 0)
-#define NVIF_OUTP_ACQUIRE_V0_TMDS_HDMI_SCDC_DIV_BY_4 (1 << 1)
- __u8 hdmi_scdc;
- __u8 hdmi_hda;
- __u8 pad06[2];
- } tmds;
- struct {
- __u8 dual;
- __u8 bpc8;
- __u8 pad02[6];
- } lvds;
+ __u8 hda;
+ } sor;
+ };
+ } v0;
+};
+
+union nvif_outp_inherit_args {
+ struct nvif_outp_inherit_v0 {
+ __u8 version;
+#define NVIF_OUTP_INHERIT_V0_RGB_CRT 0x00
+#define NVIF_OUTP_INHERIT_V0_TV 0x01
+#define NVIF_OUTP_INHERIT_V0_TMDS 0x02
+#define NVIF_OUTP_INHERIT_V0_LVDS 0x03
+#define NVIF_OUTP_INHERIT_V0_DP 0x04
+ // In/out. Input is one of the above values, output is the actual hw protocol
+ __u8 proto;
+ __u8 or;
+ __u8 link;
+ __u8 head;
+ union {
struct {
- __u8 link_nr; /* 0 = highest possible. */
- __u8 link_bw; /* 0 = highest possible, DP BW code otherwise. */
+ // TODO: Figure out padding, and whether we even want this field
__u8 hda;
- __u8 mst;
- __u8 pad04[4];
- __u8 dpcd[DP_RECEIVER_CAP_SIZE];
- } dp;
+ } tmds;
};
} v0;
};
@@ -76,6 +143,42 @@ union nvif_outp_release_args {
} vn;
};
+union nvif_outp_bl_get_args {
+ struct nvif_outp_bl_get_v0 {
+ __u8 version;
+ __u8 level;
+ } v0;
+};
+
+union nvif_outp_bl_set_args {
+ struct nvif_outp_bl_set_v0 {
+ __u8 version;
+ __u8 level;
+ } v0;
+};
+
+union nvif_outp_lvds_args {
+ struct nvif_outp_lvds_v0 {
+ __u8 version;
+ __u8 dual;
+ __u8 bpc8;
+ } v0;
+};
+
+union nvif_outp_hdmi_args {
+ struct nvif_outp_hdmi_v0 {
+ __u8 version;
+ __u8 head;
+ __u8 enable;
+ __u8 max_ac_packet;
+ __u8 rekey;
+ __u8 scdc;
+ __u8 scdc_scrambling;
+ __u8 scdc_low_rates;
+ __u32 khz;
+ } v0;
+};
+
union nvif_outp_infoframe_args {
struct nvif_outp_infoframe_v0 {
__u8 version;
@@ -105,9 +208,77 @@ union nvif_outp_dp_aux_pwr_args {
} v0;
};
-union nvif_outp_dp_retrain_args {
- struct nvif_outp_dp_retrain_vn {
- } vn;
+union nvif_outp_dp_aux_xfer_args {
+ struct nvif_outp_dp_aux_xfer_v0 {
+ __u8 version;
+ __u8 pad01;
+ __u8 type;
+ __u8 size;
+ __u32 addr;
+ __u8 data[16];
+ } v0;
+};
+
+union nvif_outp_dp_rates_args {
+ struct nvif_outp_dp_rates_v0 {
+ __u8 version;
+ __u8 pad01[6];
+ __u8 rates;
+ struct {
+ __s8 dpcd;
+ __u32 rate;
+ } rate[8];
+ } v0;
+};
+
+union nvif_outp_dp_train_args {
+ struct nvif_outp_dp_train_v0 {
+ __u8 version;
+ __u8 retrain;
+ __u8 mst;
+ __u8 lttprs;
+ __u8 post_lt_adj;
+ __u8 link_nr;
+ __u32 link_bw;
+ __u8 dpcd[DP_RECEIVER_CAP_SIZE];
+ } v0;
+};
+
+union nvif_outp_dp_drive_args {
+ struct nvif_outp_dp_drive_v0 {
+ __u8 version;
+ __u8 pad01[2];
+ __u8 lanes;
+ __u8 pe[4];
+ __u8 vs[4];
+ } v0;
+};
+
+union nvif_outp_dp_sst_args {
+ struct nvif_outp_dp_sst_v0 {
+ __u8 version;
+ __u8 head;
+ __u8 pad02[2];
+ __u32 watermark;
+ __u32 hblanksym;
+ __u32 vblanksym;
+ } v0;
+};
+
+union nvif_outp_dp_mst_id_put_args {
+ struct nvif_outp_dp_mst_id_put_v0 {
+ __u8 version;
+ __u8 pad01[3];
+ __u32 id;
+ } v0;
+};
+
+union nvif_outp_dp_mst_id_get_args {
+ struct nvif_outp_dp_mst_id_get_v0 {
+ __u8 version;
+ __u8 pad01[3];
+ __u32 id;
+ } v0;
};
union nvif_outp_dp_mst_vcpi_args {
diff --git a/drivers/gpu/drm/nouveau/include/nvif/outp.h b/drivers/gpu/drm/nouveau/include/nvif/outp.h
index fa76a7b5e..bc122a5ba 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/outp.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/outp.h
@@ -8,6 +8,46 @@ struct nvif_disp;
struct nvif_outp {
struct nvif_object object;
+ u32 id;
+
+ struct {
+ enum {
+ NVIF_OUTP_DAC,
+ NVIF_OUTP_SOR,
+ NVIF_OUTP_PIOR,
+ } type;
+
+ enum {
+ NVIF_OUTP_RGB_CRT,
+ NVIF_OUTP_TMDS,
+ NVIF_OUTP_LVDS,
+ NVIF_OUTP_DP,
+ } proto;
+
+ u8 heads;
+#define NVIF_OUTP_DDC_INVALID 0xff
+ u8 ddc;
+ u8 conn;
+
+ union {
+ struct {
+ u32 freq_max;
+ } rgb_crt;
+ struct {
+ bool dual;
+ } tmds;
+ struct {
+ bool acpi_edid;
+ } lvds;
+ struct {
+ u8 aux;
+ bool mst;
+ bool increased_wm;
+ u8 link_nr;
+ u32 link_bw;
+ } dp;
+ };
+ } info;
struct {
int id;
@@ -17,18 +57,60 @@ struct nvif_outp {
int nvif_outp_ctor(struct nvif_disp *, const char *name, int id, struct nvif_outp *);
void nvif_outp_dtor(struct nvif_outp *);
+
+enum nvif_outp_detect_status {
+ NOT_PRESENT,
+ PRESENT,
+ UNKNOWN,
+};
+
+enum nvif_outp_detect_status nvif_outp_detect(struct nvif_outp *);
+int nvif_outp_edid_get(struct nvif_outp *, u8 **pedid);
+
int nvif_outp_load_detect(struct nvif_outp *, u32 loadval);
-int nvif_outp_acquire_rgb_crt(struct nvif_outp *);
-int nvif_outp_acquire_tmds(struct nvif_outp *, int head,
- bool hdmi, u8 max_ac_packet, u8 rekey, u8 scdc, bool hda);
-int nvif_outp_acquire_lvds(struct nvif_outp *, bool dual, bool bpc8);
-int nvif_outp_acquire_dp(struct nvif_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE],
- int link_nr, int link_bw, bool hda, bool mst);
+int nvif_outp_acquire_dac(struct nvif_outp *);
+int nvif_outp_acquire_sor(struct nvif_outp *, bool hda);
+int nvif_outp_acquire_pior(struct nvif_outp *);
+int nvif_outp_inherit_rgb_crt(struct nvif_outp *outp, u8 *proto_out);
+int nvif_outp_inherit_lvds(struct nvif_outp *outp, u8 *proto_out);
+int nvif_outp_inherit_tmds(struct nvif_outp *outp, u8 *proto_out);
+int nvif_outp_inherit_dp(struct nvif_outp *outp, u8 *proto_out);
+
void nvif_outp_release(struct nvif_outp *);
+
+static inline bool
+nvif_outp_acquired(struct nvif_outp *outp)
+{
+ return outp->or.id >= 0;
+}
+
+int nvif_outp_bl_get(struct nvif_outp *);
+int nvif_outp_bl_set(struct nvif_outp *, int level);
+
+int nvif_outp_lvds(struct nvif_outp *, bool dual, bool bpc8);
+
+int nvif_outp_hdmi(struct nvif_outp *, int head, bool enable, u8 max_ac_packet, u8 rekey, u32 khz,
+ bool scdc, bool scdc_scrambling, bool scdc_low_rates);
+
int nvif_outp_infoframe(struct nvif_outp *, u8 type, struct nvif_outp_infoframe_v0 *, u32 size);
int nvif_outp_hda_eld(struct nvif_outp *, int head, void *data, u32 size);
+
int nvif_outp_dp_aux_pwr(struct nvif_outp *, bool enable);
-int nvif_outp_dp_retrain(struct nvif_outp *);
+int nvif_outp_dp_aux_xfer(struct nvif_outp *, u8 type, u8 *size, u32 addr, u8 *data);
+
+struct nvif_outp_dp_rate {
+ int dpcd; /* -1 for non-indexed rates */
+ u32 rate;
+};
+
+int nvif_outp_dp_rates(struct nvif_outp *, struct nvif_outp_dp_rate *rate, int rate_nr);
+int nvif_outp_dp_train(struct nvif_outp *, u8 dpcd[DP_RECEIVER_CAP_SIZE],
+ u8 lttprs, u8 link_nr, u32 link_bw, bool mst, bool post_lt_adj,
+ bool retrain);
+int nvif_outp_dp_drive(struct nvif_outp *, u8 link_nr, u8 pe[4], u8 vs[4]);
+int nvif_outp_dp_sst(struct nvif_outp *, int head, u32 watermark, u32 hblanksym, u32 vblanksym);
+int nvif_outp_dp_mst_id_get(struct nvif_outp *, u32 *id);
+int nvif_outp_dp_mst_id_put(struct nvif_outp *, u32 id);
int nvif_outp_dp_mst_vcpi(struct nvif_outp *, int head,
u8 start_slot, u8 num_slots, u16 pbn, u16 aligned_pbn);
#endif
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-01 19:51:36 +0000