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-rw-r--r--drivers/iio/cdc/Kconfig27
-rw-r--r--drivers/iio/cdc/Makefile7
-rw-r--r--drivers/iio/cdc/ad7150.c657
-rw-r--r--drivers/iio/cdc/ad7746.c819
4 files changed, 1510 insertions, 0 deletions
diff --git a/drivers/iio/cdc/Kconfig b/drivers/iio/cdc/Kconfig
new file mode 100644
index 0000000000..e0a5ce66a9
--- /dev/null
+++ b/drivers/iio/cdc/Kconfig
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# CDC drivers
+#
+menu "Capacitance to digital converters"
+
+config AD7150
+ tristate "Analog Devices ad7150/1/6 capacitive sensor driver"
+ depends on I2C
+ help
+ Say yes here to build support for Analog Devices capacitive sensors.
+ (ad7150, ad7151, ad7156) Provides direct access via sysfs.
+
+ To compile this driver as a module, choose M here: the
+ module will be called ad7150.
+
+config AD7746
+ tristate "Analog Devices AD7745, AD7746 AD7747 capacitive sensor driver"
+ depends on I2C
+ help
+ Say yes here to build support for Analog Devices capacitive sensors.
+ (AD7745, AD7746, AD7747) Provides direct access via sysfs.
+
+ To compile this driver as a module, choose M here: the
+ module will be called ad7746.
+
+endmenu
diff --git a/drivers/iio/cdc/Makefile b/drivers/iio/cdc/Makefile
new file mode 100644
index 0000000000..41db756d80
--- /dev/null
+++ b/drivers/iio/cdc/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for industrial I/O capacitance to digital converter (CDC) drivers
+#
+
+obj-$(CONFIG_AD7150) += ad7150.o
+obj-$(CONFIG_AD7746) += ad7746.o
diff --git a/drivers/iio/cdc/ad7150.c b/drivers/iio/cdc/ad7150.c
new file mode 100644
index 0000000000..4c03b9e834
--- /dev/null
+++ b/drivers/iio/cdc/ad7150.c
@@ -0,0 +1,657 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * AD7150 capacitive sensor driver supporting AD7150/1/6
+ *
+ * Copyright 2010-2011 Analog Devices Inc.
+ * Copyright 2021 Jonathan Cameron <Jonathan.Cameron@huawei.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/i2c.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+
+#include <linux/iio/iio.h>
+#include <linux/iio/sysfs.h>
+#include <linux/iio/events.h>
+
+#define AD7150_STATUS_REG 0
+#define AD7150_STATUS_OUT1 BIT(3)
+#define AD7150_STATUS_OUT2 BIT(5)
+#define AD7150_CH1_DATA_HIGH_REG 1
+#define AD7150_CH2_DATA_HIGH_REG 3
+#define AD7150_CH1_AVG_HIGH_REG 5
+#define AD7150_CH2_AVG_HIGH_REG 7
+#define AD7150_CH1_SENSITIVITY_REG 9
+#define AD7150_CH1_THR_HOLD_H_REG 9
+#define AD7150_CH1_TIMEOUT_REG 10
+#define AD7150_CH_TIMEOUT_RECEDING GENMASK(3, 0)
+#define AD7150_CH_TIMEOUT_APPROACHING GENMASK(7, 4)
+#define AD7150_CH1_SETUP_REG 11
+#define AD7150_CH2_SENSITIVITY_REG 12
+#define AD7150_CH2_THR_HOLD_H_REG 12
+#define AD7150_CH2_TIMEOUT_REG 13
+#define AD7150_CH2_SETUP_REG 14
+#define AD7150_CFG_REG 15
+#define AD7150_CFG_FIX BIT(7)
+#define AD7150_CFG_THRESHTYPE_MSK GENMASK(6, 5)
+#define AD7150_CFG_TT_NEG 0x0
+#define AD7150_CFG_TT_POS 0x1
+#define AD7150_CFG_TT_IN_WINDOW 0x2
+#define AD7150_CFG_TT_OUT_WINDOW 0x3
+#define AD7150_PD_TIMER_REG 16
+#define AD7150_CH1_CAPDAC_REG 17
+#define AD7150_CH2_CAPDAC_REG 18
+#define AD7150_SN3_REG 19
+#define AD7150_SN2_REG 20
+#define AD7150_SN1_REG 21
+#define AD7150_SN0_REG 22
+#define AD7150_ID_REG 23
+
+enum {
+ AD7150,
+ AD7151,
+};
+
+/**
+ * struct ad7150_chip_info - instance specific chip data
+ * @client: i2c client for this device
+ * @threshold: thresholds for simple capacitance value events
+ * @thresh_sensitivity: threshold for simple capacitance offset
+ * from 'average' value.
+ * @thresh_timeout: a timeout, in samples from the moment an
+ * adaptive threshold event occurs to when the average
+ * value jumps to current value. Note made up of two fields,
+ * 3:0 are for timeout receding - applies if below lower threshold
+ * 7:4 are for timeout approaching - applies if above upper threshold
+ * @state_lock: ensure consistent state of this structure wrt the
+ * hardware.
+ * @interrupts: one or two interrupt numbers depending on device type.
+ * @int_enabled: is a given interrupt currently enabled.
+ * @type: threshold type
+ * @dir: threshold direction
+ */
+struct ad7150_chip_info {
+ struct i2c_client *client;
+ u16 threshold[2][2];
+ u8 thresh_sensitivity[2][2];
+ u8 thresh_timeout[2][2];
+ struct mutex state_lock;
+ int interrupts[2];
+ bool int_enabled[2];
+ enum iio_event_type type;
+ enum iio_event_direction dir;
+};
+
+static const u8 ad7150_addresses[][6] = {
+ { AD7150_CH1_DATA_HIGH_REG, AD7150_CH1_AVG_HIGH_REG,
+ AD7150_CH1_SETUP_REG, AD7150_CH1_THR_HOLD_H_REG,
+ AD7150_CH1_SENSITIVITY_REG, AD7150_CH1_TIMEOUT_REG },
+ { AD7150_CH2_DATA_HIGH_REG, AD7150_CH2_AVG_HIGH_REG,
+ AD7150_CH2_SETUP_REG, AD7150_CH2_THR_HOLD_H_REG,
+ AD7150_CH2_SENSITIVITY_REG, AD7150_CH2_TIMEOUT_REG },
+};
+
+static int ad7150_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val,
+ int *val2,
+ long mask)
+{
+ struct ad7150_chip_info *chip = iio_priv(indio_dev);
+ int channel = chan->channel;
+ int ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ ret = i2c_smbus_read_word_swapped(chip->client,
+ ad7150_addresses[channel][0]);
+ if (ret < 0)
+ return ret;
+ *val = ret >> 4;
+
+ return IIO_VAL_INT;
+ case IIO_CHAN_INFO_AVERAGE_RAW:
+ ret = i2c_smbus_read_word_swapped(chip->client,
+ ad7150_addresses[channel][1]);
+ if (ret < 0)
+ return ret;
+ *val = ret;
+
+ return IIO_VAL_INT;
+ case IIO_CHAN_INFO_SCALE:
+ /*
+ * Base units for capacitance are nano farads and the value
+ * calculated from the datasheet formula is in picofarad
+ * so multiply by 1000
+ */
+ *val = 1000;
+ *val2 = 40944 >> 4; /* To match shift in _RAW */
+ return IIO_VAL_FRACTIONAL;
+ case IIO_CHAN_INFO_OFFSET:
+ *val = -(12288 >> 4); /* To match shift in _RAW */
+ return IIO_VAL_INT;
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ /* Strangely same for both 1 and 2 chan parts */
+ *val = 100;
+ return IIO_VAL_INT;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int ad7150_read_event_config(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum iio_event_type type,
+ enum iio_event_direction dir)
+{
+ struct ad7150_chip_info *chip = iio_priv(indio_dev);
+ u8 threshtype;
+ bool thrfixed;
+ int ret;
+
+ ret = i2c_smbus_read_byte_data(chip->client, AD7150_CFG_REG);
+ if (ret < 0)
+ return ret;
+
+ threshtype = FIELD_GET(AD7150_CFG_THRESHTYPE_MSK, ret);
+
+ /*check if threshold mode is fixed or adaptive*/
+ thrfixed = FIELD_GET(AD7150_CFG_FIX, ret);
+
+ switch (type) {
+ case IIO_EV_TYPE_THRESH_ADAPTIVE:
+ if (dir == IIO_EV_DIR_RISING)
+ return !thrfixed && (threshtype == AD7150_CFG_TT_POS);
+ return !thrfixed && (threshtype == AD7150_CFG_TT_NEG);
+ case IIO_EV_TYPE_THRESH:
+ if (dir == IIO_EV_DIR_RISING)
+ return thrfixed && (threshtype == AD7150_CFG_TT_POS);
+ return thrfixed && (threshtype == AD7150_CFG_TT_NEG);
+ default:
+ break;
+ }
+ return -EINVAL;
+}
+
+/* state_lock should be held to ensure consistent state */
+static int ad7150_write_event_params(struct iio_dev *indio_dev,
+ unsigned int chan,
+ enum iio_event_type type,
+ enum iio_event_direction dir)
+{
+ struct ad7150_chip_info *chip = iio_priv(indio_dev);
+ int rising = (dir == IIO_EV_DIR_RISING);
+
+ /* Only update value live, if parameter is in use */
+ if ((type != chip->type) || (dir != chip->dir))
+ return 0;
+
+ switch (type) {
+ /* Note completely different from the adaptive versions */
+ case IIO_EV_TYPE_THRESH: {
+ u16 value = chip->threshold[rising][chan];
+ return i2c_smbus_write_word_swapped(chip->client,
+ ad7150_addresses[chan][3],
+ value);
+ }
+ case IIO_EV_TYPE_THRESH_ADAPTIVE: {
+ int ret;
+ u8 sens, timeout;
+
+ sens = chip->thresh_sensitivity[rising][chan];
+ ret = i2c_smbus_write_byte_data(chip->client,
+ ad7150_addresses[chan][4],
+ sens);
+ if (ret)
+ return ret;
+
+ /*
+ * Single timeout register contains timeouts for both
+ * directions.
+ */
+ timeout = FIELD_PREP(AD7150_CH_TIMEOUT_APPROACHING,
+ chip->thresh_timeout[1][chan]);
+ timeout |= FIELD_PREP(AD7150_CH_TIMEOUT_RECEDING,
+ chip->thresh_timeout[0][chan]);
+ return i2c_smbus_write_byte_data(chip->client,
+ ad7150_addresses[chan][5],
+ timeout);
+ }
+ default:
+ return -EINVAL;
+ }
+}
+
+static int ad7150_write_event_config(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum iio_event_type type,
+ enum iio_event_direction dir, int state)
+{
+ struct ad7150_chip_info *chip = iio_priv(indio_dev);
+ int ret = 0;
+
+ /*
+ * There is only a single shared control and no on chip
+ * interrupt disables for the two interrupt lines.
+ * So, enabling will switch the events configured to enable
+ * whatever was most recently requested and if necessary enable_irq()
+ * the interrupt and any disable will disable_irq() for that
+ * channels interrupt.
+ */
+ if (!state) {
+ if ((chip->int_enabled[chan->channel]) &&
+ (type == chip->type) && (dir == chip->dir)) {
+ disable_irq(chip->interrupts[chan->channel]);
+ chip->int_enabled[chan->channel] = false;
+ }
+ return 0;
+ }
+
+ mutex_lock(&chip->state_lock);
+ if ((type != chip->type) || (dir != chip->dir)) {
+ int rising = (dir == IIO_EV_DIR_RISING);
+ u8 thresh_type, cfg, fixed;
+
+ /*
+ * Need to temporarily disable both interrupts if
+ * enabled - this is to avoid races around changing
+ * config and thresholds.
+ * Note enable/disable_irq() are reference counted so
+ * no need to check if already enabled.
+ */
+ disable_irq(chip->interrupts[0]);
+ disable_irq(chip->interrupts[1]);
+
+ ret = i2c_smbus_read_byte_data(chip->client, AD7150_CFG_REG);
+ if (ret < 0)
+ goto error_ret;
+
+ cfg = ret & ~(AD7150_CFG_THRESHTYPE_MSK | AD7150_CFG_FIX);
+
+ if (type == IIO_EV_TYPE_THRESH_ADAPTIVE)
+ fixed = 0;
+ else
+ fixed = 1;
+
+ if (rising)
+ thresh_type = AD7150_CFG_TT_POS;
+ else
+ thresh_type = AD7150_CFG_TT_NEG;
+
+ cfg |= FIELD_PREP(AD7150_CFG_FIX, fixed) |
+ FIELD_PREP(AD7150_CFG_THRESHTYPE_MSK, thresh_type);
+
+ ret = i2c_smbus_write_byte_data(chip->client, AD7150_CFG_REG,
+ cfg);
+ if (ret < 0)
+ goto error_ret;
+
+ /*
+ * There is a potential race condition here, but not easy
+ * to close given we can't disable the interrupt at the
+ * chip side of things. Rely on the status bit.
+ */
+ chip->type = type;
+ chip->dir = dir;
+
+ /* update control attributes */
+ ret = ad7150_write_event_params(indio_dev, chan->channel, type,
+ dir);
+ if (ret)
+ goto error_ret;
+ /* reenable any irq's we disabled whilst changing mode */
+ enable_irq(chip->interrupts[0]);
+ enable_irq(chip->interrupts[1]);
+ }
+ if (!chip->int_enabled[chan->channel]) {
+ enable_irq(chip->interrupts[chan->channel]);
+ chip->int_enabled[chan->channel] = true;
+ }
+
+error_ret:
+ mutex_unlock(&chip->state_lock);
+
+ return ret;
+}
+
+static int ad7150_read_event_value(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum iio_event_type type,
+ enum iio_event_direction dir,
+ enum iio_event_info info,
+ int *val, int *val2)
+{
+ struct ad7150_chip_info *chip = iio_priv(indio_dev);
+ int rising = (dir == IIO_EV_DIR_RISING);
+
+ /* Complex register sharing going on here */
+ switch (info) {
+ case IIO_EV_INFO_VALUE:
+ switch (type) {
+ case IIO_EV_TYPE_THRESH_ADAPTIVE:
+ *val = chip->thresh_sensitivity[rising][chan->channel];
+ return IIO_VAL_INT;
+ case IIO_EV_TYPE_THRESH:
+ *val = chip->threshold[rising][chan->channel];
+ return IIO_VAL_INT;
+ default:
+ return -EINVAL;
+ }
+ case IIO_EV_INFO_TIMEOUT:
+ *val = 0;
+ *val2 = chip->thresh_timeout[rising][chan->channel] * 10000;
+ return IIO_VAL_INT_PLUS_MICRO;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int ad7150_write_event_value(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan,
+ enum iio_event_type type,
+ enum iio_event_direction dir,
+ enum iio_event_info info,
+ int val, int val2)
+{
+ int ret;
+ struct ad7150_chip_info *chip = iio_priv(indio_dev);
+ int rising = (dir == IIO_EV_DIR_RISING);
+
+ mutex_lock(&chip->state_lock);
+ switch (info) {
+ case IIO_EV_INFO_VALUE:
+ switch (type) {
+ case IIO_EV_TYPE_THRESH_ADAPTIVE:
+ chip->thresh_sensitivity[rising][chan->channel] = val;
+ break;
+ case IIO_EV_TYPE_THRESH:
+ chip->threshold[rising][chan->channel] = val;
+ break;
+ default:
+ ret = -EINVAL;
+ goto error_ret;
+ }
+ break;
+ case IIO_EV_INFO_TIMEOUT: {
+ /*
+ * Raw timeout is in cycles of 10 msecs as long as both
+ * channels are enabled.
+ * In terms of INT_PLUS_MICRO, that is in units of 10,000
+ */
+ int timeout = val2 / 10000;
+
+ if (val != 0 || timeout < 0 || timeout > 15 || val2 % 10000) {
+ ret = -EINVAL;
+ goto error_ret;
+ }
+
+ chip->thresh_timeout[rising][chan->channel] = timeout;
+ break;
+ }
+ default:
+ ret = -EINVAL;
+ goto error_ret;
+ }
+
+ /* write back if active */
+ ret = ad7150_write_event_params(indio_dev, chan->channel, type, dir);
+
+error_ret:
+ mutex_unlock(&chip->state_lock);
+ return ret;
+}
+
+static const struct iio_event_spec ad7150_events[] = {
+ {
+ .type = IIO_EV_TYPE_THRESH,
+ .dir = IIO_EV_DIR_RISING,
+ .mask_separate = BIT(IIO_EV_INFO_VALUE) |
+ BIT(IIO_EV_INFO_ENABLE),
+ }, {
+ .type = IIO_EV_TYPE_THRESH,
+ .dir = IIO_EV_DIR_FALLING,
+ .mask_separate = BIT(IIO_EV_INFO_VALUE) |
+ BIT(IIO_EV_INFO_ENABLE),
+ }, {
+ .type = IIO_EV_TYPE_THRESH_ADAPTIVE,
+ .dir = IIO_EV_DIR_RISING,
+ .mask_separate = BIT(IIO_EV_INFO_VALUE) |
+ BIT(IIO_EV_INFO_ENABLE) |
+ BIT(IIO_EV_INFO_TIMEOUT),
+ }, {
+ .type = IIO_EV_TYPE_THRESH_ADAPTIVE,
+ .dir = IIO_EV_DIR_FALLING,
+ .mask_separate = BIT(IIO_EV_INFO_VALUE) |
+ BIT(IIO_EV_INFO_ENABLE) |
+ BIT(IIO_EV_INFO_TIMEOUT),
+ },
+};
+
+#define AD7150_CAPACITANCE_CHAN(_chan) { \
+ .type = IIO_CAPACITANCE, \
+ .indexed = 1, \
+ .channel = _chan, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
+ BIT(IIO_CHAN_INFO_OFFSET), \
+ .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
+ .event_spec = ad7150_events, \
+ .num_event_specs = ARRAY_SIZE(ad7150_events), \
+ }
+
+#define AD7150_CAPACITANCE_CHAN_NO_IRQ(_chan) { \
+ .type = IIO_CAPACITANCE, \
+ .indexed = 1, \
+ .channel = _chan, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
+ BIT(IIO_CHAN_INFO_OFFSET), \
+ .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
+ }
+
+static const struct iio_chan_spec ad7150_channels[] = {
+ AD7150_CAPACITANCE_CHAN(0),
+ AD7150_CAPACITANCE_CHAN(1),
+};
+
+static const struct iio_chan_spec ad7150_channels_no_irq[] = {
+ AD7150_CAPACITANCE_CHAN_NO_IRQ(0),
+ AD7150_CAPACITANCE_CHAN_NO_IRQ(1),
+};
+
+static const struct iio_chan_spec ad7151_channels[] = {
+ AD7150_CAPACITANCE_CHAN(0),
+};
+
+static const struct iio_chan_spec ad7151_channels_no_irq[] = {
+ AD7150_CAPACITANCE_CHAN_NO_IRQ(0),
+};
+
+static irqreturn_t __ad7150_event_handler(void *private, u8 status_mask,
+ int channel)
+{
+ struct iio_dev *indio_dev = private;
+ struct ad7150_chip_info *chip = iio_priv(indio_dev);
+ s64 timestamp = iio_get_time_ns(indio_dev);
+ int int_status;
+
+ int_status = i2c_smbus_read_byte_data(chip->client, AD7150_STATUS_REG);
+ if (int_status < 0)
+ return IRQ_HANDLED;
+
+ if (!(int_status & status_mask))
+ return IRQ_HANDLED;
+
+ iio_push_event(indio_dev,
+ IIO_UNMOD_EVENT_CODE(IIO_CAPACITANCE, channel,
+ chip->type, chip->dir),
+ timestamp);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t ad7150_event_handler_ch1(int irq, void *private)
+{
+ return __ad7150_event_handler(private, AD7150_STATUS_OUT1, 0);
+}
+
+static irqreturn_t ad7150_event_handler_ch2(int irq, void *private)
+{
+ return __ad7150_event_handler(private, AD7150_STATUS_OUT2, 1);
+}
+
+static IIO_CONST_ATTR(in_capacitance_thresh_adaptive_timeout_available,
+ "[0 0.01 0.15]");
+
+static struct attribute *ad7150_event_attributes[] = {
+ &iio_const_attr_in_capacitance_thresh_adaptive_timeout_available
+ .dev_attr.attr,
+ NULL,
+};
+
+static const struct attribute_group ad7150_event_attribute_group = {
+ .attrs = ad7150_event_attributes,
+ .name = "events",
+};
+
+static const struct iio_info ad7150_info = {
+ .event_attrs = &ad7150_event_attribute_group,
+ .read_raw = &ad7150_read_raw,
+ .read_event_config = &ad7150_read_event_config,
+ .write_event_config = &ad7150_write_event_config,
+ .read_event_value = &ad7150_read_event_value,
+ .write_event_value = &ad7150_write_event_value,
+};
+
+static const struct iio_info ad7150_info_no_irq = {
+ .read_raw = &ad7150_read_raw,
+};
+
+static int ad7150_probe(struct i2c_client *client)
+{
+ const struct i2c_device_id *id = i2c_client_get_device_id(client);
+ struct ad7150_chip_info *chip;
+ struct iio_dev *indio_dev;
+ bool use_irq = true;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
+ if (!indio_dev)
+ return -ENOMEM;
+
+ chip = iio_priv(indio_dev);
+ mutex_init(&chip->state_lock);
+ chip->client = client;
+
+ indio_dev->name = id->name;
+
+ indio_dev->modes = INDIO_DIRECT_MODE;
+
+ ret = devm_regulator_get_enable(&client->dev, "vdd");
+ if (ret)
+ return ret;
+
+ chip->interrupts[0] = fwnode_irq_get(dev_fwnode(&client->dev), 0);
+ if (chip->interrupts[0] < 0)
+ use_irq = false;
+ else if (id->driver_data == AD7150) {
+ chip->interrupts[1] = fwnode_irq_get(dev_fwnode(&client->dev), 1);
+ if (chip->interrupts[1] < 0)
+ use_irq = false;
+ }
+ if (use_irq) {
+ irq_set_status_flags(chip->interrupts[0], IRQ_NOAUTOEN);
+ ret = devm_request_threaded_irq(&client->dev,
+ chip->interrupts[0],
+ NULL,
+ &ad7150_event_handler_ch1,
+ IRQF_TRIGGER_RISING |
+ IRQF_ONESHOT,
+ "ad7150_irq1",
+ indio_dev);
+ if (ret)
+ return ret;
+
+ indio_dev->info = &ad7150_info;
+ switch (id->driver_data) {
+ case AD7150:
+ indio_dev->channels = ad7150_channels;
+ indio_dev->num_channels = ARRAY_SIZE(ad7150_channels);
+ irq_set_status_flags(chip->interrupts[1], IRQ_NOAUTOEN);
+ ret = devm_request_threaded_irq(&client->dev,
+ chip->interrupts[1],
+ NULL,
+ &ad7150_event_handler_ch2,
+ IRQF_TRIGGER_RISING |
+ IRQF_ONESHOT,
+ "ad7150_irq2",
+ indio_dev);
+ if (ret)
+ return ret;
+ break;
+ case AD7151:
+ indio_dev->channels = ad7151_channels;
+ indio_dev->num_channels = ARRAY_SIZE(ad7151_channels);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ } else {
+ indio_dev->info = &ad7150_info_no_irq;
+ switch (id->driver_data) {
+ case AD7150:
+ indio_dev->channels = ad7150_channels_no_irq;
+ indio_dev->num_channels =
+ ARRAY_SIZE(ad7150_channels_no_irq);
+ break;
+ case AD7151:
+ indio_dev->channels = ad7151_channels_no_irq;
+ indio_dev->num_channels =
+ ARRAY_SIZE(ad7151_channels_no_irq);
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ return devm_iio_device_register(indio_dev->dev.parent, indio_dev);
+}
+
+static const struct i2c_device_id ad7150_id[] = {
+ { "ad7150", AD7150 },
+ { "ad7151", AD7151 },
+ { "ad7156", AD7150 },
+ {}
+};
+
+MODULE_DEVICE_TABLE(i2c, ad7150_id);
+
+static const struct of_device_id ad7150_of_match[] = {
+ { "adi,ad7150" },
+ { "adi,ad7151" },
+ { "adi,ad7156" },
+ {}
+};
+static struct i2c_driver ad7150_driver = {
+ .driver = {
+ .name = "ad7150",
+ .of_match_table = ad7150_of_match,
+ },
+ .probe = ad7150_probe,
+ .id_table = ad7150_id,
+};
+module_i2c_driver(ad7150_driver);
+
+MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
+MODULE_DESCRIPTION("Analog Devices AD7150/1/6 capacitive sensor driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/iio/cdc/ad7746.c b/drivers/iio/cdc/ad7746.c
new file mode 100644
index 0000000000..d11bc3496d
--- /dev/null
+++ b/drivers/iio/cdc/ad7746.c
@@ -0,0 +1,819 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AD7746 capacitive sensor driver supporting AD7745, AD7746 and AD7747
+ *
+ * Copyright 2011 Analog Devices Inc.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/stat.h>
+#include <linux/sysfs.h>
+
+#include <asm/unaligned.h>
+
+#include <linux/iio/iio.h>
+#include <linux/iio/sysfs.h>
+
+/* AD7746 Register Definition */
+
+#define AD7746_REG_STATUS 0
+#define AD7746_REG_CAP_DATA_HIGH 1
+#define AD7746_REG_VT_DATA_HIGH 4
+#define AD7746_REG_CAP_SETUP 7
+#define AD7746_REG_VT_SETUP 8
+#define AD7746_REG_EXC_SETUP 9
+#define AD7746_REG_CFG 10
+#define AD7746_REG_CAPDACA 11
+#define AD7746_REG_CAPDACB 12
+#define AD7746_REG_CAP_OFFH 13
+#define AD7746_REG_CAP_GAINH 15
+#define AD7746_REG_VOLT_GAINH 17
+
+/* Status Register Bit Designations (AD7746_REG_STATUS) */
+#define AD7746_STATUS_EXCERR BIT(3)
+#define AD7746_STATUS_RDY BIT(2)
+#define AD7746_STATUS_RDYVT BIT(1)
+#define AD7746_STATUS_RDYCAP BIT(0)
+
+/* Capacitive Channel Setup Register Bit Designations (AD7746_REG_CAP_SETUP) */
+#define AD7746_CAPSETUP_CAPEN BIT(7)
+#define AD7746_CAPSETUP_CIN2 BIT(6) /* AD7746 only */
+#define AD7746_CAPSETUP_CAPDIFF BIT(5)
+#define AD7746_CAPSETUP_CACHOP BIT(0)
+
+/* Voltage/Temperature Setup Register Bit Designations (AD7746_REG_VT_SETUP) */
+#define AD7746_VTSETUP_VTEN BIT(7)
+#define AD7746_VTSETUP_VTMD_MASK GENMASK(6, 5)
+#define AD7746_VTSETUP_VTMD_INT_TEMP 0
+#define AD7746_VTSETUP_VTMD_EXT_TEMP 1
+#define AD7746_VTSETUP_VTMD_VDD_MON 2
+#define AD7746_VTSETUP_VTMD_EXT_VIN 3
+#define AD7746_VTSETUP_EXTREF BIT(4)
+#define AD7746_VTSETUP_VTSHORT BIT(1)
+#define AD7746_VTSETUP_VTCHOP BIT(0)
+
+/* Excitation Setup Register Bit Designations (AD7746_REG_EXC_SETUP) */
+#define AD7746_EXCSETUP_CLKCTRL BIT(7)
+#define AD7746_EXCSETUP_EXCON BIT(6)
+#define AD7746_EXCSETUP_EXCB BIT(5)
+#define AD7746_EXCSETUP_NEXCB BIT(4)
+#define AD7746_EXCSETUP_EXCA BIT(3)
+#define AD7746_EXCSETUP_NEXCA BIT(2)
+#define AD7746_EXCSETUP_EXCLVL_MASK GENMASK(1, 0)
+
+/* Config Register Bit Designations (AD7746_REG_CFG) */
+#define AD7746_CONF_VTFS_MASK GENMASK(7, 6)
+#define AD7746_CONF_CAPFS_MASK GENMASK(5, 3)
+#define AD7746_CONF_MODE_MASK GENMASK(2, 0)
+#define AD7746_CONF_MODE_IDLE 0
+#define AD7746_CONF_MODE_CONT_CONV 1
+#define AD7746_CONF_MODE_SINGLE_CONV 2
+#define AD7746_CONF_MODE_PWRDN 3
+#define AD7746_CONF_MODE_OFFS_CAL 5
+#define AD7746_CONF_MODE_GAIN_CAL 6
+
+/* CAPDAC Register Bit Designations (AD7746_REG_CAPDACx) */
+#define AD7746_CAPDAC_DACEN BIT(7)
+#define AD7746_CAPDAC_DACP_MASK GENMASK(6, 0)
+
+struct ad7746_chip_info {
+ struct i2c_client *client;
+ struct mutex lock; /* protect sensor state */
+ /*
+ * Capacitive channel digital filter setup;
+ * conversion time/update rate setup per channel
+ */
+ u8 config;
+ u8 cap_setup;
+ u8 vt_setup;
+ u8 capdac[2][2];
+ s8 capdac_set;
+};
+
+enum ad7746_chan {
+ VIN,
+ VIN_VDD,
+ TEMP_INT,
+ TEMP_EXT,
+ CIN1,
+ CIN1_DIFF,
+ CIN2,
+ CIN2_DIFF,
+};
+
+struct ad7746_chan_info {
+ u8 addr;
+ union {
+ u8 vtmd;
+ struct { /* CAP SETUP fields */
+ unsigned int cin2 : 1;
+ unsigned int capdiff : 1;
+ };
+ };
+};
+
+static const struct ad7746_chan_info ad7746_chan_info[] = {
+ [VIN] = {
+ .addr = AD7746_REG_VT_DATA_HIGH,
+ .vtmd = AD7746_VTSETUP_VTMD_EXT_VIN,
+ },
+ [VIN_VDD] = {
+ .addr = AD7746_REG_VT_DATA_HIGH,
+ .vtmd = AD7746_VTSETUP_VTMD_VDD_MON,
+ },
+ [TEMP_INT] = {
+ .addr = AD7746_REG_VT_DATA_HIGH,
+ .vtmd = AD7746_VTSETUP_VTMD_INT_TEMP,
+ },
+ [TEMP_EXT] = {
+ .addr = AD7746_REG_VT_DATA_HIGH,
+ .vtmd = AD7746_VTSETUP_VTMD_EXT_TEMP,
+ },
+ [CIN1] = {
+ .addr = AD7746_REG_CAP_DATA_HIGH,
+ },
+ [CIN1_DIFF] = {
+ .addr = AD7746_REG_CAP_DATA_HIGH,
+ .capdiff = 1,
+ },
+ [CIN2] = {
+ .addr = AD7746_REG_CAP_DATA_HIGH,
+ .cin2 = 1,
+ },
+ [CIN2_DIFF] = {
+ .addr = AD7746_REG_CAP_DATA_HIGH,
+ .cin2 = 1,
+ .capdiff = 1,
+ },
+};
+
+static const struct iio_chan_spec ad7746_channels[] = {
+ [VIN] = {
+ .type = IIO_VOLTAGE,
+ .indexed = 1,
+ .channel = 0,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .address = VIN,
+ },
+ [VIN_VDD] = {
+ .type = IIO_VOLTAGE,
+ .indexed = 1,
+ .channel = 1,
+ .extend_name = "supply",
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .address = VIN_VDD,
+ },
+ [TEMP_INT] = {
+ .type = IIO_TEMP,
+ .indexed = 1,
+ .channel = 0,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
+ .address = TEMP_INT,
+ },
+ [TEMP_EXT] = {
+ .type = IIO_TEMP,
+ .indexed = 1,
+ .channel = 1,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
+ .address = TEMP_EXT,
+ },
+ [CIN1] = {
+ .type = IIO_CAPACITANCE,
+ .indexed = 1,
+ .channel = 0,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+ BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET),
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) |
+ BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .address = CIN1,
+ },
+ [CIN1_DIFF] = {
+ .type = IIO_CAPACITANCE,
+ .differential = 1,
+ .indexed = 1,
+ .channel = 0,
+ .channel2 = 2,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+ BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_ZEROPOINT),
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) |
+ BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .address = CIN1_DIFF,
+ },
+ [CIN2] = {
+ .type = IIO_CAPACITANCE,
+ .indexed = 1,
+ .channel = 1,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+ BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET),
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) |
+ BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .address = CIN2,
+ },
+ [CIN2_DIFF] = {
+ .type = IIO_CAPACITANCE,
+ .differential = 1,
+ .indexed = 1,
+ .channel = 1,
+ .channel2 = 3,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+ BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_ZEROPOINT),
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) |
+ BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
+ .address = CIN2_DIFF,
+ }
+};
+
+/* Values are Update Rate (Hz), Conversion Time (ms) + 1*/
+static const unsigned char ad7746_vt_filter_rate_table[][2] = {
+ { 50, 20 + 1 }, { 31, 32 + 1 }, { 16, 62 + 1 }, { 8, 122 + 1 },
+};
+
+static const unsigned char ad7746_cap_filter_rate_table[][2] = {
+ { 91, 11 + 1 }, { 84, 12 + 1 }, { 50, 20 + 1 }, { 26, 38 + 1 },
+ { 16, 62 + 1 }, { 13, 77 + 1 }, { 11, 92 + 1 }, { 9, 110 + 1 },
+};
+
+static int ad7746_set_capdac(struct ad7746_chip_info *chip, int channel)
+{
+ int ret = i2c_smbus_write_byte_data(chip->client,
+ AD7746_REG_CAPDACA,
+ chip->capdac[channel][0]);
+ if (ret < 0)
+ return ret;
+
+ return i2c_smbus_write_byte_data(chip->client,
+ AD7746_REG_CAPDACB,
+ chip->capdac[channel][1]);
+}
+
+static int ad7746_select_channel(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan)
+{
+ struct ad7746_chip_info *chip = iio_priv(indio_dev);
+ u8 vt_setup, cap_setup;
+ int ret, delay, idx;
+
+ switch (chan->type) {
+ case IIO_CAPACITANCE:
+ cap_setup = FIELD_PREP(AD7746_CAPSETUP_CIN2,
+ ad7746_chan_info[chan->address].cin2) |
+ FIELD_PREP(AD7746_CAPSETUP_CAPDIFF,
+ ad7746_chan_info[chan->address].capdiff) |
+ FIELD_PREP(AD7746_CAPSETUP_CAPEN, 1);
+ vt_setup = chip->vt_setup & ~AD7746_VTSETUP_VTEN;
+ idx = FIELD_GET(AD7746_CONF_CAPFS_MASK, chip->config);
+ delay = ad7746_cap_filter_rate_table[idx][1];
+
+ ret = ad7746_set_capdac(chip, chan->channel);
+ if (ret < 0)
+ return ret;
+
+ chip->capdac_set = chan->channel;
+ break;
+ case IIO_VOLTAGE:
+ case IIO_TEMP:
+ vt_setup = FIELD_PREP(AD7746_VTSETUP_VTMD_MASK,
+ ad7746_chan_info[chan->address].vtmd) |
+ FIELD_PREP(AD7746_VTSETUP_VTEN, 1);
+ cap_setup = chip->cap_setup & ~AD7746_CAPSETUP_CAPEN;
+ idx = FIELD_GET(AD7746_CONF_VTFS_MASK, chip->config);
+ delay = ad7746_cap_filter_rate_table[idx][1];
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (chip->cap_setup != cap_setup) {
+ ret = i2c_smbus_write_byte_data(chip->client,
+ AD7746_REG_CAP_SETUP,
+ cap_setup);
+ if (ret < 0)
+ return ret;
+
+ chip->cap_setup = cap_setup;
+ }
+
+ if (chip->vt_setup != vt_setup) {
+ ret = i2c_smbus_write_byte_data(chip->client,
+ AD7746_REG_VT_SETUP,
+ vt_setup);
+ if (ret < 0)
+ return ret;
+
+ chip->vt_setup = vt_setup;
+ }
+
+ return delay;
+}
+
+static inline ssize_t ad7746_start_calib(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t len,
+ u8 regval)
+{
+ struct iio_dev *indio_dev = dev_to_iio_dev(dev);
+ struct ad7746_chip_info *chip = iio_priv(indio_dev);
+ int ret, timeout = 10;
+ bool doit;
+
+ ret = kstrtobool(buf, &doit);
+ if (ret < 0)
+ return ret;
+
+ if (!doit)
+ return 0;
+
+ mutex_lock(&chip->lock);
+ regval |= chip->config;
+ ret = i2c_smbus_write_byte_data(chip->client, AD7746_REG_CFG, regval);
+ if (ret < 0)
+ goto unlock;
+
+ do {
+ msleep(20);
+ ret = i2c_smbus_read_byte_data(chip->client, AD7746_REG_CFG);
+ if (ret < 0)
+ goto unlock;
+
+ } while ((ret == regval) && timeout--);
+
+ mutex_unlock(&chip->lock);
+
+ return len;
+
+unlock:
+ mutex_unlock(&chip->lock);
+ return ret;
+}
+
+static ssize_t ad7746_start_offset_calib(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t len)
+{
+ struct iio_dev *indio_dev = dev_to_iio_dev(dev);
+ int ret = ad7746_select_channel(indio_dev,
+ &ad7746_channels[to_iio_dev_attr(attr)->address]);
+ if (ret < 0)
+ return ret;
+
+ return ad7746_start_calib(dev, attr, buf, len,
+ FIELD_PREP(AD7746_CONF_MODE_MASK,
+ AD7746_CONF_MODE_OFFS_CAL));
+}
+
+static ssize_t ad7746_start_gain_calib(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t len)
+{
+ struct iio_dev *indio_dev = dev_to_iio_dev(dev);
+ int ret = ad7746_select_channel(indio_dev,
+ &ad7746_channels[to_iio_dev_attr(attr)->address]);
+ if (ret < 0)
+ return ret;
+
+ return ad7746_start_calib(dev, attr, buf, len,
+ FIELD_PREP(AD7746_CONF_MODE_MASK,
+ AD7746_CONF_MODE_GAIN_CAL));
+}
+
+static IIO_DEVICE_ATTR(in_capacitance0_calibbias_calibration,
+ 0200, NULL, ad7746_start_offset_calib, CIN1);
+static IIO_DEVICE_ATTR(in_capacitance1_calibbias_calibration,
+ 0200, NULL, ad7746_start_offset_calib, CIN2);
+static IIO_DEVICE_ATTR(in_capacitance0_calibscale_calibration,
+ 0200, NULL, ad7746_start_gain_calib, CIN1);
+static IIO_DEVICE_ATTR(in_capacitance1_calibscale_calibration,
+ 0200, NULL, ad7746_start_gain_calib, CIN2);
+static IIO_DEVICE_ATTR(in_voltage0_calibscale_calibration,
+ 0200, NULL, ad7746_start_gain_calib, VIN);
+
+static int ad7746_store_cap_filter_rate_setup(struct ad7746_chip_info *chip,
+ int val)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ad7746_cap_filter_rate_table); i++)
+ if (val >= ad7746_cap_filter_rate_table[i][0])
+ break;
+
+ if (i >= ARRAY_SIZE(ad7746_cap_filter_rate_table))
+ i = ARRAY_SIZE(ad7746_cap_filter_rate_table) - 1;
+
+ chip->config &= ~AD7746_CONF_CAPFS_MASK;
+ chip->config |= FIELD_PREP(AD7746_CONF_CAPFS_MASK, i);
+
+ return 0;
+}
+
+static int ad7746_store_vt_filter_rate_setup(struct ad7746_chip_info *chip,
+ int val)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ad7746_vt_filter_rate_table); i++)
+ if (val >= ad7746_vt_filter_rate_table[i][0])
+ break;
+
+ if (i >= ARRAY_SIZE(ad7746_vt_filter_rate_table))
+ i = ARRAY_SIZE(ad7746_vt_filter_rate_table) - 1;
+
+ chip->config &= ~AD7746_CONF_VTFS_MASK;
+ chip->config |= FIELD_PREP(AD7746_CONF_VTFS_MASK, i);
+
+ return 0;
+}
+
+static struct attribute *ad7746_attributes[] = {
+ &iio_dev_attr_in_capacitance0_calibbias_calibration.dev_attr.attr,
+ &iio_dev_attr_in_capacitance0_calibscale_calibration.dev_attr.attr,
+ &iio_dev_attr_in_capacitance1_calibscale_calibration.dev_attr.attr,
+ &iio_dev_attr_in_capacitance1_calibbias_calibration.dev_attr.attr,
+ &iio_dev_attr_in_voltage0_calibscale_calibration.dev_attr.attr,
+ NULL,
+};
+
+static const struct attribute_group ad7746_attribute_group = {
+ .attrs = ad7746_attributes,
+};
+
+static int ad7746_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val,
+ int val2,
+ long mask)
+{
+ struct ad7746_chip_info *chip = iio_priv(indio_dev);
+ int ret, reg;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_CALIBSCALE:
+ if (val != 1)
+ return -EINVAL;
+
+ val = (val2 * 1024) / 15625;
+
+ switch (chan->type) {
+ case IIO_CAPACITANCE:
+ reg = AD7746_REG_CAP_GAINH;
+ break;
+ case IIO_VOLTAGE:
+ reg = AD7746_REG_VOLT_GAINH;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ mutex_lock(&chip->lock);
+ ret = i2c_smbus_write_word_swapped(chip->client, reg, val);
+ mutex_unlock(&chip->lock);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+ case IIO_CHAN_INFO_CALIBBIAS:
+ if (val < 0 || val > 0xFFFF)
+ return -EINVAL;
+
+ mutex_lock(&chip->lock);
+ ret = i2c_smbus_write_word_swapped(chip->client,
+ AD7746_REG_CAP_OFFH, val);
+ mutex_unlock(&chip->lock);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+ case IIO_CHAN_INFO_OFFSET:
+ case IIO_CHAN_INFO_ZEROPOINT:
+ if (val < 0 || val > 43008000) /* 21pF */
+ return -EINVAL;
+
+ /*
+ * CAPDAC Scale = 21pF_typ / 127
+ * CIN Scale = 8.192pF / 2^24
+ * Offset Scale = CAPDAC Scale / CIN Scale = 338646
+ */
+
+ val /= 338646;
+ mutex_lock(&chip->lock);
+ chip->capdac[chan->channel][chan->differential] = val > 0 ?
+ FIELD_PREP(AD7746_CAPDAC_DACP_MASK, val) | AD7746_CAPDAC_DACEN : 0;
+
+ ret = ad7746_set_capdac(chip, chan->channel);
+ if (ret < 0) {
+ mutex_unlock(&chip->lock);
+ return ret;
+ }
+
+ chip->capdac_set = chan->channel;
+ mutex_unlock(&chip->lock);
+
+ return 0;
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ if (val2)
+ return -EINVAL;
+
+ switch (chan->type) {
+ case IIO_CAPACITANCE:
+ mutex_lock(&chip->lock);
+ ret = ad7746_store_cap_filter_rate_setup(chip, val);
+ mutex_unlock(&chip->lock);
+ return ret;
+ case IIO_VOLTAGE:
+ mutex_lock(&chip->lock);
+ ret = ad7746_store_vt_filter_rate_setup(chip, val);
+ mutex_unlock(&chip->lock);
+ return ret;
+ default:
+ return -EINVAL;
+ }
+ default:
+ return -EINVAL;
+ }
+}
+
+static const int ad7746_v_samp_freq[] = { 50, 31, 16, 8, };
+static const int ad7746_cap_samp_freq[] = { 91, 84, 50, 26, 16, 13, 11, 9, };
+
+static int ad7746_read_avail(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan, const int **vals,
+ int *type, int *length, long mask)
+{
+ if (mask != IIO_CHAN_INFO_SAMP_FREQ)
+ return -EINVAL;
+
+ switch (chan->type) {
+ case IIO_VOLTAGE:
+ *vals = ad7746_v_samp_freq;
+ *length = ARRAY_SIZE(ad7746_v_samp_freq);
+ break;
+ case IIO_CAPACITANCE:
+ *vals = ad7746_cap_samp_freq;
+ *length = ARRAY_SIZE(ad7746_cap_samp_freq);
+ break;
+ default:
+ return -EINVAL;
+ }
+ *type = IIO_VAL_INT;
+ return IIO_AVAIL_LIST;
+}
+
+static int ad7746_read_channel(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val)
+{
+ struct ad7746_chip_info *chip = iio_priv(indio_dev);
+ int ret, delay;
+ u8 data[3];
+ u8 regval;
+
+ ret = ad7746_select_channel(indio_dev, chan);
+ if (ret < 0)
+ return ret;
+ delay = ret;
+
+ regval = chip->config | FIELD_PREP(AD7746_CONF_MODE_MASK,
+ AD7746_CONF_MODE_SINGLE_CONV);
+ ret = i2c_smbus_write_byte_data(chip->client, AD7746_REG_CFG, regval);
+ if (ret < 0)
+ return ret;
+
+ msleep(delay);
+ /* Now read the actual register */
+ ret = i2c_smbus_read_i2c_block_data(chip->client,
+ ad7746_chan_info[chan->address].addr,
+ sizeof(data), data);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * Offset applied internally becaue the _offset userspace interface is
+ * needed for the CAP DACs which apply a controllable offset.
+ */
+ *val = get_unaligned_be24(data) - 0x800000;
+
+ return 0;
+}
+
+static int ad7746_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val, int *val2,
+ long mask)
+{
+ struct ad7746_chip_info *chip = iio_priv(indio_dev);
+ int ret, idx;
+ u8 reg;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ mutex_lock(&chip->lock);
+ ret = ad7746_read_channel(indio_dev, chan, val);
+ mutex_unlock(&chip->lock);
+ if (ret < 0)
+ return ret;
+
+ return IIO_VAL_INT;
+ case IIO_CHAN_INFO_CALIBSCALE:
+ switch (chan->type) {
+ case IIO_CAPACITANCE:
+ reg = AD7746_REG_CAP_GAINH;
+ break;
+ case IIO_VOLTAGE:
+ reg = AD7746_REG_VOLT_GAINH;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ mutex_lock(&chip->lock);
+ ret = i2c_smbus_read_word_swapped(chip->client, reg);
+ mutex_unlock(&chip->lock);
+ if (ret < 0)
+ return ret;
+ /* 1 + gain_val / 2^16 */
+ *val = 1;
+ *val2 = (15625 * ret) / 1024;
+
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_CHAN_INFO_CALIBBIAS:
+ mutex_lock(&chip->lock);
+ ret = i2c_smbus_read_word_swapped(chip->client,
+ AD7746_REG_CAP_OFFH);
+ mutex_unlock(&chip->lock);
+ if (ret < 0)
+ return ret;
+ *val = ret;
+
+ return IIO_VAL_INT;
+ case IIO_CHAN_INFO_OFFSET:
+ case IIO_CHAN_INFO_ZEROPOINT:
+ *val = FIELD_GET(AD7746_CAPDAC_DACP_MASK,
+ chip->capdac[chan->channel][chan->differential]) * 338646;
+
+ return IIO_VAL_INT;
+ case IIO_CHAN_INFO_SCALE:
+ switch (chan->type) {
+ case IIO_CAPACITANCE:
+ /* 8.192pf / 2^24 */
+ *val = 0;
+ *val2 = 488;
+ return IIO_VAL_INT_PLUS_NANO;
+ case IIO_VOLTAGE:
+ /* 1170mV / 2^23 */
+ *val = 1170;
+ if (chan->channel == 1)
+ *val *= 6;
+ *val2 = 23;
+ return IIO_VAL_FRACTIONAL_LOG2;
+ case IIO_TEMP:
+ *val = 125;
+ *val2 = 8;
+ return IIO_VAL_FRACTIONAL_LOG2;
+ default:
+ return -EINVAL;
+ }
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ switch (chan->type) {
+ case IIO_CAPACITANCE:
+ idx = FIELD_GET(AD7746_CONF_CAPFS_MASK, chip->config);
+ *val = ad7746_cap_filter_rate_table[idx][0];
+ return IIO_VAL_INT;
+ case IIO_VOLTAGE:
+ idx = FIELD_GET(AD7746_CONF_VTFS_MASK, chip->config);
+ *val = ad7746_vt_filter_rate_table[idx][0];
+ return IIO_VAL_INT;
+ default:
+ return -EINVAL;
+ }
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct iio_info ad7746_info = {
+ .attrs = &ad7746_attribute_group,
+ .read_raw = ad7746_read_raw,
+ .read_avail = ad7746_read_avail,
+ .write_raw = ad7746_write_raw,
+};
+
+static int ad7746_probe(struct i2c_client *client)
+{
+ const struct i2c_device_id *id = i2c_client_get_device_id(client);
+ struct device *dev = &client->dev;
+ struct ad7746_chip_info *chip;
+ struct iio_dev *indio_dev;
+ unsigned char regval = 0;
+ unsigned int vdd_permille;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
+ if (!indio_dev)
+ return -ENOMEM;
+
+ chip = iio_priv(indio_dev);
+ mutex_init(&chip->lock);
+
+ chip->client = client;
+ chip->capdac_set = -1;
+
+ indio_dev->name = id->name;
+ indio_dev->info = &ad7746_info;
+ indio_dev->channels = ad7746_channels;
+ if (id->driver_data == 7746)
+ indio_dev->num_channels = ARRAY_SIZE(ad7746_channels);
+ else
+ indio_dev->num_channels = ARRAY_SIZE(ad7746_channels) - 2;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+
+ if (device_property_read_bool(dev, "adi,exca-output-en")) {
+ if (device_property_read_bool(dev, "adi,exca-output-invert"))
+ regval |= AD7746_EXCSETUP_NEXCA;
+ else
+ regval |= AD7746_EXCSETUP_EXCA;
+ }
+
+ if (device_property_read_bool(dev, "adi,excb-output-en")) {
+ if (device_property_read_bool(dev, "adi,excb-output-invert"))
+ regval |= AD7746_EXCSETUP_NEXCB;
+ else
+ regval |= AD7746_EXCSETUP_EXCB;
+ }
+
+ ret = device_property_read_u32(dev, "adi,excitation-vdd-permille",
+ &vdd_permille);
+ if (!ret) {
+ switch (vdd_permille) {
+ case 125:
+ regval |= FIELD_PREP(AD7746_EXCSETUP_EXCLVL_MASK, 0);
+ break;
+ case 250:
+ regval |= FIELD_PREP(AD7746_EXCSETUP_EXCLVL_MASK, 1);
+ break;
+ case 375:
+ regval |= FIELD_PREP(AD7746_EXCSETUP_EXCLVL_MASK, 2);
+ break;
+ case 500:
+ regval |= FIELD_PREP(AD7746_EXCSETUP_EXCLVL_MASK, 3);
+ break;
+ default:
+ break;
+ }
+ }
+
+ ret = i2c_smbus_write_byte_data(chip->client, AD7746_REG_EXC_SETUP,
+ regval);
+ if (ret < 0)
+ return ret;
+
+ return devm_iio_device_register(indio_dev->dev.parent, indio_dev);
+}
+
+static const struct i2c_device_id ad7746_id[] = {
+ { "ad7745", 7745 },
+ { "ad7746", 7746 },
+ { "ad7747", 7747 },
+ {}
+};
+MODULE_DEVICE_TABLE(i2c, ad7746_id);
+
+static const struct of_device_id ad7746_of_match[] = {
+ { .compatible = "adi,ad7745" },
+ { .compatible = "adi,ad7746" },
+ { .compatible = "adi,ad7747" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, ad7746_of_match);
+
+static struct i2c_driver ad7746_driver = {
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = ad7746_of_match,
+ },
+ .probe = ad7746_probe,
+ .id_table = ad7746_id,
+};
+module_i2c_driver(ad7746_driver);
+
+MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
+MODULE_DESCRIPTION("Analog Devices AD7746/5/7 capacitive sensor driver");
+MODULE_LICENSE("GPL v2");