diff options
Diffstat (limited to '')
30 files changed, 1348 insertions, 38 deletions
diff --git a/drivers/interconnect/imx/imx.h b/drivers/interconnect/imx/imx.h index 895907cdcb..d4d0e98886 100644 --- a/drivers/interconnect/imx/imx.h +++ b/drivers/interconnect/imx/imx.h @@ -10,8 +10,13 @@ #ifndef __DRIVERS_INTERCONNECT_IMX_H #define __DRIVERS_INTERCONNECT_IMX_H +#include <linux/args.h> +#include <linux/bits.h> +#include <linux/types.h> + #include <linux/interconnect-provider.h> -#include <linux/kernel.h> + +struct platform_device; #define IMX_ICC_MAX_LINKS 4 @@ -89,7 +94,7 @@ struct imx_icc_noc_setting { .id = _id, \ .name = _name, \ .adj = _adj, \ - .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ + .num_links = COUNT_ARGS(__VA_ARGS__), \ .links = { __VA_ARGS__ }, \ } diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig index 825b647d91..62b516d38d 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -182,6 +182,15 @@ config INTERCONNECT_QCOM_SDX65 This is a driver for the Qualcomm Network-on-Chip on sdx65-based platforms. +config INTERCONNECT_QCOM_SDX75 + tristate "Qualcomm SDX75 interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on sdx75-based + platforms. + config INTERCONNECT_QCOM_SM6350 tristate "Qualcomm SM6350 interconnect driver" depends on INTERCONNECT_QCOM_RPMH_POSSIBLE diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index 80d9d2da95..c5320e2939 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -23,6 +23,7 @@ qnoc-sdm670-objs := sdm670.o qnoc-sdm845-objs := sdm845.o qnoc-sdx55-objs := sdx55.o qnoc-sdx65-objs := sdx65.o +qnoc-sdx75-objs := sdx75.o qnoc-sm6350-objs := sm6350.o qnoc-sm8150-objs := sm8150.o qnoc-sm8250-objs := sm8250.o @@ -51,6 +52,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDM670) += qnoc-sdm670.o obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) += qnoc-sdx65.o +obj-$(CONFIG_INTERCONNECT_QCOM_SDX75) += qnoc-sdx75.o obj-$(CONFIG_INTERCONNECT_QCOM_SM6350) += qnoc-sm6350.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o diff --git a/drivers/interconnect/qcom/icc-rpm-clocks.c b/drivers/interconnect/qcom/icc-rpm-clocks.c index 63c82a91bb..ac1677de7d 100644 --- a/drivers/interconnect/qcom/icc-rpm-clocks.c +++ b/drivers/interconnect/qcom/icc-rpm-clocks.c @@ -25,6 +25,12 @@ const struct rpm_clk_resource bimc_clk = { }; EXPORT_SYMBOL_GPL(bimc_clk); +const struct rpm_clk_resource mem_1_clk = { + .resource_type = QCOM_SMD_RPM_MEM_CLK, + .clock_id = 1, +}; +EXPORT_SYMBOL_GPL(mem_1_clk); + const struct rpm_clk_resource bus_0_clk = { .resource_type = QCOM_SMD_RPM_BUS_CLK, .clock_id = 0, diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index e76356f911..dbacb2a7af 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -291,6 +291,32 @@ static int qcom_icc_bw_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, return 0; } +static u64 qcom_icc_calc_rate(struct qcom_icc_provider *qp, struct qcom_icc_node *qn, int ctx) +{ + u64 agg_avg_rate, agg_peak_rate, agg_rate; + + if (qn->channels) + agg_avg_rate = div_u64(qn->sum_avg[ctx], qn->channels); + else + agg_avg_rate = qn->sum_avg[ctx]; + + if (qn->ab_coeff) { + agg_avg_rate = agg_avg_rate * qn->ab_coeff; + agg_avg_rate = div_u64(agg_avg_rate, 100); + } + + if (qn->ib_coeff) { + agg_peak_rate = qn->max_peak[ctx] * 100; + agg_peak_rate = div_u64(agg_peak_rate, qn->ib_coeff); + } else { + agg_peak_rate = qn->max_peak[ctx]; + } + + agg_rate = max_t(u64, agg_avg_rate, agg_peak_rate); + + return div_u64(agg_rate, qn->buswidth); +} + /** * qcom_icc_bus_aggregate - calculate bus clock rates by traversing all nodes * @provider: generic interconnect provider @@ -298,10 +324,10 @@ static int qcom_icc_bw_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, */ static void qcom_icc_bus_aggregate(struct icc_provider *provider, u64 *agg_clk_rate) { - u64 agg_avg_rate, agg_rate; + struct qcom_icc_provider *qp = to_qcom_provider(provider); struct qcom_icc_node *qn; struct icc_node *node; - int i; + int ctx; /* * Iterate nodes on the provider, aggregate bandwidth requests for @@ -309,16 +335,9 @@ static void qcom_icc_bus_aggregate(struct icc_provider *provider, u64 *agg_clk_r */ list_for_each_entry(node, &provider->nodes, node_list) { qn = node->data; - for (i = 0; i < QCOM_SMD_RPM_STATE_NUM; i++) { - if (qn->channels) - agg_avg_rate = div_u64(qn->sum_avg[i], qn->channels); - else - agg_avg_rate = qn->sum_avg[i]; - - agg_rate = max_t(u64, agg_avg_rate, qn->max_peak[i]); - do_div(agg_rate, qn->buswidth); - - agg_clk_rate[i] = max_t(u64, agg_clk_rate[i], agg_rate); + for (ctx = 0; ctx < QCOM_SMD_RPM_STATE_NUM; ctx++) { + agg_clk_rate[ctx] = max_t(u64, agg_clk_rate[ctx], + qcom_icc_calc_rate(qp, qn, ctx)); } } } @@ -395,6 +414,33 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) qp->bus_clk_rate[QCOM_SMD_RPM_SLEEP_STATE] = sleep_rate; } + /* Handle the node-specific clock */ + if (!src_qn->bus_clk_desc) + return 0; + + active_rate = qcom_icc_calc_rate(qp, src_qn, QCOM_SMD_RPM_ACTIVE_STATE); + sleep_rate = qcom_icc_calc_rate(qp, src_qn, QCOM_SMD_RPM_SLEEP_STATE); + + if (active_rate != src_qn->bus_clk_rate[QCOM_SMD_RPM_ACTIVE_STATE]) { + ret = qcom_icc_rpm_set_bus_rate(src_qn->bus_clk_desc, QCOM_SMD_RPM_ACTIVE_STATE, + active_rate); + if (ret) + return ret; + + /* Cache the rate after we've successfully committed it to RPM */ + src_qn->bus_clk_rate[QCOM_SMD_RPM_ACTIVE_STATE] = active_rate; + } + + if (sleep_rate != src_qn->bus_clk_rate[QCOM_SMD_RPM_SLEEP_STATE]) { + ret = qcom_icc_rpm_set_bus_rate(src_qn->bus_clk_desc, QCOM_SMD_RPM_SLEEP_STATE, + sleep_rate); + if (ret) + return ret; + + /* Cache the rate after we've successfully committed it to RPM */ + src_qn->bus_clk_rate[QCOM_SMD_RPM_SLEEP_STATE] = sleep_rate; + } + return 0; } @@ -517,6 +563,12 @@ regmap_done: for (i = 0; i < num_nodes; i++) { size_t j; + if (!qnodes[i]->ab_coeff) + qnodes[i]->ab_coeff = qp->ab_coeff; + + if (!qnodes[i]->ib_coeff) + qnodes[i]->ib_coeff = qp->ib_coeff; + node = icc_node_create(qnodes[i]->id); if (IS_ERR(node)) { clk_bulk_disable_unprepare(qp->num_intf_clks, diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index eed3451af3..a13768cfd2 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -44,6 +44,8 @@ struct rpm_clk_resource { * @type: the ICC provider type * @regmap: regmap for QoS registers read/write access * @qos_offset: offset to QoS registers + * @ab_coeff: a percentage-based coefficient for compensating the AB calculations + * @ib_coeff: an inverse-percentage-based coefficient for compensating the IB calculations * @bus_clk_rate: bus clock rate in Hz * @bus_clk_desc: a pointer to a rpm_clk_resource description of bus clocks * @bus_clk: a pointer to a HLOS-owned bus clock @@ -57,6 +59,8 @@ struct qcom_icc_provider { enum qcom_icc_type type; struct regmap *regmap; unsigned int qos_offset; + u16 ab_coeff; + u16 ib_coeff; u32 bus_clk_rate[QCOM_SMD_RPM_STATE_NUM]; const struct rpm_clk_resource *bus_clk_desc; struct clk *bus_clk; @@ -93,11 +97,15 @@ struct qcom_icc_qos { * @num_links: the total number of @links * @channels: number of channels at this node (e.g. DDR channels) * @buswidth: width of the interconnect between a node and the bus (bytes) + * @bus_clk_desc: a pointer to a rpm_clk_resource description of bus clocks * @sum_avg: current sum aggregate value of all avg bw requests * @max_peak: current max aggregate value of all peak bw requests * @mas_rpm_id: RPM id for devices that are bus masters * @slv_rpm_id: RPM id for devices that are bus slaves * @qos: NoC QoS setting parameters + * @ab_coeff: a percentage-based coefficient for compensating the AB calculations + * @ib_coeff: an inverse-percentage-based coefficient for compensating the IB calculations + * @bus_clk_rate: a pointer to an array containing bus clock rates in Hz */ struct qcom_icc_node { unsigned char *name; @@ -106,11 +114,15 @@ struct qcom_icc_node { u16 num_links; u16 channels; u16 buswidth; + const struct rpm_clk_resource *bus_clk_desc; u64 sum_avg[QCOM_SMD_RPM_STATE_NUM]; u64 max_peak[QCOM_SMD_RPM_STATE_NUM]; int mas_rpm_id; int slv_rpm_id; struct qcom_icc_qos qos; + u16 ab_coeff; + u16 ib_coeff; + u32 bus_clk_rate[QCOM_SMD_RPM_STATE_NUM]; }; struct qcom_icc_desc { @@ -123,6 +135,8 @@ struct qcom_icc_desc { enum qcom_icc_type type; const struct regmap_config *regmap_cfg; unsigned int qos_offset; + u16 ab_coeff; + u16 ib_coeff; }; /* Valid for all bus types */ @@ -138,6 +152,7 @@ extern const struct rpm_clk_resource bimc_clk; extern const struct rpm_clk_resource bus_0_clk; extern const struct rpm_clk_resource bus_1_clk; extern const struct rpm_clk_resource bus_2_clk; +extern const struct rpm_clk_resource mem_1_clk; extern const struct rpm_clk_resource mmaxi_0_clk; extern const struct rpm_clk_resource mmaxi_1_clk; extern const struct rpm_clk_resource qup_clk; diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c index b9f27ce3b6..c1aa265c1f 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -253,14 +253,12 @@ err_remove_nodes: } EXPORT_SYMBOL_GPL(qcom_icc_rpmh_probe); -int qcom_icc_rpmh_remove(struct platform_device *pdev) +void qcom_icc_rpmh_remove(struct platform_device *pdev) { struct qcom_icc_provider *qp = platform_get_drvdata(pdev); icc_provider_deregister(&qp->provider); icc_nodes_remove(&qp->provider); - - return 0; } EXPORT_SYMBOL_GPL(qcom_icc_rpmh_remove); diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h index 5f0af8b1fc..2de29460e8 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -126,6 +126,6 @@ int qcom_icc_set(struct icc_node *src, struct icc_node *dst); int qcom_icc_bcm_init(struct qcom_icc_bcm *bcm, struct device *dev); void qcom_icc_pre_aggregate(struct icc_node *node); int qcom_icc_rpmh_probe(struct platform_device *pdev); -int qcom_icc_rpmh_remove(struct platform_device *pdev); +void qcom_icc_rpmh_remove(struct platform_device *pdev); #endif diff --git a/drivers/interconnect/qcom/msm8974.c b/drivers/interconnect/qcom/msm8974.c index 885ca9d6d4..21f6c85214 100644 --- a/drivers/interconnect/qcom/msm8974.c +++ b/drivers/interconnect/qcom/msm8974.c @@ -28,6 +28,8 @@ */ #include <dt-bindings/interconnect/qcom,msm8974.h> + +#include <linux/args.h> #include <linux/clk.h> #include <linux/device.h> #include <linux/interconnect-provider.h> @@ -231,7 +233,7 @@ struct msm8974_icc_desc { .buswidth = _buswidth, \ .mas_rpm_id = _mas_rpm_id, \ .slv_rpm_id = _slv_rpm_id, \ - .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ + .num_links = COUNT_ARGS(__VA_ARGS__), \ .links = { __VA_ARGS__ }, \ } diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c index 88683dfa46..b73566c9b2 100644 --- a/drivers/interconnect/qcom/msm8996.c +++ b/drivers/interconnect/qcom/msm8996.c @@ -448,6 +448,7 @@ static struct qcom_icc_node mas_mdp_p0 = { .name = "mas_mdp_p0", .id = MSM8996_MASTER_MDP_PORT0, .buswidth = 32, + .ib_coeff = 25, .mas_rpm_id = 8, .slv_rpm_id = -1, .qos.ap_owned = true, @@ -463,6 +464,7 @@ static struct qcom_icc_node mas_mdp_p1 = { .name = "mas_mdp_p1", .id = MSM8996_MASTER_MDP_PORT1, .buswidth = 32, + .ib_coeff = 25, .mas_rpm_id = 61, .slv_rpm_id = -1, .qos.ap_owned = true, @@ -1889,7 +1891,8 @@ static const struct qcom_icc_desc msm8996_bimc = { .nodes = bimc_nodes, .num_nodes = ARRAY_SIZE(bimc_nodes), .bus_clk_desc = &bimc_clk, - .regmap_cfg = &msm8996_bimc_regmap_config + .regmap_cfg = &msm8996_bimc_regmap_config, + .ab_coeff = 154, }; static struct qcom_icc_node * const cnoc_nodes[] = { @@ -2004,7 +2007,8 @@ static const struct qcom_icc_desc msm8996_mnoc = { .bus_clk_desc = &mmaxi_0_clk, .intf_clocks = mm_intf_clocks, .num_intf_clocks = ARRAY_SIZE(mm_intf_clocks), - .regmap_cfg = &msm8996_mnoc_regmap_config + .regmap_cfg = &msm8996_mnoc_regmap_config, + .ab_coeff = 154, }; static struct qcom_icc_node * const pnoc_nodes[] = { diff --git a/drivers/interconnect/qcom/qcm2290.c b/drivers/interconnect/qcom/qcm2290.c index 5bc4b75166..b88cf9a022 100644 --- a/drivers/interconnect/qcom/qcm2290.c +++ b/drivers/interconnect/qcom/qcm2290.c @@ -112,6 +112,9 @@ static struct qcom_icc_node mas_appss_proc = { .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.prio_level = 0, .qos.areq_prio = 0, + .bus_clk_desc = &mem_1_clk, + .ab_coeff = 159, + .ib_coeff = 96, .mas_rpm_id = 0, .slv_rpm_id = -1, .num_links = ARRAY_SIZE(mas_appss_proc_links), @@ -675,7 +678,8 @@ static struct qcom_icc_node mas_gfx3d = { static struct qcom_icc_node slv_ebi1 = { .name = "slv_ebi1", .id = QCM2290_SLAVE_EBI1, - .buswidth = 8, + .buswidth = 4, + .channels = 2, .mas_rpm_id = -1, .slv_rpm_id = 0, }; @@ -1199,6 +1203,7 @@ static const struct qcom_icc_desc qcm2290_bimc = { .keep_alive = true, /* M_REG_BASE() in vendor msm_bus_bimc_adhoc driver */ .qos_offset = 0x8000, + .ab_coeff = 153, }; static struct qcom_icc_node * const qcm2290_cnoc_nodes[] = { @@ -1329,6 +1334,7 @@ static const struct qcom_icc_desc qcm2290_mmnrt_virt = { .regmap_cfg = &qcm2290_snoc_regmap_config, .keep_alive = true, .qos_offset = 0x15000, + .ab_coeff = 142, }; static struct qcom_icc_node * const qcm2290_mmrt_virt_nodes[] = { @@ -1345,6 +1351,7 @@ static const struct qcom_icc_desc qcm2290_mmrt_virt = { .regmap_cfg = &qcm2290_snoc_regmap_config, .keep_alive = true, .qos_offset = 0x15000, + .ab_coeff = 139, }; static const struct of_device_id qcm2290_noc_of_match[] = { diff --git a/drivers/interconnect/qcom/qdu1000.c b/drivers/interconnect/qcom/qdu1000.c index a7392eb73d..9cb477d2bd 100644 --- a/drivers/interconnect/qcom/qdu1000.c +++ b/drivers/interconnect/qcom/qdu1000.c @@ -1046,7 +1046,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qnoc_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-qdu1000", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qcom/sa8775p.c index ef1b5e3260..dd6281db08 100644 --- a/drivers/interconnect/qcom/sa8775p.c +++ b/drivers/interconnect/qcom/sa8775p.c @@ -2519,7 +2519,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sa8775p", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom/sc7180.c index af2be15438..34a1d163d6 100644 --- a/drivers/interconnect/qcom/sc7180.c +++ b/drivers/interconnect/qcom/sc7180.c @@ -1807,7 +1807,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sc7180", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c index a626dbc719..7d33694368 100644 --- a/drivers/interconnect/qcom/sc7280.c +++ b/drivers/interconnect/qcom/sc7280.c @@ -1835,7 +1835,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sc7280", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c index bdd3471d4a..03d626776b 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -1372,6 +1372,7 @@ static struct qcom_icc_bcm bcm_mm0 = { static struct qcom_icc_bcm bcm_co0 = { .name = "CO0", + .keepalive = true, .num_nodes = 1, .nodes = { &slv_qns_cdsp_mem_noc } }; @@ -1888,7 +1889,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sc8180x", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sc8280xp.c b/drivers/interconnect/qcom/sc8280xp.c index 0270f6c644..7acd152bf0 100644 --- a/drivers/interconnect/qcom/sc8280xp.c +++ b/drivers/interconnect/qcom/sc8280xp.c @@ -2391,7 +2391,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sc8280xp", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c index 36962f7bd7..7392bebba3 100644 --- a/drivers/interconnect/qcom/sdm660.c +++ b/drivers/interconnect/qcom/sdm660.c @@ -602,6 +602,7 @@ static struct qcom_icc_node mas_mdp_p0 = { .name = "mas_mdp_p0", .id = SDM660_MASTER_MDP_P0, .buswidth = 16, + .ib_coeff = 50, .mas_rpm_id = 8, .slv_rpm_id = -1, .qos.ap_owned = true, @@ -621,6 +622,7 @@ static struct qcom_icc_node mas_mdp_p1 = { .name = "mas_mdp_p1", .id = SDM660_MASTER_MDP_P1, .buswidth = 16, + .ib_coeff = 50, .mas_rpm_id = 61, .slv_rpm_id = -1, .qos.ap_owned = true, @@ -1540,6 +1542,7 @@ static const struct qcom_icc_desc sdm660_bimc = { .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes), .bus_clk_desc = &bimc_clk, .regmap_cfg = &sdm660_bimc_regmap_config, + .ab_coeff = 153, }; static struct qcom_icc_node * const sdm660_cnoc_nodes[] = { @@ -1659,6 +1662,7 @@ static const struct qcom_icc_desc sdm660_mnoc = { .intf_clocks = mm_intf_clocks, .num_intf_clocks = ARRAY_SIZE(mm_intf_clocks), .regmap_cfg = &sdm660_mnoc_regmap_config, + .ab_coeff = 153, }; static struct qcom_icc_node * const sdm660_snoc_nodes[] = { diff --git a/drivers/interconnect/qcom/sdm670.c b/drivers/interconnect/qcom/sdm670.c index 907e1ff4ff..e5ee7fbaa6 100644 --- a/drivers/interconnect/qcom/sdm670.c +++ b/drivers/interconnect/qcom/sdm670.c @@ -1533,7 +1533,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sdm670", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c index 855802be93..584800ac87 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -1802,7 +1802,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sdm845", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sdx55.c b/drivers/interconnect/qcom/sdx55.c index 4117db046f..e97f28b8d2 100644 --- a/drivers/interconnect/qcom/sdx55.c +++ b/drivers/interconnect/qcom/sdx55.c @@ -913,7 +913,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sdx55", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sdx65.c b/drivers/interconnect/qcom/sdx65.c index d3a6c6c148..2f3f5479d8 100644 --- a/drivers/interconnect/qcom/sdx65.c +++ b/drivers/interconnect/qcom/sdx65.c @@ -897,7 +897,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sdx65", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sdx75.c b/drivers/interconnect/qcom/sdx75.c new file mode 100644 index 0000000000..7f422c2748 --- /dev/null +++ b/drivers/interconnect/qcom/sdx75.c @@ -0,0 +1,1107 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * + */ + +#include <linux/device.h> +#include <linux/interconnect.h> +#include <linux/interconnect-provider.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <dt-bindings/interconnect/qcom,sdx75.h> + +#include "bcm-voter.h" +#include "icc-common.h" +#include "icc-rpmh.h" +#include "sdx75.h" + +static struct qcom_icc_node qpic_core_master = { + .name = "qpic_core_master", + .id = SDX75_MASTER_QPIC_CORE, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_QPIC_CORE }, +}; + +static struct qcom_icc_node qup0_core_master = { + .name = "qup0_core_master", + .id = SDX75_MASTER_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qnm_cnoc = { + .name = "qnm_cnoc", + .id = SDX75_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 4, + .links = { SDX75_SLAVE_LAGG_CFG, SDX75_SLAVE_MCCC_MASTER, + SDX75_SLAVE_GEM_NOC_CFG, SDX75_SLAVE_SNOOP_BWMON }, +}; + +static struct qcom_icc_node alm_sys_tcu = { + .name = "alm_sys_tcu", + .id = SDX75_MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC }, +}; + +static struct qcom_icc_node chm_apps = { + .name = "chm_apps", + .id = SDX75_MASTER_APPSS_PROC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC, + SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qnm_gemnoc_cfg = { + .name = "qnm_gemnoc_cfg", + .id = SDX75_MASTER_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_SERVICE_GEM_NOC }, +}; + +static struct qcom_icc_node qnm_mdsp = { + .name = "qnm_mdsp", + .id = SDX75_MASTER_MSS_PROC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC, + SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qnm_pcie = { + .name = "qnm_pcie", + .id = SDX75_MASTER_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 2, + .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = SDX75_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC, + SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .id = SDX75_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_LLCC }, +}; + +static struct qcom_icc_node xm_ipa2pcie = { + .name = "xm_ipa2pcie", + .id = SDX75_MASTER_IPA_PCIE, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SDX75_MASTER_LLCC, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node xm_pcie3_0 = { + .name = "xm_pcie3_0", + .id = SDX75_MASTER_PCIE_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 = { + .name = "xm_pcie3_1", + .id = SDX75_MASTER_PCIE_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_2 = { + .name = "xm_pcie3_2", + .id = SDX75_MASTER_PCIE_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node qhm_audio = { + .name = "qhm_audio", + .id = SDX75_MASTER_AUDIO, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qhm_gic = { + .name = "qhm_gic", + .id = SDX75_MASTER_GIC_AHB, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qhm_pcie_rscc = { + .name = "qhm_pcie_rscc", + .id = SDX75_MASTER_PCIE_RSCC, + .channels = 1, + .buswidth = 4, + .num_links = 31, + .links = { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG, + SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL, + SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG, + SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG, + SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG, + SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG, + SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PDM, + SDX75_SLAVE_PRNG, SDX75_SLAVE_QDSS_CFG, + SDX75_SLAVE_QPIC, SDX75_SLAVE_QUP_0, + SDX75_SLAVE_SDCC_1, SDX75_SLAVE_SDCC_4, + SDX75_SLAVE_SPMI_VGI_COEX, SDX75_SLAVE_TCSR, + SDX75_SLAVE_TLMM, SDX75_SLAVE_USB3, + SDX75_SLAVE_USB3_PHY_CFG, SDX75_SLAVE_DDRSS_CFG, + SDX75_SLAVE_SNOC_CFG, SDX75_SLAVE_PCIE_ANOC_CFG, + SDX75_SLAVE_IMEM, SDX75_SLAVE_QDSS_STM, + SDX75_SLAVE_TCU }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SDX75_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhm_qpic = { + .name = "qhm_qpic", + .id = SDX75_MASTER_QPIC, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhm_qup0 = { + .name = "qhm_qup0", + .id = SDX75_MASTER_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node qnm_aggre_noc = { + .name = "qnm_aggre_noc", + .id = SDX75_MASTER_ANOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc = { + .name = "qnm_gemnoc_cnoc", + .id = SDX75_MASTER_GEM_NOC_CNOC, + .channels = 1, + .buswidth = 8, + .num_links = 32, + .links = { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG, + SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL, + SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG, + SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG, + SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG, + SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG, + SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PCIE_RSC_CFG, + SDX75_SLAVE_PDM, SDX75_SLAVE_PRNG, + SDX75_SLAVE_QDSS_CFG, SDX75_SLAVE_QPIC, + SDX75_SLAVE_QUP_0, SDX75_SLAVE_SDCC_1, + SDX75_SLAVE_SDCC_4, SDX75_SLAVE_SPMI_VGI_COEX, + SDX75_SLAVE_TCSR, SDX75_SLAVE_TLMM, + SDX75_SLAVE_USB3, SDX75_SLAVE_USB3_PHY_CFG, + SDX75_SLAVE_DDRSS_CFG, SDX75_SLAVE_SNOC_CFG, + SDX75_SLAVE_PCIE_ANOC_CFG, SDX75_SLAVE_IMEM, + SDX75_SLAVE_QDSS_STM, SDX75_SLAVE_TCU }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie = { + .name = "qnm_gemnoc_pcie", + .id = SDX75_MASTER_GEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SDX75_SLAVE_PCIE_0, SDX75_SLAVE_PCIE_1, + SDX75_SLAVE_PCIE_2 }, +}; + +static struct qcom_icc_node qnm_system_noc_cfg = { + .name = "qnm_system_noc_cfg", + .id = SDX75_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_system_noc_pcie_cfg = { + .name = "qnm_system_noc_pcie_cfg", + .id = SDX75_MASTER_PCIE_ANOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_SERVICE_PCIE_ANOC }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SDX75_MASTER_CRYPTO, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = SDX75_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qxm_mvmss = { + .name = "qxm_mvmss", + .id = SDX75_MASTER_MVMSS, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node xm_emac_0 = { + .name = "xm_emac_0", + .id = SDX75_MASTER_EMAC_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node xm_emac_1 = { + .name = "xm_emac_1", + .id = SDX75_MASTER_EMAC_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node xm_qdss_etr0 = { + .name = "xm_qdss_etr0", + .id = SDX75_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node xm_qdss_etr1 = { + .name = "xm_qdss_etr1", + .id = SDX75_MASTER_QDSS_ETR_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node xm_sdc1 = { + .name = "xm_sdc1", + .id = SDX75_MASTER_SDCC_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node xm_sdc4 = { + .name = "xm_sdc4", + .id = SDX75_MASTER_SDCC_4, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node xm_usb3 = { + .name = "xm_usb3", + .id = SDX75_MASTER_USB3_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node qpic_core_slave = { + .name = "qpic_core_slave", + .id = SDX75_SLAVE_QPIC_CORE, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qup0_core_slave = { + .name = "qup0_core_slave", + .id = SDX75_SLAVE_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_lagg = { + .name = "qhs_lagg", + .id = SDX75_SLAVE_LAGG_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_mccc_master = { + .name = "qhs_mccc_master", + .id = SDX75_SLAVE_MCCC_MASTER, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_gemnoc = { + .name = "qns_gemnoc", + .id = SDX75_SLAVE_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qss_snoop_bwmon = { + .name = "qss_snoop_bwmon", + .id = SDX75_SLAVE_SNOOP_BWMON, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_gemnoc_cnoc = { + .name = "qns_gemnoc_cnoc", + .id = SDX75_SLAVE_GEM_NOC_CNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_MASTER_GEM_NOC_CNOC }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SDX75_SLAVE_LLCC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDX75_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_pcie = { + .name = "qns_pcie", + .id = SDX75_SLAVE_MEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDX75_MASTER_GEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node srvc_gemnoc = { + .name = "srvc_gemnoc", + .id = SDX75_SLAVE_SERVICE_GEM_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SDX75_SLAVE_EBI1, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_pcie_gemnoc = { + .name = "qns_pcie_gemnoc", + .id = SDX75_SLAVE_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDX75_MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node ps_eth0_cfg = { + .name = "ps_eth0_cfg", + .id = SDX75_SLAVE_ETH0_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node ps_eth1_cfg = { + .name = "ps_eth1_cfg", + .id = SDX75_SLAVE_ETH1_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_audio = { + .name = "qhs_audio", + .id = SDX75_SLAVE_AUDIO, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SDX75_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_crypto_cfg = { + .name = "qhs_crypto_cfg", + .id = SDX75_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SDX75_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SDX75_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ipc_router = { + .name = "qhs_ipc_router", + .id = SDX75_SLAVE_IPC_ROUTER_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_mss_cfg = { + .name = "qhs_mss_cfg", + .id = SDX75_SLAVE_CNOC_MSS, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_mvmss_cfg = { + .name = "qhs_mvmss_cfg", + .id = SDX75_SLAVE_ICBDI_MVMSS_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pcie0_cfg = { + .name = "qhs_pcie0_cfg", + .id = SDX75_SLAVE_PCIE_0_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pcie1_cfg = { + .name = "qhs_pcie1_cfg", + .id = SDX75_SLAVE_PCIE_1_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pcie2_cfg = { + .name = "qhs_pcie2_cfg", + .id = SDX75_SLAVE_PCIE_2_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pcie_rscc = { + .name = "qhs_pcie_rscc", + .id = SDX75_SLAVE_PCIE_RSC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SDX75_SLAVE_PDM, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = SDX75_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SDX75_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qpic = { + .name = "qhs_qpic", + .id = SDX75_SLAVE_QPIC, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .id = SDX75_SLAVE_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_sdc1 = { + .name = "qhs_sdc1", + .id = SDX75_SLAVE_SDCC_1, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_sdc4 = { + .name = "qhs_sdc4", + .id = SDX75_SLAVE_SDCC_4, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_spmi_vgi_coex = { + .name = "qhs_spmi_vgi_coex", + .id = SDX75_SLAVE_SPMI_VGI_COEX, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SDX75_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .id = SDX75_SLAVE_TLMM, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_usb3 = { + .name = "qhs_usb3", + .id = SDX75_SLAVE_USB3, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_usb3_phy = { + .name = "qhs_usb3_phy", + .id = SDX75_SLAVE_USB3_PHY_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_a1noc = { + .name = "qns_a1noc", + .id = SDX75_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_MASTER_ANOC_SNOC }, +}; + +static struct qcom_icc_node qns_ddrss_cfg = { + .name = "qns_ddrss_cfg", + .id = SDX75_SLAVE_DDRSS_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .id = SDX75_SLAVE_SNOC_GEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDX75_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_system_noc_cfg = { + .name = "qns_system_noc_cfg", + .id = SDX75_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qns_system_noc_pcie_cfg = { + .name = "qns_system_noc_pcie_cfg", + .id = SDX75_SLAVE_PCIE_ANOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_MASTER_PCIE_ANOC_CFG }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SDX75_SLAVE_IMEM, + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node srvc_pcie_system_noc = { + .name = "srvc_pcie_system_noc", + .id = SDX75_SLAVE_SERVICE_PCIE_ANOC, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node srvc_system_noc = { + .name = "srvc_system_noc", + .id = SDX75_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node xs_pcie_0 = { + .name = "xs_pcie_0", + .id = SDX75_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node xs_pcie_1 = { + .name = "xs_pcie_1", + .id = SDX75_SLAVE_PCIE_1, + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node xs_pcie_2 = { + .name = "xs_pcie_2", + .id = SDX75_SLAVE_PCIE_2, + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SDX75_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SDX75_SLAVE_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .num_nodes = 39, + .nodes = { &qhm_pcie_rscc, &qnm_gemnoc_cnoc, + &ps_eth0_cfg, &ps_eth1_cfg, + &qhs_audio, &qhs_clk_ctl, + &qhs_crypto_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_mss_cfg, &qhs_mvmss_cfg, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pcie2_cfg, &qhs_pcie_rscc, + &qhs_pdm, &qhs_prng, + &qhs_qdss_cfg, &qhs_qpic, + &qhs_qup0, &qhs_sdc1, + &qhs_sdc4, &qhs_spmi_vgi_coex, + &qhs_tcsr, &qhs_tlmm, + &qhs_usb3, &qhs_usb3_phy, + &qns_ddrss_cfg, &qns_system_noc_cfg, + &qns_system_noc_pcie_cfg, &qxs_imem, + &srvc_pcie_system_noc, &srvc_system_noc, + &xs_pcie_0, &xs_pcie_1, + &xs_pcie_2, &xs_qdss_stm, + &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_qp0 = { + .name = "QP0", + .num_nodes = 1, + .nodes = { &qpic_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 = { + .name = "SH1", + .num_nodes = 10, + .nodes = { &alm_sys_tcu, &chm_apps, + &qnm_gemnoc_cfg, &qnm_mdsp, + &qnm_snoc_sf, &xm_gic, + &xm_ipa2pcie, &qns_gemnoc_cnoc, + &qns_pcie, &srvc_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .num_nodes = 21, + .nodes = { &xm_pcie3_0, &xm_pcie3_1, + &xm_pcie3_2, &qhm_audio, + &qhm_gic, &qhm_qdss_bam, + &qhm_qpic, &qhm_qup0, + &qnm_gemnoc_pcie, &qnm_system_noc_cfg, + &qnm_system_noc_pcie_cfg, &qxm_crypto, + &qxm_ipa, &qxm_mvmss, + &xm_emac_0, &xm_emac_1, + &xm_qdss_etr0, &xm_qdss_etr1, + &xm_sdc1, &xm_sdc4, + &xm_usb3 }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .num_nodes = 2, + .nodes = { &qnm_aggre_noc, &qns_a1noc }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .num_nodes = 2, + .nodes = { &qnm_pcie, &qns_pcie_gemnoc }, +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] = { + &bcm_qp0, + &bcm_qup0, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] = { + [MASTER_QPIC_CORE] = &qpic_core_master, + [MASTER_QUP_CORE_0] = &qup0_core_master, + [SLAVE_QPIC_CORE] = &qpic_core_slave, + [SLAVE_QUP_CORE_0] = &qup0_core_slave, +}; + +static const struct qcom_icc_desc sdx75_clk_virt = { + .nodes = clk_virt_nodes, + .num_nodes = ARRAY_SIZE(clk_virt_nodes), + .bcms = clk_virt_bcms, + .num_bcms = ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_node * const dc_noc_nodes[] = { + [MASTER_CNOC_DC_NOC] = &qnm_cnoc, + [SLAVE_LAGG_CFG] = &qhs_lagg, + [SLAVE_MCCC_MASTER] = &qhs_mccc_master, + [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, + [SLAVE_SNOOP_BWMON] = &qss_snoop_bwmon, +}; + +static const struct qcom_icc_desc sdx75_dc_noc = { + .nodes = dc_noc_nodes, + .num_nodes = ARRAY_SIZE(dc_noc_nodes), +}; + +static struct qcom_icc_bcm * const gem_noc_bcms[] = { + &bcm_sh0, + &bcm_sh1, + &bcm_sn4, +}; + +static struct qcom_icc_node * const gem_noc_nodes[] = { + [MASTER_SYS_TCU] = &alm_sys_tcu, + [MASTER_APPSS_PROC] = &chm_apps, + [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, + [MASTER_MSS_PROC] = &qnm_mdsp, + [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, + [MASTER_GIC] = &xm_gic, + [MASTER_IPA_PCIE] = &xm_ipa2pcie, + [SLAVE_GEM_NOC_CNOC] = &qns_gemnoc_cnoc, + [SLAVE_LLCC] = &qns_llcc, + [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, + [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, +}; + +static const struct qcom_icc_desc sdx75_gem_noc = { + .nodes = gem_noc_nodes, + .num_nodes = ARRAY_SIZE(gem_noc_nodes), + .bcms = gem_noc_bcms, + .num_bcms = ARRAY_SIZE(gem_noc_bcms), +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] = { + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] = { + [MASTER_LLCC] = &llcc_mc, + [SLAVE_EBI1] = &ebi, +}; + +static const struct qcom_icc_desc sdx75_mc_virt = { + .nodes = mc_virt_nodes, + .num_nodes = ARRAY_SIZE(mc_virt_nodes), + .bcms = mc_virt_bcms, + .num_bcms = ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { + &bcm_sn1, + &bcm_sn4, +}; + +static struct qcom_icc_node * const pcie_anoc_nodes[] = { + [MASTER_PCIE_0] = &xm_pcie3_0, + [MASTER_PCIE_1] = &xm_pcie3_1, + [MASTER_PCIE_2] = &xm_pcie3_2, + [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc, +}; + +static const struct qcom_icc_desc sdx75_pcie_anoc = { + .nodes = pcie_anoc_nodes, + .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), + .bcms = pcie_anoc_bcms, + .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] = { + &bcm_ce0, + &bcm_cn0, + &bcm_sn0, + &bcm_sn1, + &bcm_sn2, +}; + +static struct qcom_icc_node * const system_noc_nodes[] = { + [MASTER_AUDIO] = &qhm_audio, + [MASTER_GIC_AHB] = &qhm_gic, + [MASTER_PCIE_RSCC] = &qhm_pcie_rscc, + [MASTER_QDSS_BAM] = &qhm_qdss_bam, + [MASTER_QPIC] = &qhm_qpic, + [MASTER_QUP_0] = &qhm_qup0, + [MASTER_ANOC_SNOC] = &qnm_aggre_noc, + [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, + [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, + [MASTER_SNOC_CFG] = &qnm_system_noc_cfg, + [MASTER_PCIE_ANOC_CFG] = &qnm_system_noc_pcie_cfg, + [MASTER_CRYPTO] = &qxm_crypto, + [MASTER_IPA] = &qxm_ipa, + [MASTER_MVMSS] = &qxm_mvmss, + [MASTER_EMAC_0] = &xm_emac_0, + [MASTER_EMAC_1] = &xm_emac_1, + [MASTER_QDSS_ETR] = &xm_qdss_etr0, + [MASTER_QDSS_ETR_1] = &xm_qdss_etr1, + [MASTER_SDCC_1] = &xm_sdc1, + [MASTER_SDCC_4] = &xm_sdc4, + [MASTER_USB3_0] = &xm_usb3, + [SLAVE_ETH0_CFG] = &ps_eth0_cfg, + [SLAVE_ETH1_CFG] = &ps_eth1_cfg, + [SLAVE_AUDIO] = &qhs_audio, + [SLAVE_CLK_CTL] = &qhs_clk_ctl, + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto_cfg, + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, + [SLAVE_IPA_CFG] = &qhs_ipa, + [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, + [SLAVE_CNOC_MSS] = &qhs_mss_cfg, + [SLAVE_ICBDI_MVMSS_CFG] = &qhs_mvmss_cfg, + [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, + [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, + [SLAVE_PCIE_2_CFG] = &qhs_pcie2_cfg, + [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rscc, + [SLAVE_PDM] = &qhs_pdm, + [SLAVE_PRNG] = &qhs_prng, + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, + [SLAVE_QPIC] = &qhs_qpic, + [SLAVE_QUP_0] = &qhs_qup0, + [SLAVE_SDCC_1] = &qhs_sdc1, + [SLAVE_SDCC_4] = &qhs_sdc4, + [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex, + [SLAVE_TCSR] = &qhs_tcsr, + [SLAVE_TLMM] = &qhs_tlmm, + [SLAVE_USB3] = &qhs_usb3, + [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy, + [SLAVE_A1NOC_CFG] = &qns_a1noc, + [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, + [SLAVE_SNOC_CFG] = &qns_system_noc_cfg, + [SLAVE_PCIE_ANOC_CFG] = &qns_system_noc_pcie_cfg, + [SLAVE_IMEM] = &qxs_imem, + [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_system_noc, + [SLAVE_SERVICE_SNOC] = &srvc_system_noc, + [SLAVE_PCIE_0] = &xs_pcie_0, + [SLAVE_PCIE_1] = &xs_pcie_1, + [SLAVE_PCIE_2] = &xs_pcie_2, + [SLAVE_QDSS_STM] = &xs_qdss_stm, + [SLAVE_TCU] = &xs_sys_tcu_cfg, +}; + +static const struct qcom_icc_desc sdx75_system_noc = { + .nodes = system_noc_nodes, + .num_nodes = ARRAY_SIZE(system_noc_nodes), + .bcms = system_noc_bcms, + .num_bcms = ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,sdx75-clk-virt", .data = &sdx75_clk_virt }, + { .compatible = "qcom,sdx75-dc-noc", .data = &sdx75_dc_noc }, + { .compatible = "qcom,sdx75-gem-noc", .data = &sdx75_gem_noc }, + { .compatible = "qcom,sdx75-mc-virt", .data = &sdx75_mc_virt }, + { .compatible = "qcom,sdx75-pcie-anoc", .data = &sdx75_pcie_anoc }, + { .compatible = "qcom,sdx75-system-noc", .data = &sdx75_system_noc }, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qcom_icc_rpmh_probe, + .remove_new = qcom_icc_rpmh_remove, + .driver = { + .name = "qnoc-sdx75", + .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("SDX75 NoC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/interconnect/qcom/sdx75.h b/drivers/interconnect/qcom/sdx75.h new file mode 100644 index 0000000000..24e8871599 --- /dev/null +++ b/drivers/interconnect/qcom/sdx75.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX75_H +#define __DRIVERS_INTERCONNECT_QCOM_SDX75_H + +#define SDX75_MASTER_ANOC_PCIE_GEM_NOC 0 +#define SDX75_MASTER_ANOC_SNOC 1 +#define SDX75_MASTER_APPSS_PROC 2 +#define SDX75_MASTER_AUDIO 3 +#define SDX75_MASTER_CNOC_DC_NOC 4 +#define SDX75_MASTER_CRYPTO 5 +#define SDX75_MASTER_EMAC_0 6 +#define SDX75_MASTER_EMAC_1 7 +#define SDX75_MASTER_GEM_NOC_CFG 8 +#define SDX75_MASTER_GEM_NOC_CNOC 9 +#define SDX75_MASTER_GEM_NOC_PCIE_SNOC 10 +#define SDX75_MASTER_GIC 11 +#define SDX75_MASTER_GIC_AHB 12 +#define SDX75_MASTER_IPA 13 +#define SDX75_MASTER_IPA_PCIE 14 +#define SDX75_MASTER_LLCC 15 +#define SDX75_MASTER_MSS_PROC 16 +#define SDX75_MASTER_MVMSS 17 +#define SDX75_MASTER_PCIE_0 18 +#define SDX75_MASTER_PCIE_1 19 +#define SDX75_MASTER_PCIE_2 20 +#define SDX75_MASTER_PCIE_ANOC_CFG 21 +#define SDX75_MASTER_PCIE_RSCC 22 +#define SDX75_MASTER_QDSS_BAM 23 +#define SDX75_MASTER_QDSS_ETR 24 +#define SDX75_MASTER_QDSS_ETR_1 25 +#define SDX75_MASTER_QPIC 26 +#define SDX75_MASTER_QPIC_CORE 27 +#define SDX75_MASTER_QUP_0 28 +#define SDX75_MASTER_QUP_CORE_0 29 +#define SDX75_MASTER_SDCC_1 30 +#define SDX75_MASTER_SDCC_4 31 +#define SDX75_MASTER_SNOC_CFG 32 +#define SDX75_MASTER_SNOC_SF_MEM_NOC 33 +#define SDX75_MASTER_SYS_TCU 34 +#define SDX75_MASTER_USB3_0 35 +#define SDX75_SLAVE_A1NOC_CFG 36 +#define SDX75_SLAVE_ANOC_PCIE_GEM_NOC 37 +#define SDX75_SLAVE_AUDIO 38 +#define SDX75_SLAVE_CLK_CTL 39 +#define SDX75_SLAVE_CRYPTO_0_CFG 40 +#define SDX75_SLAVE_CNOC_MSS 41 +#define SDX75_SLAVE_DDRSS_CFG 42 +#define SDX75_SLAVE_EBI1 43 +#define SDX75_SLAVE_ETH0_CFG 44 +#define SDX75_SLAVE_ETH1_CFG 45 +#define SDX75_SLAVE_GEM_NOC_CFG 46 +#define SDX75_SLAVE_GEM_NOC_CNOC 47 +#define SDX75_SLAVE_ICBDI_MVMSS_CFG 48 +#define SDX75_SLAVE_IMEM 49 +#define SDX75_SLAVE_IMEM_CFG 50 +#define SDX75_SLAVE_IPA_CFG 51 +#define SDX75_SLAVE_IPC_ROUTER_CFG 52 +#define SDX75_SLAVE_LAGG_CFG 53 +#define SDX75_SLAVE_LLCC 54 +#define SDX75_SLAVE_MCCC_MASTER 55 +#define SDX75_SLAVE_MEM_NOC_PCIE_SNOC 56 +#define SDX75_SLAVE_PCIE_0 57 +#define SDX75_SLAVE_PCIE_1 58 +#define SDX75_SLAVE_PCIE_2 59 +#define SDX75_SLAVE_PCIE_0_CFG 60 +#define SDX75_SLAVE_PCIE_1_CFG 61 +#define SDX75_SLAVE_PCIE_2_CFG 62 +#define SDX75_SLAVE_PCIE_ANOC_CFG 63 +#define SDX75_SLAVE_PCIE_RSC_CFG 64 +#define SDX75_SLAVE_PDM 65 +#define SDX75_SLAVE_PRNG 66 +#define SDX75_SLAVE_QDSS_CFG 67 +#define SDX75_SLAVE_QDSS_STM 68 +#define SDX75_SLAVE_QPIC 69 +#define SDX75_SLAVE_QPIC_CORE 70 +#define SDX75_SLAVE_QUP_0 71 +#define SDX75_SLAVE_QUP_CORE_0 72 +#define SDX75_SLAVE_SDCC_1 73 +#define SDX75_SLAVE_SDCC_4 74 +#define SDX75_SLAVE_SERVICE_GEM_NOC 75 +#define SDX75_SLAVE_SERVICE_PCIE_ANOC 76 +#define SDX75_SLAVE_SERVICE_SNOC 77 +#define SDX75_SLAVE_SNOC_CFG 78 +#define SDX75_SLAVE_SNOC_GEM_NOC_SF 79 +#define SDX75_SLAVE_SNOOP_BWMON 80 +#define SDX75_SLAVE_SPMI_VGI_COEX 81 +#define SDX75_SLAVE_TCSR 82 +#define SDX75_SLAVE_TCU 83 +#define SDX75_SLAVE_TLMM 84 +#define SDX75_SLAVE_USB3 85 +#define SDX75_SLAVE_USB3_PHY_CFG 86 + +#endif diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom/sm6350.c index f41d7e19ba..20923e8e61 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -1702,7 +1702,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm6350", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom/sm8150.c index edfe824cad..f29b77556a 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -1864,7 +1864,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm8150", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c index 2a2f56b993..02d40eea0d 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -1991,7 +1991,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm8250", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c index 562322d4fc..b321c3009a 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -1961,7 +1961,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm8350", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c index eb7e17df32..b3cd008737 100644 --- a/drivers/interconnect/qcom/sm8450.c +++ b/drivers/interconnect/qcom/sm8450.c @@ -1884,7 +1884,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm8450", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c index a10c8b6549..fc22cecf65 100644 --- a/drivers/interconnect/qcom/sm8550.c +++ b/drivers/interconnect/qcom/sm8550.c @@ -2219,10 +2219,11 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm8550", .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, }, }; 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