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path: root/drivers/mfd/lpc_ich.c
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Diffstat (limited to 'drivers/mfd/lpc_ich.c')
-rw-r--r--drivers/mfd/lpc_ich.c127
1 files changed, 103 insertions, 24 deletions
diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c
index 7b1c597b68..73a0e7f9bd 100644
--- a/drivers/mfd/lpc_ich.c
+++ b/drivers/mfd/lpc_ich.c
@@ -85,19 +85,6 @@
#define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
#define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
-struct lpc_ich_priv {
- int chipset;
-
- int abase; /* ACPI base */
- int actrl_pbase; /* ACPI control or PMC base */
- int gbase; /* GPIO base */
- int gctrl; /* GPIO control */
-
- int abase_save; /* Cached ACPI base value */
- int actrl_pbase_save; /* Cached ACPI control or PMC base value */
- int gctrl_save; /* Cached GPIO control value */
-};
-
static struct resource wdt_ich_res[] = {
/* ACPI - TCO */
{
@@ -144,22 +131,33 @@ static struct mfd_cell lpc_ich_gpio_cell = {
.ignore_resource_conflicts = true,
};
+#define INTEL_GPIO_RESOURCE_SIZE 0x1000
+
+struct lpc_ich_gpio_info {
+ const char *hid;
+ const struct mfd_cell *devices;
+ size_t nr_devices;
+ struct resource **resources;
+ size_t nr_resources;
+ const resource_size_t *offsets;
+};
+
#define APL_GPIO_NORTH 0
#define APL_GPIO_NORTHWEST 1
#define APL_GPIO_WEST 2
#define APL_GPIO_SOUTHWEST 3
+
#define APL_GPIO_NR_DEVICES 4
+#define APL_GPIO_NR_RESOURCES 4
/* Offset data for Apollo Lake GPIO controllers */
-static resource_size_t apl_gpio_offsets[APL_GPIO_NR_DEVICES] = {
+static const resource_size_t apl_gpio_offsets[APL_GPIO_NR_RESOURCES] = {
[APL_GPIO_NORTH] = 0xc50000,
[APL_GPIO_NORTHWEST] = 0xc40000,
[APL_GPIO_WEST] = 0xc70000,
[APL_GPIO_SOUTHWEST] = 0xc00000,
};
-#define APL_GPIO_RESOURCE_SIZE 0x1000
-
#define APL_GPIO_IRQ 14
static struct resource apl_gpio_resources[APL_GPIO_NR_DEVICES][2] = {
@@ -181,6 +179,13 @@ static struct resource apl_gpio_resources[APL_GPIO_NR_DEVICES][2] = {
},
};
+static struct resource *apl_gpio_mem_resources[APL_GPIO_NR_RESOURCES] = {
+ [APL_GPIO_NORTH] = &apl_gpio_resources[APL_GPIO_NORTH][0],
+ [APL_GPIO_NORTHWEST] = &apl_gpio_resources[APL_GPIO_NORTHWEST][0],
+ [APL_GPIO_WEST] = &apl_gpio_resources[APL_GPIO_WEST][0],
+ [APL_GPIO_SOUTHWEST] = &apl_gpio_resources[APL_GPIO_SOUTHWEST][0],
+};
+
static const struct mfd_cell apl_gpio_devices[APL_GPIO_NR_DEVICES] = {
[APL_GPIO_NORTH] = {
.name = "apollolake-pinctrl",
@@ -212,6 +217,58 @@ static const struct mfd_cell apl_gpio_devices[APL_GPIO_NR_DEVICES] = {
},
};
+static const struct lpc_ich_gpio_info apl_gpio_info = {
+ .hid = "INT3452",
+ .devices = apl_gpio_devices,
+ .nr_devices = ARRAY_SIZE(apl_gpio_devices),
+ .resources = apl_gpio_mem_resources,
+ .nr_resources = ARRAY_SIZE(apl_gpio_mem_resources),
+ .offsets = apl_gpio_offsets,
+};
+
+#define DNV_GPIO_NORTH 0
+#define DNV_GPIO_SOUTH 1
+
+#define DNV_GPIO_NR_DEVICES 1
+#define DNV_GPIO_NR_RESOURCES 2
+
+/* Offset data for Denverton GPIO controllers */
+static const resource_size_t dnv_gpio_offsets[DNV_GPIO_NR_RESOURCES] = {
+ [DNV_GPIO_NORTH] = 0xc20000,
+ [DNV_GPIO_SOUTH] = 0xc50000,
+};
+
+#define DNV_GPIO_IRQ 14
+
+static struct resource dnv_gpio_resources[DNV_GPIO_NR_RESOURCES + 1] = {
+ [DNV_GPIO_NORTH] = DEFINE_RES_MEM(0, 0),
+ [DNV_GPIO_SOUTH] = DEFINE_RES_MEM(0, 0),
+ DEFINE_RES_IRQ(DNV_GPIO_IRQ),
+};
+
+static struct resource *dnv_gpio_mem_resources[DNV_GPIO_NR_RESOURCES] = {
+ [DNV_GPIO_NORTH] = &dnv_gpio_resources[DNV_GPIO_NORTH],
+ [DNV_GPIO_SOUTH] = &dnv_gpio_resources[DNV_GPIO_SOUTH],
+};
+
+static const struct mfd_cell dnv_gpio_devices[DNV_GPIO_NR_DEVICES] = {
+ {
+ .name = "denverton-pinctrl",
+ .num_resources = ARRAY_SIZE(dnv_gpio_resources),
+ .resources = dnv_gpio_resources,
+ .ignore_resource_conflicts = true,
+ },
+};
+
+static const struct lpc_ich_gpio_info dnv_gpio_info = {
+ .hid = "INTC3000",
+ .devices = dnv_gpio_devices,
+ .nr_devices = ARRAY_SIZE(dnv_gpio_devices),
+ .resources = dnv_gpio_mem_resources,
+ .nr_resources = ARRAY_SIZE(dnv_gpio_mem_resources),
+ .offsets = dnv_gpio_offsets,
+};
+
static struct mfd_cell lpc_ich_spi_cell = {
.name = "intel-spi",
.num_resources = ARRAY_SIZE(intel_spi_res),
@@ -289,10 +346,24 @@ enum lpc_chipsets {
LPC_LEWISBURG, /* Lewisburg */
LPC_9S, /* 9 Series */
LPC_APL, /* Apollo Lake SoC */
+ LPC_DNV, /* Denverton SoC */
LPC_GLK, /* Gemini Lake SoC */
LPC_COUGARMOUNTAIN,/* Cougar Mountain SoC*/
};
+struct lpc_ich_priv {
+ enum lpc_chipsets chipset;
+
+ int abase; /* ACPI base */
+ int actrl_pbase; /* ACPI control or PMC base */
+ int gbase; /* GPIO base */
+ int gctrl; /* GPIO control */
+
+ int abase_save; /* Cached ACPI base value */
+ int actrl_pbase_save; /* Cached ACPI control or PMC base value */
+ int gctrl_save; /* Cached GPIO control value */
+};
+
static struct lpc_ich_info lpc_chipset_info[] = {
[LPC_ICH] = {
.name = "ICH",
@@ -618,8 +689,13 @@ static struct lpc_ich_info lpc_chipset_info[] = {
[LPC_APL] = {
.name = "Apollo Lake SoC",
.iTCO_version = 5,
+ .gpio_info = &apl_gpio_info,
.spi_type = INTEL_SPI_BXT,
},
+ [LPC_DNV] = {
+ .name = "Denverton SoC",
+ .gpio_info = &dnv_gpio_info,
+ },
[LPC_GLK] = {
.name = "Gemini Lake SoC",
.spi_type = INTEL_SPI_BXT,
@@ -638,6 +714,7 @@ static struct lpc_ich_info lpc_chipset_info[] = {
*/
static const struct pci_device_id lpc_ich_ids[] = {
{ PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL},
+ { PCI_VDEVICE(INTEL, 0x19dc), LPC_DNV},
{ PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
{ PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
@@ -1156,30 +1233,32 @@ wdt_done:
static int lpc_ich_init_pinctrl(struct pci_dev *dev)
{
+ struct lpc_ich_priv *priv = pci_get_drvdata(dev);
+ const struct lpc_ich_gpio_info *info = lpc_chipset_info[priv->chipset].gpio_info;
struct resource base;
unsigned int i;
int ret;
/* Check, if GPIO has been exported as an ACPI device */
- if (acpi_dev_present("INT3452", NULL, -1))
+ if (acpi_dev_present(info->hid, NULL, -1))
return -EEXIST;
ret = p2sb_bar(dev->bus, 0, &base);
if (ret)
return ret;
- for (i = 0; i < ARRAY_SIZE(apl_gpio_devices); i++) {
- struct resource *mem = &apl_gpio_resources[i][0];
- resource_size_t offset = apl_gpio_offsets[i];
+ for (i = 0; i < info->nr_resources; i++) {
+ struct resource *mem = info->resources[i];
+ resource_size_t offset = info->offsets[i];
/* Fill MEM resource */
mem->start = base.start + offset;
- mem->end = base.start + offset + APL_GPIO_RESOURCE_SIZE - 1;
+ mem->end = base.start + offset + INTEL_GPIO_RESOURCE_SIZE - 1;
mem->flags = base.flags;
}
- return mfd_add_devices(&dev->dev, 0, apl_gpio_devices,
- ARRAY_SIZE(apl_gpio_devices), NULL, 0, NULL);
+ return mfd_add_devices(&dev->dev, 0, info->devices, info->nr_devices,
+ NULL, 0, NULL);
}
static bool lpc_ich_byt_set_writeable(void __iomem *base, void *data)
@@ -1332,7 +1411,7 @@ static int lpc_ich_probe(struct pci_dev *dev,
cell_added = true;
}
- if (priv->chipset == LPC_APL) {
+ if (lpc_chipset_info[priv->chipset].gpio_info) {
ret = lpc_ich_init_pinctrl(dev);
if (!ret)
cell_added = true;