diff options
Diffstat (limited to 'drivers/pinctrl/samsung')
| -rw-r--r-- | drivers/pinctrl/samsung/Kconfig | 29 | ||||
| -rw-r--r-- | drivers/pinctrl/samsung/Makefile | 8 | ||||
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-exynos-arm.c | 893 | ||||
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 798 | ||||
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-exynos.c | 765 | ||||
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-exynos.h | 173 | ||||
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-s3c64xx.c | 806 | ||||
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-samsung.c | 1349 | ||||
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-samsung.h | 361 |
9 files changed, 5182 insertions, 0 deletions
diff --git a/drivers/pinctrl/samsung/Kconfig b/drivers/pinctrl/samsung/Kconfig new file mode 100644 index 0000000000..697ff7812d --- /dev/null +++ b/drivers/pinctrl/samsung/Kconfig @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Samsung Pin control drivers +# +config PINCTRL_SAMSUNG + bool + select GPIOLIB + select PINMUX + select PINCONF + +config PINCTRL_EXYNOS + bool "Pinctrl common driver part for Samsung Exynos SoCs" + depends on ARCH_EXYNOS || ARCH_S5PV210 || (COMPILE_TEST && OF) + select PINCTRL_SAMSUNG + select PINCTRL_EXYNOS_ARM if ARM && (ARCH_EXYNOS || ARCH_S5PV210) + select PINCTRL_EXYNOS_ARM64 if ARM64 && ARCH_EXYNOS + +config PINCTRL_EXYNOS_ARM + bool "ARMv7-specific pinctrl driver for Samsung Exynos SoCs" if COMPILE_TEST + depends on PINCTRL_EXYNOS + +config PINCTRL_EXYNOS_ARM64 + bool "ARMv8-specific pinctrl driver for Samsung Exynos SoCs" if COMPILE_TEST + depends on PINCTRL_EXYNOS + +config PINCTRL_S3C64XX + bool "Samsung S3C64XX SoC pinctrl driver" + depends on ARCH_S3C64XX || (COMPILE_TEST && OF) + select PINCTRL_SAMSUNG diff --git a/drivers/pinctrl/samsung/Makefile b/drivers/pinctrl/samsung/Makefile new file mode 100644 index 0000000000..4dd4a92ab6 --- /dev/null +++ b/drivers/pinctrl/samsung/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +# Samsung pin control drivers + +obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o +obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o +obj-$(CONFIG_PINCTRL_EXYNOS_ARM) += pinctrl-exynos-arm.o +obj-$(CONFIG_PINCTRL_EXYNOS_ARM64) += pinctrl-exynos-arm64.o +obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c new file mode 100644 index 0000000000..85ddf49a51 --- /dev/null +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c @@ -0,0 +1,893 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. +// +// Copyright (c) 2012 Samsung Electronics Co., Ltd. +// http://www.samsung.com +// Copyright (c) 2012 Linaro Ltd +// http://www.linaro.org +// +// Author: Thomas Abraham <thomas.ab@samsung.com> +// +// This file contains the Samsung Exynos specific information required by the +// the Samsung pinctrl/gpiolib driver. It also includes the implementation of +// external gpio and wakeup interrupt support. + +#include <linux/device.h> +#include <linux/of_address.h> +#include <linux/slab.h> +#include <linux/err.h> +#include <linux/soc/samsung/exynos-regs-pmu.h> + +#include "pinctrl-samsung.h" +#include "pinctrl-exynos.h" + +static const struct samsung_pin_bank_type bank_type_off = { + .fld_width = { 4, 1, 2, 2, 2, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, +}; + +static const struct samsung_pin_bank_type bank_type_alive = { + .fld_width = { 4, 1, 2, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + +/* Retention control for S5PV210 are located at the end of clock controller */ +#define S5P_OTHERS 0xE000 + +#define S5P_OTHERS_RET_IO (1 << 31) +#define S5P_OTHERS_RET_CF (1 << 30) +#define S5P_OTHERS_RET_MMC (1 << 29) +#define S5P_OTHERS_RET_UART (1 << 28) + +static void s5pv210_retention_disable(struct samsung_pinctrl_drv_data *drvdata) +{ + void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; + u32 tmp; + + tmp = __raw_readl(clk_base + S5P_OTHERS); + tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | S5P_OTHERS_RET_MMC | + S5P_OTHERS_RET_UART); + __raw_writel(tmp, clk_base + S5P_OTHERS); +} + +static struct samsung_retention_ctrl * +s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata, + const struct samsung_retention_data *data) +{ + struct samsung_retention_ctrl *ctrl; + struct device_node *np; + void __iomem *clk_base; + + ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return ERR_PTR(-ENOMEM); + + np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); + if (!np) { + pr_err("%s: failed to find clock controller DT node\n", + __func__); + return ERR_PTR(-ENODEV); + } + + clk_base = of_iomap(np, 0); + of_node_put(np); + if (!clk_base) { + pr_err("%s: failed to map clock registers\n", __func__); + return ERR_PTR(-EINVAL); + } + + ctrl->priv = (void __force *)clk_base; + ctrl->disable = s5pv210_retention_disable; + + return ctrl; +} + +static const struct samsung_retention_data s5pv210_retention_data __initconst = { + .init = s5pv210_retention_init, +}; + +/* pin banks of s5pv210 pin-controller */ +static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), + EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c), + EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20), + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24), + EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28), + EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c), + EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30), + EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34), + EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38), + EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c), + EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40), + EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44), + EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48), + EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c), + EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50), + EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54), + EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"), + EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"), + EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"), + EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"), + EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"), + EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"), + EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"), + EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"), + EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c), +}; + +static const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = s5pv210_pin_bank, + .nr_banks = ARRAY_SIZE(s5pv210_pin_bank), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &s5pv210_retention_data, + }, +}; + +const struct samsung_pinctrl_of_match_data s5pv210_of_data __initconst = { + .ctrl = s5pv210_pin_ctrl, + .num_ctrl = ARRAY_SIZE(s5pv210_pin_ctrl), +}; + +/* Pad retention control code for accessing PMU regmap */ +static atomic_t exynos_shared_retention_refcnt; + +/* pin banks of exynos3250 pin-controller 0 */ +static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18), +}; + +/* pin banks of exynos3250 pin-controller 1 */ +static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"), + EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"), + EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08), + EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), + EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), + EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30), + EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34), + EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), +}; + +/* + * PMU pad retention groups for Exynos3250 doesn't match pin banks, so handle + * them all together + */ +static const u32 exynos3250_retention_regs[] = { + S5P_PAD_RET_MAUDIO_OPTION, + S5P_PAD_RET_GPIO_OPTION, + S5P_PAD_RET_UART_OPTION, + S5P_PAD_RET_MMCA_OPTION, + S5P_PAD_RET_MMCB_OPTION, + S5P_PAD_RET_EBIA_OPTION, + S5P_PAD_RET_EBIB_OPTION, + S5P_PAD_RET_MMC2_OPTION, + S5P_PAD_RET_SPI_OPTION, +}; + +static const struct samsung_retention_data exynos3250_retention_data __initconst = { + .regs = exynos3250_retention_regs, + .nr_regs = ARRAY_SIZE(exynos3250_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + +/* + * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes + * two gpio/pin-mux/pinconfig controllers. + */ +static const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos3250_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos3250_retention_data, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos3250_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos3250_retention_data, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos3250_of_data __initconst = { + .ctrl = exynos3250_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos3250_pin_ctrl), +}; + +/* pin banks of exynos4210 pin-controller 0 */ +static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), + EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20), + EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24), + EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28), + EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), + EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), + EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), + EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), +}; + +/* pin banks of exynos4210 pin-controller 1 */ +static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00), + EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04), + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), + EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), + EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), + EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18), + EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), + EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos4210 pin-controller 2 */ +static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), +}; + +/* PMU pad retention groups registers for Exynos4 (without audio) */ +static const u32 exynos4_retention_regs[] = { + S5P_PAD_RET_GPIO_OPTION, + S5P_PAD_RET_UART_OPTION, + S5P_PAD_RET_MMCA_OPTION, + S5P_PAD_RET_MMCB_OPTION, + S5P_PAD_RET_EBIA_OPTION, + S5P_PAD_RET_EBIB_OPTION, +}; + +static const struct samsung_retention_data exynos4_retention_data __initconst = { + .regs = exynos4_retention_regs, + .nr_regs = ARRAY_SIZE(exynos4_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + +/* PMU retention control for audio pins can be tied to audio pin bank */ +static const u32 exynos4_audio_retention_regs[] = { + S5P_PAD_RET_MAUDIO_OPTION, +}; + +static const struct samsung_retention_data exynos4_audio_retention_data __initconst = { + .regs = exynos4_audio_retention_regs, + .nr_regs = ARRAY_SIZE(exynos4_audio_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .init = exynos_retention_init, +}; + +/* + * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes + * three gpio/pin-mux/pinconfig controllers. + */ +static const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos4210_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos4210_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos4210_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), + .retention_data = &exynos4_audio_retention_data, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos4210_of_data __initconst = { + .ctrl = exynos4210_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos4210_pin_ctrl), +}; + +/* pin banks of exynos4x12 pin-controller 0 */ +static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), + EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), + EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), + EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), + EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40), + EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44), +}; + +/* pin banks of exynos4x12 pin-controller 1 */ +static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), + EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), + EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), + EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), + EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18), + EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), + EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), + EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30), + EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34), + EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos4x12 pin-controller 2 */ +static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), +}; + +/* pin banks of exynos4x12 pin-controller 3 */ +static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10), +}; + +/* + * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +static const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos4x12_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos4x12_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos4x12_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_audio_retention_data, + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos4x12_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos4x12_of_data __initconst = { + .ctrl = exynos4x12_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos4x12_pin_ctrl), +}; + +/* pin banks of exynos5250 pin-controller 0 */ +static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), + EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20), + EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28), + EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30), + EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34), + EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5250 pin-controller 1 */ +static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), + EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), + EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), + EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), + EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20), +}; + +/* pin banks of exynos5250 pin-controller 2 */ +static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), +}; + +/* pin banks of exynos5250 pin-controller 3 */ +static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), +}; + +/* + * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +static const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5250_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5250_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5250_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos5250_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_audio_retention_data, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos5250_of_data __initconst = { + .ctrl = exynos5250_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos5250_pin_ctrl), +}; + +/* pin banks of exynos5260 pin-controller 0 */ +static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20), + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28), + EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30), + EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34), + EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38), + EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c), + EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40), + EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5260 pin-controller 1 */ +static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10), +}; + +/* pin banks of exynos5260 pin-controller 2 */ +static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), +}; + +/* + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes + * three gpio/pin-mux/pinconfig controllers. + */ +static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5260_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5260_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5260_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos5260_of_data __initconst = { + .ctrl = exynos5260_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos5260_pin_ctrl), +}; + +/* pin banks of exynos5410 pin-controller 0 */ +static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), + EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20), + EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30), + EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34), + EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38), + EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c), + EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40), + EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44), + EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48), + EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c), + EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50), + EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"), + EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"), + EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"), + EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5410 pin-controller 1 */ +static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c), + EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20), +}; + +/* pin banks of exynos5410 pin-controller 2 */ +static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), +}; + +/* pin banks of exynos5410 pin-controller 3 */ +static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), +}; + +/* + * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +static const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5410_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5410_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5410_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos5410_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos5410_of_data __initconst = { + .ctrl = exynos5410_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos5410_pin_ctrl), +}; + +/* pin banks of exynos5420 pin-controller 0 */ +static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5420 pin-controller 1 */ +static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04), + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14), + EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"), +}; + +/* pin banks of exynos5420 pin-controller 2 */ +static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), + EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), + EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), + EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), + EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c), +}; + +/* pin banks of exynos5420 pin-controller 3 */ +static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20), +}; + +/* pin banks of exynos5420 pin-controller 4 */ +static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), +}; + +/* PMU pad retention groups registers for Exynos5420 (without audio) */ +static const u32 exynos5420_retention_regs[] = { + EXYNOS_PAD_RET_DRAM_OPTION, + EXYNOS_PAD_RET_JTAG_OPTION, + EXYNOS5420_PAD_RET_GPIO_OPTION, + EXYNOS5420_PAD_RET_UART_OPTION, + EXYNOS5420_PAD_RET_MMCA_OPTION, + EXYNOS5420_PAD_RET_MMCB_OPTION, + EXYNOS5420_PAD_RET_MMCC_OPTION, + EXYNOS5420_PAD_RET_HSI_OPTION, + EXYNOS_PAD_RET_EBIA_OPTION, + EXYNOS_PAD_RET_EBIB_OPTION, + EXYNOS5420_PAD_RET_SPI_OPTION, + EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, +}; + +static const struct samsung_retention_data exynos5420_retention_data __initconst = { + .regs = exynos5420_retention_regs, + .nr_regs = ARRAY_SIZE(exynos5420_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + +/* + * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +static const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5420_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5420_retention_data, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5420_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5420_retention_data, + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5420_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5420_retention_data, + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos5420_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5420_retention_data, + }, { + /* pin-controller instance 4 data */ + .pin_banks = exynos5420_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_audio_retention_data, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos5420_of_data __initconst = { + .ctrl = exynos5420_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos5420_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c new file mode 100644 index 0000000000..cb965cf937 --- /dev/null +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -0,0 +1,798 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Exynos ARMv8 specific support for Samsung pinctrl/gpiolib driver +// with eint support. +// +// Copyright (c) 2012 Samsung Electronics Co., Ltd. +// http://www.samsung.com +// Copyright (c) 2012 Linaro Ltd +// http://www.linaro.org +// Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org> +// +// This file contains the Samsung Exynos specific information required by the +// the Samsung pinctrl/gpiolib driver. It also includes the implementation of +// external gpio and wakeup interrupt support. + +#include <linux/slab.h> +#include <linux/soc/samsung/exynos-regs-pmu.h> + +#include "pinctrl-samsung.h" +#include "pinctrl-exynos.h" + +static const struct samsung_pin_bank_type bank_type_off = { + .fld_width = { 4, 1, 2, 2, 2, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, +}; + +static const struct samsung_pin_bank_type bank_type_alive = { + .fld_width = { 4, 1, 2, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + +/* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */ +static const struct samsung_pin_bank_type exynos5433_bank_type_off = { + .fld_width = { 4, 1, 2, 4, 2, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, +}; + +static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { + .fld_width = { 4, 1, 2, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + +/* + * Bank type for non-alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4 + */ +static const struct samsung_pin_bank_type exynos850_bank_type_off = { + .fld_width = { 4, 1, 4, 4, 2, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, +}; + +/* + * Bank type for alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 4, DRV: 4 + */ +static const struct samsung_pin_bank_type exynos850_bank_type_alive = { + .fld_width = { 4, 1, 4, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + +/* Pad retention control code for accessing PMU regmap */ +static atomic_t exynos_shared_retention_refcnt; + +/* pin banks of exynos5433 pin-controller - ALIVE */ +static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), + EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), + EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), + EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), + EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1), + EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1), + EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1), + EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1), + EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1), +}; + +/* pin banks of exynos5433 pin-controller - AUD */ +static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), + EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), +}; + +/* pin banks of exynos5433 pin-controller - CPIF */ +static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00), +}; + +/* pin banks of exynos5433 pin-controller - eSE */ +static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00), +}; + +/* pin banks of exynos5433 pin-controller - FINGER */ +static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00), +}; + +/* pin banks of exynos5433 pin-controller - FSYS */ +static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00), + EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04), + EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08), + EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c), + EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10), + EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14), +}; + +/* pin banks of exynos5433 pin-controller - IMEM */ +static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00), +}; + +/* pin banks of exynos5433 pin-controller - NFC */ +static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), +}; + +/* pin banks of exynos5433 pin-controller - PERIC */ +static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00), + EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04), + EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08), + EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c), + EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10), + EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14), + EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18), + EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c), + EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20), + EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24), + EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28), + EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c), + EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30), + EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34), + EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38), + EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c), + EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), +}; + +/* pin banks of exynos5433 pin-controller - TOUCH */ +static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), +}; + +/* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */ +static const u32 exynos5433_retention_regs[] = { + EXYNOS5433_PAD_RETENTION_TOP_OPTION, + EXYNOS5433_PAD_RETENTION_UART_OPTION, + EXYNOS5433_PAD_RETENTION_EBIA_OPTION, + EXYNOS5433_PAD_RETENTION_EBIB_OPTION, + EXYNOS5433_PAD_RETENTION_SPI_OPTION, + EXYNOS5433_PAD_RETENTION_MIF_OPTION, + EXYNOS5433_PAD_RETENTION_USBXTI_OPTION, + EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION, + EXYNOS5433_PAD_RETENTION_UFS_OPTION, + EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION, +}; + +static const struct samsung_retention_data exynos5433_retention_data __initconst = { + .regs = exynos5433_retention_regs, + .nr_regs = ARRAY_SIZE(exynos5433_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + +/* PMU retention control for audio pins can be tied to audio pin bank */ +static const u32 exynos5433_audio_retention_regs[] = { + EXYNOS5433_PAD_RETENTION_AUD_OPTION, +}; + +static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = { + .regs = exynos5433_audio_retention_regs, + .nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .init = exynos_retention_init, +}; + +/* PMU retention control for mmc pins can be tied to fsys pin bank */ +static const u32 exynos5433_fsys_retention_regs[] = { + EXYNOS5433_PAD_RETENTION_MMC0_OPTION, + EXYNOS5433_PAD_RETENTION_MMC1_OPTION, + EXYNOS5433_PAD_RETENTION_MMC2_OPTION, +}; + +static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = { + .regs = exynos5433_fsys_retention_regs, + .nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .init = exynos_retention_init, +}; + +/* + * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes + * ten gpio/pin-mux/pinconfig controllers. + */ +static const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5433_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .nr_ext_resources = 1, + .retention_data = &exynos5433_retention_data, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5433_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5433_audio_retention_data, + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5433_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5433_retention_data, + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos5433_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5433_retention_data, + }, { + /* pin-controller instance 4 data */ + .pin_banks = exynos5433_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5433_retention_data, + }, { + /* pin-controller instance 5 data */ + .pin_banks = exynos5433_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5433_fsys_retention_data, + }, { + /* pin-controller instance 6 data */ + .pin_banks = exynos5433_pin_banks6, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks6), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5433_retention_data, + }, { + /* pin-controller instance 7 data */ + .pin_banks = exynos5433_pin_banks7, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks7), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5433_retention_data, + }, { + /* pin-controller instance 8 data */ + .pin_banks = exynos5433_pin_banks8, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks8), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5433_retention_data, + }, { + /* pin-controller instance 9 data */ + .pin_banks = exynos5433_pin_banks9, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks9), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5433_retention_data, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos5433_of_data __initconst = { + .ctrl = exynos5433_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos5433_pin_ctrl), +}; + +/* pin banks of exynos7 pin-controller - ALIVE */ +static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), +}; + +/* pin banks of exynos7 pin-controller - BUS0 */ +static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04), + EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08), + EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), + EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c), + EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20), + EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24), + EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28), + EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c), + EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30), + EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34), + EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38), +}; + +/* pin banks of exynos7 pin-controller - NFC */ +static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), +}; + +/* pin banks of exynos7 pin-controller - TOUCH */ +static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), +}; + +/* pin banks of exynos7 pin-controller - FF */ +static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00), +}; + +/* pin banks of exynos7 pin-controller - ESE */ +static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00), +}; + +/* pin banks of exynos7 pin-controller - FSYS0 */ +static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00), +}; + +/* pin banks of exynos7 pin-controller - FSYS1 */ +static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04), + EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c), +}; + +/* pin banks of exynos7 pin-controller - BUS1 */ +static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c), + EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14), + EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18), + EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c), + EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20), + EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24), +}; + +static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), +}; + +static const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 Alive data */ + .pin_banks = exynos7_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 1 BUS0 data */ + .pin_banks = exynos7_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 2 NFC data */ + .pin_banks = exynos7_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 3 TOUCH data */ + .pin_banks = exynos7_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 4 FF data */ + .pin_banks = exynos7_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 5 ESE data */ + .pin_banks = exynos7_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 6 FSYS0 data */ + .pin_banks = exynos7_pin_banks6, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks6), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 7 FSYS1 data */ + .pin_banks = exynos7_pin_banks7, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks7), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 8 BUS1 data */ + .pin_banks = exynos7_pin_banks8, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks8), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 9 AUD data */ + .pin_banks = exynos7_pin_banks9, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks9), + .eint_gpio_init = exynos_eint_gpio_init, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { + .ctrl = exynos7_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl), +}; + +/* pin banks of exynos7885 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynos7885_pin_banks0[] __initconst = { + EXYNOS_PIN_BANK_EINTN(3, 0x000, "etc0"), + EXYNOS_PIN_BANK_EINTN(3, 0x020, "etc1"), + EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa0", 0x00), + EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa1", 0x04), + EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa2", 0x08), + EXYNOS850_PIN_BANK_EINTW(5, 0x0a0, "gpq0", 0x0c), +}; + +/* pin banks of exynos7885 pin-controller 1 (DISPAUD) */ +static const struct samsung_pin_bank_data exynos7885_pin_banks1[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), + EXYNOS850_PIN_BANK_EINTG(4, 0x020, "gpb1", 0x04), + EXYNOS850_PIN_BANK_EINTG(5, 0x040, "gpb2", 0x08), +}; + +/* pin banks of exynos7885 pin-controller 2 (FSYS) */ +static const struct samsung_pin_bank_data exynos7885_pin_banks2[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf2", 0x04), + EXYNOS850_PIN_BANK_EINTG(6, 0x040, "gpf3", 0x08), + EXYNOS850_PIN_BANK_EINTG(6, 0x060, "gpf4", 0x0c), +}; + +/* pin banks of exynos7885 pin-controller 3 (TOP) */ +static const struct samsung_pin_bank_data exynos7885_pin_banks3[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpp0", 0x00), + EXYNOS850_PIN_BANK_EINTG(3, 0x020, "gpg0", 0x04), + EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), + EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c), + EXYNOS850_PIN_BANK_EINTG(3, 0x080, "gpp3", 0x10), + EXYNOS850_PIN_BANK_EINTG(6, 0x0a0, "gpp4", 0x14), + EXYNOS850_PIN_BANK_EINTG(4, 0x0c0, "gpp5", 0x18), + EXYNOS850_PIN_BANK_EINTG(5, 0x0e0, "gpp6", 0x1c), + EXYNOS850_PIN_BANK_EINTG(2, 0x100, "gpp7", 0x20), + EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp8", 0x24), + EXYNOS850_PIN_BANK_EINTG(8, 0x140, "gpg1", 0x28), + EXYNOS850_PIN_BANK_EINTG(8, 0x160, "gpg2", 0x2c), + EXYNOS850_PIN_BANK_EINTG(8, 0x180, "gpg3", 0x30), + EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpg4", 0x34), + EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpc0", 0x38), + EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpc1", 0x3c), + EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpc2", 0x40), +}; + +static const struct samsung_pin_ctrl exynos7885_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 Alive data */ + .pin_banks = exynos7885_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos7885_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 DISPAUD data */ + .pin_banks = exynos7885_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos7885_pin_banks1), + }, { + /* pin-controller instance 2 FSYS data */ + .pin_banks = exynos7885_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos7885_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 3 TOP data */ + .pin_banks = exynos7885_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos7885_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos7885_of_data __initconst = { + .ctrl = exynos7885_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos7885_pin_ctrl), +}; + +/* pin banks of exynos850 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), + EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), + EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), + EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), + EXYNOS850_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10), + EXYNOS850_PIN_BANK_EINTN(3, 0x0a0, "gpq0"), +}; + +/* pin banks of exynos850 pin-controller 1 (CMGP) */ +static const struct samsung_pin_bank_data exynos850_pin_banks1[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), + EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), + EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), + EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0c), + EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), + EXYNOS850_PIN_BANK_EINTW(1, 0x0a0, "gpm5", 0x14), + EXYNOS850_PIN_BANK_EINTW(1, 0x0c0, "gpm6", 0x18), + EXYNOS850_PIN_BANK_EINTW(1, 0x0e0, "gpm7", 0x1c), +}; + +/* pin banks of exynos850 pin-controller 2 (AUD) */ +static const struct samsung_pin_bank_data exynos850_pin_banks2[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), + EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04), +}; + +/* pin banks of exynos850 pin-controller 3 (HSI) */ +static const struct samsung_pin_bank_data exynos850_pin_banks3[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00), +}; + +/* pin banks of exynos850 pin-controller 4 (CORE) */ +static const struct samsung_pin_bank_data exynos850_pin_banks4[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), +}; + +/* pin banks of exynos850 pin-controller 5 (PERI) */ +static const struct samsung_pin_bank_data exynos850_pin_banks5[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00), + EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04), + EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), + EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10), + EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpg2", 0x14), + EXYNOS850_PIN_BANK_EINTG(1, 0x0c0, "gpg3", 0x18), + EXYNOS850_PIN_BANK_EINTG(3, 0x0e0, "gpc0", 0x1c), + EXYNOS850_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20), +}; + +static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos850_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 1 CMGP data */ + .pin_banks = exynos850_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks1), + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 2 AUD data */ + .pin_banks = exynos850_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks2), + }, { + /* pin-controller instance 3 HSI data */ + .pin_banks = exynos850_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 4 CORE data */ + .pin_banks = exynos850_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 5 PERI data */ + .pin_banks = exynos850_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = { + .ctrl = exynos850_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl), +}; + +/* pin banks of exynosautov9 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynosautov9_pin_banks0[] __initconst = { + EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), + EXYNOS850_PIN_BANK_EINTW(2, 0x020, "gpa1", 0x04), + EXYNOS850_PIN_BANK_EINTN(2, 0x040, "gpq0"), +}; + +/* pin banks of exynosautov9 pin-controller 1 (AUD) */ +static const struct samsung_pin_bank_data exynosautov9_pin_banks1[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpb1", 0x04), + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpb2", 0x08), + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpb3", 0x0C), +}; + +/* pin banks of exynosautov9 pin-controller 2 (FSYS0) */ +static const struct samsung_pin_bank_data exynosautov9_pin_banks2[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf0", 0x00), + EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf1", 0x04), +}; + +/* pin banks of exynosautov9 pin-controller 3 (FSYS1) */ +static const struct samsung_pin_bank_data exynosautov9_pin_banks3[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf8", 0x00), +}; + +/* pin banks of exynosautov9 pin-controller 4 (FSYS2) */ +static const struct samsung_pin_bank_data exynosautov9_pin_banks4[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf2", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf3", 0x04), + EXYNOS850_PIN_BANK_EINTG(7, 0x040, "gpf4", 0x08), + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpf5", 0x0C), + EXYNOS850_PIN_BANK_EINTG(7, 0x080, "gpf6", 0x10), +}; + +/* pin banks of exynosautov9 pin-controller 5 (PERIC0) */ +static const struct samsung_pin_bank_data exynosautov9_pin_banks5[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), + EXYNOS850_PIN_BANK_EINTG(5, 0x060, "gpg0", 0x0C), +}; + +/* pin banks of exynosautov9 pin-controller 6 (PERIC1) */ +static const struct samsung_pin_bank_data exynosautov9_pin_banks6[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp3", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp4", 0x04), + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp5", 0x08), + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpg1", 0x0C), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg2", 0x10), + EXYNOS850_PIN_BANK_EINTG(4, 0x0A0, "gpg3", 0x14), +}; + +static const struct samsung_pin_ctrl exynosautov9_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynosautov9_pin_banks0, + .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 AUD data */ + .pin_banks = exynosautov9_pin_banks1, + .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks1), + }, { + /* pin-controller instance 2 FSYS0 data */ + .pin_banks = exynosautov9_pin_banks2, + .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 3 FSYS1 data */ + .pin_banks = exynosautov9_pin_banks3, + .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 4 FSYS2 data */ + .pin_banks = exynosautov9_pin_banks4, + .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 5 PERIC0 data */ + .pin_banks = exynosautov9_pin_banks5, + .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 6 PERIC1 data */ + .pin_banks = exynosautov9_pin_banks6, + .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks6), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + +const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = { + .ctrl = exynosautov9_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynosautov9_pin_ctrl), +}; + +/* + * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three + * gpio/pin-mux/pinconfig controllers. + */ + +/* pin banks of FSD pin-controller 0 (FSYS) */ +static const struct samsung_pin_bank_data fsd_pin_banks0[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(7, 0x00, "gpf0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gpf1", 0x04), + EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gpf6", 0x08), + EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpf4", 0x0c), + EXYNOS850_PIN_BANK_EINTG(6, 0x80, "gpf5", 0x10), +}; + +/* pin banks of FSD pin-controller 1 (PERIC) */ +static const struct samsung_pin_bank_data fsd_pin_banks1[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpc8", 0x00), + EXYNOS850_PIN_BANK_EINTG(7, 0x020, "gpf2", 0x04), + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpf3", 0x08), + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpd0", 0x0c), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpb0", 0x10), + EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpb1", 0x14), + EXYNOS850_PIN_BANK_EINTG(8, 0x0c0, "gpb4", 0x18), + EXYNOS850_PIN_BANK_EINTG(4, 0x0e0, "gpb5", 0x1c), + EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb6", 0x20), + EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb7", 0x24), + EXYNOS850_PIN_BANK_EINTG(5, 0x140, "gpd1", 0x28), + EXYNOS850_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), + EXYNOS850_PIN_BANK_EINTG(7, 0x180, "gpd3", 0x30), + EXYNOS850_PIN_BANK_EINTG(8, 0x1a0, "gpg0", 0x34), + EXYNOS850_PIN_BANK_EINTG(8, 0x1c0, "gpg1", 0x38), + EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpg2", 0x3c), + EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), + EXYNOS850_PIN_BANK_EINTG(8, 0x220, "gpg4", 0x44), + EXYNOS850_PIN_BANK_EINTG(8, 0x240, "gpg5", 0x48), + EXYNOS850_PIN_BANK_EINTG(8, 0x260, "gpg6", 0x4c), + EXYNOS850_PIN_BANK_EINTG(8, 0x280, "gpg7", 0x50), +}; + +/* pin banks of FSD pin-controller 2 (PMU) */ +static const struct samsung_pin_bank_data fsd_pin_banks2[] __initconst = { + EXYNOS850_PIN_BANK_EINTN(3, 0x00, "gpq0"), +}; + +static const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 FSYS0 data */ + .pin_banks = fsd_pin_banks0, + .nr_banks = ARRAY_SIZE(fsd_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 PERIC data */ + .pin_banks = fsd_pin_banks1, + .nr_banks = ARRAY_SIZE(fsd_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 PMU data */ + .pin_banks = fsd_pin_banks2, + .nr_banks = ARRAY_SIZE(fsd_pin_banks2), + }, +}; + +const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { + .ctrl = fsd_pin_ctrl, + .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c new file mode 100644 index 0000000000..a8212fc126 --- /dev/null +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -0,0 +1,765 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. +// +// Copyright (c) 2012 Samsung Electronics Co., Ltd. +// http://www.samsung.com +// Copyright (c) 2012 Linaro Ltd +// http://www.linaro.org +// +// Author: Thomas Abraham <thomas.ab@samsung.com> +// +// This file contains the Samsung Exynos specific information required by the +// the Samsung pinctrl/gpiolib driver. It also includes the implementation of +// external gpio and wakeup interrupt support. + +#include <linux/device.h> +#include <linux/interrupt.h> +#include <linux/irqdomain.h> +#include <linux/irq.h> +#include <linux/irqchip/chained_irq.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/slab.h> +#include <linux/spinlock.h> +#include <linux/regmap.h> +#include <linux/err.h> +#include <linux/soc/samsung/exynos-pmu.h> +#include <linux/soc/samsung/exynos-regs-pmu.h> + +#include "pinctrl-samsung.h" +#include "pinctrl-exynos.h" + +struct exynos_irq_chip { + struct irq_chip chip; + + u32 eint_con; + u32 eint_mask; + u32 eint_pend; + u32 *eint_wake_mask_value; + u32 eint_wake_mask_reg; + void (*set_eint_wakeup_mask)(struct samsung_pinctrl_drv_data *drvdata, + struct exynos_irq_chip *irq_chip); +}; + +static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip) +{ + return container_of(chip, struct exynos_irq_chip, chip); +} + +static void exynos_irq_mask(struct irq_data *irqd) +{ + struct irq_chip *chip = irq_data_get_irq_chip(irqd); + struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; + unsigned int mask; + unsigned long flags; + + raw_spin_lock_irqsave(&bank->slock, flags); + + mask = readl(bank->eint_base + reg_mask); + mask |= 1 << irqd->hwirq; + writel(mask, bank->eint_base + reg_mask); + + raw_spin_unlock_irqrestore(&bank->slock, flags); +} + +static void exynos_irq_ack(struct irq_data *irqd) +{ + struct irq_chip *chip = irq_data_get_irq_chip(irqd); + struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; + + writel(1 << irqd->hwirq, bank->eint_base + reg_pend); +} + +static void exynos_irq_unmask(struct irq_data *irqd) +{ + struct irq_chip *chip = irq_data_get_irq_chip(irqd); + struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; + unsigned int mask; + unsigned long flags; + + /* + * Ack level interrupts right before unmask + * + * If we don't do this we'll get a double-interrupt. Level triggered + * interrupts must not fire an interrupt if the level is not + * _currently_ active, even if it was active while the interrupt was + * masked. + */ + if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) + exynos_irq_ack(irqd); + + raw_spin_lock_irqsave(&bank->slock, flags); + + mask = readl(bank->eint_base + reg_mask); + mask &= ~(1 << irqd->hwirq); + writel(mask, bank->eint_base + reg_mask); + + raw_spin_unlock_irqrestore(&bank->slock, flags); +} + +static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) +{ + struct irq_chip *chip = irq_data_get_irq_chip(irqd); + struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; + unsigned int con, trig_type; + unsigned long reg_con = our_chip->eint_con + bank->eint_offset; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + trig_type = EXYNOS_EINT_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + trig_type = EXYNOS_EINT_EDGE_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + trig_type = EXYNOS_EINT_EDGE_BOTH; + break; + case IRQ_TYPE_LEVEL_HIGH: + trig_type = EXYNOS_EINT_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + trig_type = EXYNOS_EINT_LEVEL_LOW; + break; + default: + pr_err("unsupported external interrupt type\n"); + return -EINVAL; + } + + if (type & IRQ_TYPE_EDGE_BOTH) + irq_set_handler_locked(irqd, handle_edge_irq); + else + irq_set_handler_locked(irqd, handle_level_irq); + + con = readl(bank->eint_base + reg_con); + con &= ~(EXYNOS_EINT_CON_MASK << shift); + con |= trig_type << shift; + writel(con, bank->eint_base + reg_con); + + return 0; +} + +static int exynos_irq_request_resources(struct irq_data *irqd) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + const struct samsung_pin_bank_type *bank_type = bank->type; + unsigned long reg_con, flags; + unsigned int shift, mask, con; + int ret; + + ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq); + if (ret) { + dev_err(bank->gpio_chip.parent, + "unable to lock pin %s-%lu IRQ\n", + bank->name, irqd->hwirq); + return ret; + } + + reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; + shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; + mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; + + raw_spin_lock_irqsave(&bank->slock, flags); + + con = readl(bank->pctl_base + reg_con); + con &= ~(mask << shift); + con |= EXYNOS_PIN_CON_FUNC_EINT << shift; + writel(con, bank->pctl_base + reg_con); + + raw_spin_unlock_irqrestore(&bank->slock, flags); + + return 0; +} + +static void exynos_irq_release_resources(struct irq_data *irqd) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + const struct samsung_pin_bank_type *bank_type = bank->type; + unsigned long reg_con, flags; + unsigned int shift, mask, con; + + reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; + shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; + mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; + + raw_spin_lock_irqsave(&bank->slock, flags); + + con = readl(bank->pctl_base + reg_con); + con &= ~(mask << shift); + con |= PIN_CON_FUNC_INPUT << shift; + writel(con, bank->pctl_base + reg_con); + + raw_spin_unlock_irqrestore(&bank->slock, flags); + + gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq); +} + +/* + * irq_chip for gpio interrupts. + */ +static const struct exynos_irq_chip exynos_gpio_irq_chip __initconst = { + .chip = { + .name = "exynos_gpio_irq_chip", + .irq_unmask = exynos_irq_unmask, + .irq_mask = exynos_irq_mask, + .irq_ack = exynos_irq_ack, + .irq_set_type = exynos_irq_set_type, + .irq_request_resources = exynos_irq_request_resources, + .irq_release_resources = exynos_irq_release_resources, + }, + .eint_con = EXYNOS_GPIO_ECON_OFFSET, + .eint_mask = EXYNOS_GPIO_EMASK_OFFSET, + .eint_pend = EXYNOS_GPIO_EPEND_OFFSET, + /* eint_wake_mask_value not used */ +}; + +static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct samsung_pin_bank *b = h->host_data; + + irq_set_chip_data(virq, b); + irq_set_chip_and_handler(virq, &b->irq_chip->chip, + handle_level_irq); + return 0; +} + +/* + * irq domain callbacks for external gpio and wakeup interrupt controllers. + */ +static const struct irq_domain_ops exynos_eint_irqd_ops = { + .map = exynos_eint_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) +{ + struct samsung_pinctrl_drv_data *d = data; + struct samsung_pin_bank *bank = d->pin_banks; + unsigned int svc, group, pin; + int ret; + + svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); + group = EXYNOS_SVC_GROUP(svc); + pin = svc & EXYNOS_SVC_NUM_MASK; + + if (!group) + return IRQ_HANDLED; + bank += (group - 1); + + ret = generic_handle_domain_irq(bank->irq_domain, pin); + if (ret) + return IRQ_NONE; + + return IRQ_HANDLED; +} + +struct exynos_eint_gpio_save { + u32 eint_con; + u32 eint_fltcon0; + u32 eint_fltcon1; + u32 eint_mask; +}; + +/* + * exynos_eint_gpio_init() - setup handling of external gpio interrupts. + * @d: driver data of samsung pinctrl driver. + */ +__init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) +{ + struct samsung_pin_bank *bank; + struct device *dev = d->dev; + int ret; + int i; + + if (!d->irq) { + dev_err(dev, "irq number not available\n"); + return -EINVAL; + } + + ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq, + 0, dev_name(dev), d); + if (ret) { + dev_err(dev, "irq request failed\n"); + return -ENXIO; + } + + bank = d->pin_banks; + for (i = 0; i < d->nr_banks; ++i, ++bank) { + if (bank->eint_type != EINT_TYPE_GPIO) + continue; + + bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip, + sizeof(*bank->irq_chip), GFP_KERNEL); + if (!bank->irq_chip) { + ret = -ENOMEM; + goto err_domains; + } + bank->irq_chip->chip.name = bank->name; + + bank->irq_domain = irq_domain_create_linear(bank->fwnode, + bank->nr_pins, &exynos_eint_irqd_ops, bank); + if (!bank->irq_domain) { + dev_err(dev, "gpio irq domain add failed\n"); + ret = -ENXIO; + goto err_domains; + } + + bank->soc_priv = devm_kzalloc(d->dev, + sizeof(struct exynos_eint_gpio_save), GFP_KERNEL); + if (!bank->soc_priv) { + irq_domain_remove(bank->irq_domain); + ret = -ENOMEM; + goto err_domains; + } + + } + + return 0; + +err_domains: + for (--i, --bank; i >= 0; --i, --bank) { + if (bank->eint_type != EINT_TYPE_GPIO) + continue; + irq_domain_remove(bank->irq_domain); + } + + return ret; +} + +static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) +{ + struct irq_chip *chip = irq_data_get_irq_chip(irqd); + struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); + + pr_info("wake %s for irq %u (%s-%lu)\n", on ? "enabled" : "disabled", + irqd->irq, bank->name, irqd->hwirq); + + if (!on) + *our_chip->eint_wake_mask_value |= bit; + else + *our_chip->eint_wake_mask_value &= ~bit; + + return 0; +} + +static void +exynos_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata, + struct exynos_irq_chip *irq_chip) +{ + struct regmap *pmu_regs; + + if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) { + dev_warn(drvdata->dev, + "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n"); + return; + } + + pmu_regs = drvdata->retention_ctrl->priv; + dev_info(drvdata->dev, + "Setting external wakeup interrupt mask: 0x%x\n", + *irq_chip->eint_wake_mask_value); + + regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg, + *irq_chip->eint_wake_mask_value); +} + +static void +s5pv210_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata, + struct exynos_irq_chip *irq_chip) + +{ + void __iomem *clk_base; + + if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) { + dev_warn(drvdata->dev, + "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n"); + return; + } + + + clk_base = (void __iomem *) drvdata->retention_ctrl->priv; + + __raw_writel(*irq_chip->eint_wake_mask_value, + clk_base + irq_chip->eint_wake_mask_reg); +} + +static u32 eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED; +/* + * irq_chip for wakeup interrupts + */ +static const struct exynos_irq_chip s5pv210_wkup_irq_chip __initconst = { + .chip = { + .name = "s5pv210_wkup_irq_chip", + .irq_unmask = exynos_irq_unmask, + .irq_mask = exynos_irq_mask, + .irq_ack = exynos_irq_ack, + .irq_set_type = exynos_irq_set_type, + .irq_set_wake = exynos_wkup_irq_set_wake, + .irq_request_resources = exynos_irq_request_resources, + .irq_release_resources = exynos_irq_release_resources, + }, + .eint_con = EXYNOS_WKUP_ECON_OFFSET, + .eint_mask = EXYNOS_WKUP_EMASK_OFFSET, + .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, + .eint_wake_mask_value = &eint_wake_mask_value, + /* Only differences with exynos4210_wkup_irq_chip: */ + .eint_wake_mask_reg = S5PV210_EINT_WAKEUP_MASK, + .set_eint_wakeup_mask = s5pv210_pinctrl_set_eint_wakeup_mask, +}; + +static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = { + .chip = { + .name = "exynos4210_wkup_irq_chip", + .irq_unmask = exynos_irq_unmask, + .irq_mask = exynos_irq_mask, + .irq_ack = exynos_irq_ack, + .irq_set_type = exynos_irq_set_type, + .irq_set_wake = exynos_wkup_irq_set_wake, + .irq_request_resources = exynos_irq_request_resources, + .irq_release_resources = exynos_irq_release_resources, + }, + .eint_con = EXYNOS_WKUP_ECON_OFFSET, + .eint_mask = EXYNOS_WKUP_EMASK_OFFSET, + .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, + .eint_wake_mask_value = &eint_wake_mask_value, + .eint_wake_mask_reg = EXYNOS_EINT_WAKEUP_MASK, + .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask, +}; + +static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = { + .chip = { + .name = "exynos7_wkup_irq_chip", + .irq_unmask = exynos_irq_unmask, + .irq_mask = exynos_irq_mask, + .irq_ack = exynos_irq_ack, + .irq_set_type = exynos_irq_set_type, + .irq_set_wake = exynos_wkup_irq_set_wake, + .irq_request_resources = exynos_irq_request_resources, + .irq_release_resources = exynos_irq_release_resources, + }, + .eint_con = EXYNOS7_WKUP_ECON_OFFSET, + .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET, + .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET, + .eint_wake_mask_value = &eint_wake_mask_value, + .eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK, + .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask, +}; + +/* list of external wakeup controllers supported */ +static const struct of_device_id exynos_wkup_irq_ids[] = { + { .compatible = "samsung,s5pv210-wakeup-eint", + .data = &s5pv210_wkup_irq_chip }, + { .compatible = "samsung,exynos4210-wakeup-eint", + .data = &exynos4210_wkup_irq_chip }, + { .compatible = "samsung,exynos7-wakeup-eint", + .data = &exynos7_wkup_irq_chip }, + { .compatible = "samsung,exynos850-wakeup-eint", + .data = &exynos7_wkup_irq_chip }, + { .compatible = "samsung,exynosautov9-wakeup-eint", + .data = &exynos7_wkup_irq_chip }, + { } +}; + +/* interrupt handler for wakeup interrupts 0..15 */ +static void exynos_irq_eint0_15(struct irq_desc *desc) +{ + struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc); + struct samsung_pin_bank *bank = eintd->bank; + struct irq_chip *chip = irq_desc_get_chip(desc); + + chained_irq_enter(chip, desc); + + generic_handle_domain_irq(bank->irq_domain, eintd->irq); + + chained_irq_exit(chip, desc); +} + +static inline void exynos_irq_demux_eint(unsigned int pend, + struct irq_domain *domain) +{ + unsigned int irq; + + while (pend) { + irq = fls(pend) - 1; + generic_handle_domain_irq(domain, irq); + pend &= ~(1 << irq); + } +} + +/* interrupt handler for wakeup interrupt 16 */ +static void exynos_irq_demux_eint16_31(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc); + unsigned int pend; + unsigned int mask; + int i; + + chained_irq_enter(chip, desc); + + for (i = 0; i < eintd->nr_banks; ++i) { + struct samsung_pin_bank *b = eintd->banks[i]; + pend = readl(b->eint_base + b->irq_chip->eint_pend + + b->eint_offset); + mask = readl(b->eint_base + b->irq_chip->eint_mask + + b->eint_offset); + exynos_irq_demux_eint(pend & ~mask, b->irq_domain); + } + + chained_irq_exit(chip, desc); +} + +/* + * exynos_eint_wkup_init() - setup handling of external wakeup interrupts. + * @d: driver data of samsung pinctrl driver. + */ +__init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) +{ + struct device *dev = d->dev; + struct device_node *wkup_np = NULL; + struct device_node *np; + struct samsung_pin_bank *bank; + struct exynos_weint_data *weint_data; + struct exynos_muxed_weint_data *muxed_data; + const struct exynos_irq_chip *irq_chip; + unsigned int muxed_banks = 0; + unsigned int i; + int idx, irq; + + for_each_child_of_node(dev->of_node, np) { + const struct of_device_id *match; + + match = of_match_node(exynos_wkup_irq_ids, np); + if (match) { + irq_chip = match->data; + wkup_np = np; + break; + } + } + if (!wkup_np) + return -ENODEV; + + bank = d->pin_banks; + for (i = 0; i < d->nr_banks; ++i, ++bank) { + if (bank->eint_type != EINT_TYPE_WKUP) + continue; + + bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip), + GFP_KERNEL); + if (!bank->irq_chip) { + of_node_put(wkup_np); + return -ENOMEM; + } + bank->irq_chip->chip.name = bank->name; + + bank->irq_domain = irq_domain_create_linear(bank->fwnode, + bank->nr_pins, &exynos_eint_irqd_ops, bank); + if (!bank->irq_domain) { + dev_err(dev, "wkup irq domain add failed\n"); + of_node_put(wkup_np); + return -ENXIO; + } + + if (!fwnode_property_present(bank->fwnode, "interrupts")) { + bank->eint_type = EINT_TYPE_WKUP_MUX; + ++muxed_banks; + continue; + } + + weint_data = devm_kcalloc(dev, + bank->nr_pins, sizeof(*weint_data), + GFP_KERNEL); + if (!weint_data) { + of_node_put(wkup_np); + return -ENOMEM; + } + + for (idx = 0; idx < bank->nr_pins; ++idx) { + irq = irq_of_parse_and_map(to_of_node(bank->fwnode), idx); + if (!irq) { + dev_err(dev, "irq number for eint-%s-%d not found\n", + bank->name, idx); + continue; + } + weint_data[idx].irq = idx; + weint_data[idx].bank = bank; + irq_set_chained_handler_and_data(irq, + exynos_irq_eint0_15, + &weint_data[idx]); + } + } + + if (!muxed_banks) { + of_node_put(wkup_np); + return 0; + } + + irq = irq_of_parse_and_map(wkup_np, 0); + of_node_put(wkup_np); + if (!irq) { + dev_err(dev, "irq number for muxed EINTs not found\n"); + return 0; + } + + muxed_data = devm_kzalloc(dev, sizeof(*muxed_data) + + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL); + if (!muxed_data) + return -ENOMEM; + + irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31, + muxed_data); + + bank = d->pin_banks; + idx = 0; + for (i = 0; i < d->nr_banks; ++i, ++bank) { + if (bank->eint_type != EINT_TYPE_WKUP_MUX) + continue; + + muxed_data->banks[idx++] = bank; + } + muxed_data->nr_banks = muxed_banks; + + return 0; +} + +static void exynos_pinctrl_suspend_bank( + struct samsung_pinctrl_drv_data *drvdata, + struct samsung_pin_bank *bank) +{ + struct exynos_eint_gpio_save *save = bank->soc_priv; + void __iomem *regs = bank->eint_base; + + save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset); + save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset); + save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset + 4); + save->eint_mask = readl(regs + bank->irq_chip->eint_mask + + bank->eint_offset); + + pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); + pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); + pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); + pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); +} + +void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) +{ + struct samsung_pin_bank *bank = drvdata->pin_banks; + struct exynos_irq_chip *irq_chip = NULL; + int i; + + for (i = 0; i < drvdata->nr_banks; ++i, ++bank) { + if (bank->eint_type == EINT_TYPE_GPIO) + exynos_pinctrl_suspend_bank(drvdata, bank); + else if (bank->eint_type == EINT_TYPE_WKUP) { + if (!irq_chip) { + irq_chip = bank->irq_chip; + irq_chip->set_eint_wakeup_mask(drvdata, + irq_chip); + } + } + } +} + +static void exynos_pinctrl_resume_bank( + struct samsung_pinctrl_drv_data *drvdata, + struct samsung_pin_bank *bank) +{ + struct exynos_eint_gpio_save *save = bank->soc_priv; + void __iomem *regs = bank->eint_base; + + pr_debug("%s: con %#010x => %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset), save->eint_con); + pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset), save->eint_fltcon0); + pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset + 4), save->eint_fltcon1); + pr_debug("%s: mask %#010x => %#010x\n", bank->name, + readl(regs + bank->irq_chip->eint_mask + + bank->eint_offset), save->eint_mask); + + writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset); + writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset); + writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset + 4); + writel(save->eint_mask, regs + bank->irq_chip->eint_mask + + bank->eint_offset); +} + +void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) +{ + struct samsung_pin_bank *bank = drvdata->pin_banks; + int i; + + for (i = 0; i < drvdata->nr_banks; ++i, ++bank) + if (bank->eint_type == EINT_TYPE_GPIO) + exynos_pinctrl_resume_bank(drvdata, bank); +} + +static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) +{ + if (drvdata->retention_ctrl->refcnt) + atomic_inc(drvdata->retention_ctrl->refcnt); +} + +static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata) +{ + struct samsung_retention_ctrl *ctrl = drvdata->retention_ctrl; + struct regmap *pmu_regs = ctrl->priv; + int i; + + if (ctrl->refcnt && !atomic_dec_and_test(ctrl->refcnt)) + return; + + for (i = 0; i < ctrl->nr_regs; i++) + regmap_write(pmu_regs, ctrl->regs[i], ctrl->value); +} + +struct samsung_retention_ctrl * +exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, + const struct samsung_retention_data *data) +{ + struct samsung_retention_ctrl *ctrl; + struct regmap *pmu_regs; + int i; + + ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return ERR_PTR(-ENOMEM); + + pmu_regs = exynos_get_pmu_regmap(); + if (IS_ERR(pmu_regs)) + return ERR_CAST(pmu_regs); + + ctrl->priv = pmu_regs; + ctrl->regs = data->regs; + ctrl->nr_regs = data->nr_regs; + ctrl->value = data->value; + ctrl->refcnt = data->refcnt; + ctrl->enable = exynos_retention_enable; + ctrl->disable = exynos_retention_disable; + + /* Ensure that retention is disabled on driver init */ + for (i = 0; i < ctrl->nr_regs; i++) + regmap_write(pmu_regs, ctrl->regs[i], ctrl->value); + + return ctrl; +} diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h new file mode 100644 index 0000000000..7bd6d82c9f --- /dev/null +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Exynos specific definitions for Samsung pinctrl and gpiolib driver. + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2012 Linaro Ltd + * http://www.linaro.org + * + * This file contains the Exynos specific definitions for the Samsung + * pinctrl/gpiolib interface drivers. + * + * Author: Thomas Abraham <thomas.ab@samsung.com> + */ + +#ifndef __PINCTRL_SAMSUNG_EXYNOS_H +#define __PINCTRL_SAMSUNG_EXYNOS_H + +/* Values for the pin CON register */ +#define EXYNOS_PIN_CON_FUNC_EINT 0xf + +/* External GPIO and wakeup interrupt related definitions */ +#define EXYNOS_GPIO_ECON_OFFSET 0x700 +#define EXYNOS_GPIO_EFLTCON_OFFSET 0x800 +#define EXYNOS_GPIO_EMASK_OFFSET 0x900 +#define EXYNOS_GPIO_EPEND_OFFSET 0xA00 +#define EXYNOS_WKUP_ECON_OFFSET 0xE00 +#define EXYNOS_WKUP_EMASK_OFFSET 0xF00 +#define EXYNOS_WKUP_EPEND_OFFSET 0xF40 +#define EXYNOS7_WKUP_ECON_OFFSET 0x700 +#define EXYNOS7_WKUP_EMASK_OFFSET 0x900 +#define EXYNOS7_WKUP_EPEND_OFFSET 0xA00 +#define EXYNOS_SVC_OFFSET 0xB08 + +/* helpers to access interrupt service register */ +#define EXYNOS_SVC_GROUP_SHIFT 3 +#define EXYNOS_SVC_GROUP_MASK 0x1f +#define EXYNOS_SVC_NUM_MASK 7 +#define EXYNOS_SVC_GROUP(x) ((x >> EXYNOS_SVC_GROUP_SHIFT) & \ + EXYNOS_SVC_GROUP_MASK) + +/* Exynos specific external interrupt trigger types */ +#define EXYNOS_EINT_LEVEL_LOW 0 +#define EXYNOS_EINT_LEVEL_HIGH 1 +#define EXYNOS_EINT_EDGE_FALLING 2 +#define EXYNOS_EINT_EDGE_RISING 3 +#define EXYNOS_EINT_EDGE_BOTH 4 +#define EXYNOS_EINT_CON_MASK 0xF +#define EXYNOS_EINT_CON_LEN 4 + +#define EXYNOS_EINT_MAX_PER_BANK 8 +#define EXYNOS_EINT_NR_WKUP_EINT + +#define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ + { \ + .type = &bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \ + { \ + .type = &bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_offset = offs, \ + .name = id \ + } + +#define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \ + { \ + .type = &bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = offs, \ + .name = id \ + } + +#define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \ + { \ + .type = &exynos5433_bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_offset = offs, \ + .name = id \ + } + +#define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \ + { \ + .type = &exynos5433_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = offs, \ + .name = id \ + } + +#define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \ + { \ + .type = &exynos5433_bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = offs, \ + .name = id, \ + .pctl_res_idx = pctl_idx, \ + } \ + +#define EXYNOS850_PIN_BANK_EINTN(pins, reg, id) \ + { \ + .type = &exynos850_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define EXYNOS850_PIN_BANK_EINTG(pins, reg, id, offs) \ + { \ + .type = &exynos850_bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_offset = offs, \ + .name = id \ + } + +#define EXYNOS850_PIN_BANK_EINTW(pins, reg, id, offs) \ + { \ + .type = &exynos850_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = offs, \ + .name = id \ + } + +/** + * struct exynos_weint_data: irq specific data for all the wakeup interrupts + * generated by the external wakeup interrupt controller. + * @irq: interrupt number within the domain. + * @bank: bank responsible for this interrupt + */ +struct exynos_weint_data { + unsigned int irq; + struct samsung_pin_bank *bank; +}; + +/** + * struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts + * generated by the external wakeup interrupt controller. + * @nr_banks: count of banks being part of the mux + * @banks: array of banks being part of the mux + */ +struct exynos_muxed_weint_data { + unsigned int nr_banks; + struct samsung_pin_bank *banks[]; +}; + +int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d); +int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d); +void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata); +void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata); +struct samsung_retention_ctrl * +exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, + const struct samsung_retention_data *data); + +#endif /* __PINCTRL_SAMSUNG_EXYNOS_H */ diff --git a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c new file mode 100644 index 0000000000..c5d92db4fd --- /dev/null +++ b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c @@ -0,0 +1,806 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// S3C64xx specific support for pinctrl-samsung driver. +// +// Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> +// +// Based on pinctrl-exynos.c, please see the file for original copyrights. +// +// This file contains the Samsung S3C64xx specific information required by the +// the Samsung pinctrl/gpiolib driver. It also includes the implementation of +// external gpio and wakeup interrupt support. + +#include <linux/init.h> +#include <linux/device.h> +#include <linux/interrupt.h> +#include <linux/irqdomain.h> +#include <linux/irq.h> +#include <linux/of_irq.h> +#include <linux/io.h> +#include <linux/irqchip/chained_irq.h> +#include <linux/slab.h> +#include <linux/err.h> + +#include "pinctrl-samsung.h" + +#define NUM_EINT0 28 +#define NUM_EINT0_IRQ 4 +#define EINT_MAX_PER_REG 16 +#define EINT_MAX_PER_GROUP 16 + +/* External GPIO and wakeup interrupt related definitions */ +#define SVC_GROUP_SHIFT 4 +#define SVC_GROUP_MASK 0xf +#define SVC_NUM_MASK 0xf +#define SVC_GROUP(x) ((x >> SVC_GROUP_SHIFT) & \ + SVC_GROUP_MASK) + +#define EINT12CON_REG 0x200 +#define EINT12MASK_REG 0x240 +#define EINT12PEND_REG 0x260 + +#define EINT_OFFS(i) ((i) % (2 * EINT_MAX_PER_GROUP)) +#define EINT_GROUP(i) ((i) / EINT_MAX_PER_GROUP) +#define EINT_REG(g) (4 * ((g) / 2)) + +#define EINTCON_REG(i) (EINT12CON_REG + EINT_REG(EINT_GROUP(i))) +#define EINTMASK_REG(i) (EINT12MASK_REG + EINT_REG(EINT_GROUP(i))) +#define EINTPEND_REG(i) (EINT12PEND_REG + EINT_REG(EINT_GROUP(i))) + +#define SERVICE_REG 0x284 +#define SERVICEPEND_REG 0x288 + +#define EINT0CON0_REG 0x900 +#define EINT0MASK_REG 0x920 +#define EINT0PEND_REG 0x924 + +/* S3C64xx specific external interrupt trigger types */ +#define EINT_LEVEL_LOW 0 +#define EINT_LEVEL_HIGH 1 +#define EINT_EDGE_FALLING 2 +#define EINT_EDGE_RISING 4 +#define EINT_EDGE_BOTH 6 +#define EINT_CON_MASK 0xF +#define EINT_CON_LEN 4 + +static const struct samsung_pin_bank_type bank_type_4bit_off = { + .fld_width = { 4, 1, 2, 0, 2, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, }, +}; + +static const struct samsung_pin_bank_type bank_type_4bit_alive = { + .fld_width = { 4, 1, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, }, +}; + +static const struct samsung_pin_bank_type bank_type_4bit2_off = { + .fld_width = { 4, 1, 2, 0, 2, 2, }, + .reg_offset = { 0x00, 0x08, 0x0c, 0, 0x10, 0x14, }, +}; + +static const struct samsung_pin_bank_type bank_type_4bit2_alive = { + .fld_width = { 4, 1, 2, }, + .reg_offset = { 0x00, 0x08, 0x0c, }, +}; + +static const struct samsung_pin_bank_type bank_type_2bit_off = { + .fld_width = { 2, 1, 2, 0, 2, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, }, +}; + +static const struct samsung_pin_bank_type bank_type_2bit_alive = { + .fld_width = { 2, 1, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, }, +}; + +#define PIN_BANK_4BIT(pins, reg, id) \ + { \ + .type = &bank_type_4bit_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define PIN_BANK_4BIT_EINTG(pins, reg, id, eoffs) \ + { \ + .type = &bank_type_4bit_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_func = 7, \ + .eint_mask = (1 << (pins)) - 1, \ + .eint_offset = eoffs, \ + .name = id \ + } + +#define PIN_BANK_4BIT_EINTW(pins, reg, id, eoffs, emask) \ + { \ + .type = &bank_type_4bit_alive,\ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_func = 3, \ + .eint_mask = emask, \ + .eint_offset = eoffs, \ + .name = id \ + } + +#define PIN_BANK_4BIT2_EINTG(pins, reg, id, eoffs) \ + { \ + .type = &bank_type_4bit2_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_func = 7, \ + .eint_mask = (1 << (pins)) - 1, \ + .eint_offset = eoffs, \ + .name = id \ + } + +#define PIN_BANK_4BIT2_EINTW(pins, reg, id, eoffs, emask) \ + { \ + .type = &bank_type_4bit2_alive,\ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_func = 3, \ + .eint_mask = emask, \ + .eint_offset = eoffs, \ + .name = id \ + } + +#define PIN_BANK_4BIT2_ALIVE(pins, reg, id) \ + { \ + .type = &bank_type_4bit2_alive,\ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define PIN_BANK_2BIT(pins, reg, id) \ + { \ + .type = &bank_type_2bit_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define PIN_BANK_2BIT_EINTG(pins, reg, id, eoffs, emask) \ + { \ + .type = &bank_type_2bit_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_func = 3, \ + .eint_mask = emask, \ + .eint_offset = eoffs, \ + .name = id \ + } + +#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs) \ + { \ + .type = &bank_type_2bit_alive,\ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_func = 2, \ + .eint_mask = (1 << (pins)) - 1, \ + .eint_offset = eoffs, \ + .name = id \ + } + +/** + * struct s3c64xx_eint0_data - EINT0 common data + * @drvdata: pin controller driver data + * @domains: IRQ domains of particular EINT0 interrupts + * @pins: pin offsets inside of banks of particular EINT0 interrupts + */ +struct s3c64xx_eint0_data { + struct samsung_pinctrl_drv_data *drvdata; + struct irq_domain *domains[NUM_EINT0]; + u8 pins[NUM_EINT0]; +}; + +/** + * struct s3c64xx_eint0_domain_data - EINT0 per-domain data + * @bank: pin bank related to the domain + * @eints: EINT0 interrupts related to the domain + */ +struct s3c64xx_eint0_domain_data { + struct samsung_pin_bank *bank; + u8 eints[]; +}; + +/** + * struct s3c64xx_eint_gpio_data - GPIO EINT data + * @drvdata: pin controller driver data + * @domains: array of domains related to EINT interrupt groups + */ +struct s3c64xx_eint_gpio_data { + struct samsung_pinctrl_drv_data *drvdata; + struct irq_domain *domains[]; +}; + +/* + * Common functions for S3C64xx EINT configuration + */ + +static int s3c64xx_irq_get_trigger(unsigned int type) +{ + int trigger; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + trigger = EINT_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + trigger = EINT_EDGE_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + trigger = EINT_EDGE_BOTH; + break; + case IRQ_TYPE_LEVEL_HIGH: + trigger = EINT_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + trigger = EINT_LEVEL_LOW; + break; + default: + return -EINVAL; + } + + return trigger; +} + +static void s3c64xx_irq_set_handler(struct irq_data *d, unsigned int type) +{ + /* Edge- and level-triggered interrupts need different handlers */ + if (type & IRQ_TYPE_EDGE_BOTH) + irq_set_handler_locked(d, handle_edge_irq); + else + irq_set_handler_locked(d, handle_level_irq); +} + +static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d, + struct samsung_pin_bank *bank, int pin) +{ + const struct samsung_pin_bank_type *bank_type = bank->type; + unsigned long flags; + void __iomem *reg; + u8 shift; + u32 mask; + u32 val; + + /* Make sure that pin is configured as interrupt */ + reg = d->virt_base + bank->pctl_offset; + shift = pin; + if (bank_type->fld_width[PINCFG_TYPE_FUNC] * shift >= 32) { + /* 4-bit bank type with 2 con regs */ + reg += 4; + shift -= 8; + } + + shift = shift * bank_type->fld_width[PINCFG_TYPE_FUNC]; + mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; + + raw_spin_lock_irqsave(&bank->slock, flags); + + val = readl(reg); + val &= ~(mask << shift); + val |= bank->eint_func << shift; + writel(val, reg); + + raw_spin_unlock_irqrestore(&bank->slock, flags); +} + +/* + * Functions for EINT GPIO configuration (EINT groups 1-9) + */ + +static inline void s3c64xx_gpio_irq_set_mask(struct irq_data *irqd, bool mask) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; + void __iomem *reg = d->virt_base + EINTMASK_REG(bank->eint_offset); + u32 val; + + val = readl(reg); + if (mask) + val |= 1 << index; + else + val &= ~(1 << index); + writel(val, reg); +} + +static void s3c64xx_gpio_irq_unmask(struct irq_data *irqd) +{ + s3c64xx_gpio_irq_set_mask(irqd, false); +} + +static void s3c64xx_gpio_irq_mask(struct irq_data *irqd) +{ + s3c64xx_gpio_irq_set_mask(irqd, true); +} + +static void s3c64xx_gpio_irq_ack(struct irq_data *irqd) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; + void __iomem *reg = d->virt_base + EINTPEND_REG(bank->eint_offset); + + writel(1 << index, reg); +} + +static int s3c64xx_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + void __iomem *reg; + int trigger; + u8 shift; + u32 val; + + trigger = s3c64xx_irq_get_trigger(type); + if (trigger < 0) { + pr_err("unsupported external interrupt type\n"); + return -EINVAL; + } + + s3c64xx_irq_set_handler(irqd, type); + + /* Set up interrupt trigger */ + reg = d->virt_base + EINTCON_REG(bank->eint_offset); + shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq; + shift = 4 * (shift / 4); /* 4 EINTs per trigger selector */ + + val = readl(reg); + val &= ~(EINT_CON_MASK << shift); + val |= trigger << shift; + writel(val, reg); + + s3c64xx_irq_set_function(d, bank, irqd->hwirq); + + return 0; +} + +/* + * irq_chip for gpio interrupts. + */ +static struct irq_chip s3c64xx_gpio_irq_chip = { + .name = "GPIO", + .irq_unmask = s3c64xx_gpio_irq_unmask, + .irq_mask = s3c64xx_gpio_irq_mask, + .irq_ack = s3c64xx_gpio_irq_ack, + .irq_set_type = s3c64xx_gpio_irq_set_type, +}; + +static int s3c64xx_gpio_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct samsung_pin_bank *bank = h->host_data; + + if (!(bank->eint_mask & (1 << hw))) + return -EINVAL; + + irq_set_chip_and_handler(virq, + &s3c64xx_gpio_irq_chip, handle_level_irq); + irq_set_chip_data(virq, bank); + + return 0; +} + +/* + * irq domain callbacks for external gpio interrupt controller. + */ +static const struct irq_domain_ops s3c64xx_gpio_irqd_ops = { + .map = s3c64xx_gpio_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +static void s3c64xx_eint_gpio_irq(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct s3c64xx_eint_gpio_data *data = irq_desc_get_handler_data(desc); + struct samsung_pinctrl_drv_data *drvdata = data->drvdata; + + chained_irq_enter(chip, desc); + + do { + unsigned int svc; + unsigned int group; + unsigned int pin; + int ret; + + svc = readl(drvdata->virt_base + SERVICE_REG); + group = SVC_GROUP(svc); + pin = svc & SVC_NUM_MASK; + + if (!group) + break; + + /* Group 1 is used for two pin banks */ + if (group == 1) { + if (pin < 8) + group = 0; + else + pin -= 8; + } + + ret = generic_handle_domain_irq(data->domains[group], pin); + /* + * Something must be really wrong if an unmapped EINT + * was unmasked... + */ + BUG_ON(ret); + } while (1); + + chained_irq_exit(chip, desc); +} + +/** + * s3c64xx_eint_gpio_init() - setup handling of external gpio interrupts. + * @d: driver data of samsung pinctrl driver. + */ +static int s3c64xx_eint_gpio_init(struct samsung_pinctrl_drv_data *d) +{ + struct s3c64xx_eint_gpio_data *data; + struct samsung_pin_bank *bank; + struct device *dev = d->dev; + unsigned int nr_domains; + unsigned int i; + + if (!d->irq) { + dev_err(dev, "irq number not available\n"); + return -EINVAL; + } + + nr_domains = 0; + bank = d->pin_banks; + for (i = 0; i < d->nr_banks; ++i, ++bank) { + unsigned int nr_eints; + unsigned int mask; + + if (bank->eint_type != EINT_TYPE_GPIO) + continue; + + mask = bank->eint_mask; + nr_eints = fls(mask); + + bank->irq_domain = irq_domain_create_linear(bank->fwnode, + nr_eints, &s3c64xx_gpio_irqd_ops, bank); + if (!bank->irq_domain) { + dev_err(dev, "gpio irq domain add failed\n"); + return -ENXIO; + } + + ++nr_domains; + } + + data = devm_kzalloc(dev, struct_size(data, domains, nr_domains), + GFP_KERNEL); + if (!data) + return -ENOMEM; + data->drvdata = d; + + bank = d->pin_banks; + nr_domains = 0; + for (i = 0; i < d->nr_banks; ++i, ++bank) { + if (bank->eint_type != EINT_TYPE_GPIO) + continue; + + data->domains[nr_domains++] = bank->irq_domain; + } + + irq_set_chained_handler_and_data(d->irq, s3c64xx_eint_gpio_irq, data); + + return 0; +} + +/* + * Functions for configuration of EINT0 wake-up interrupts + */ + +static inline void s3c64xx_eint0_irq_set_mask(struct irq_data *irqd, bool mask) +{ + struct s3c64xx_eint0_domain_data *ddata = + irq_data_get_irq_chip_data(irqd); + struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata; + u32 val; + + val = readl(d->virt_base + EINT0MASK_REG); + if (mask) + val |= 1 << ddata->eints[irqd->hwirq]; + else + val &= ~(1 << ddata->eints[irqd->hwirq]); + writel(val, d->virt_base + EINT0MASK_REG); +} + +static void s3c64xx_eint0_irq_unmask(struct irq_data *irqd) +{ + s3c64xx_eint0_irq_set_mask(irqd, false); +} + +static void s3c64xx_eint0_irq_mask(struct irq_data *irqd) +{ + s3c64xx_eint0_irq_set_mask(irqd, true); +} + +static void s3c64xx_eint0_irq_ack(struct irq_data *irqd) +{ + struct s3c64xx_eint0_domain_data *ddata = + irq_data_get_irq_chip_data(irqd); + struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata; + + writel(1 << ddata->eints[irqd->hwirq], + d->virt_base + EINT0PEND_REG); +} + +static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type) +{ + struct s3c64xx_eint0_domain_data *ddata = + irq_data_get_irq_chip_data(irqd); + struct samsung_pin_bank *bank = ddata->bank; + struct samsung_pinctrl_drv_data *d = bank->drvdata; + void __iomem *reg; + int trigger; + u8 shift; + u32 val; + + trigger = s3c64xx_irq_get_trigger(type); + if (trigger < 0) { + pr_err("unsupported external interrupt type\n"); + return -EINVAL; + } + + s3c64xx_irq_set_handler(irqd, type); + + /* Set up interrupt trigger */ + reg = d->virt_base + EINT0CON0_REG; + shift = ddata->eints[irqd->hwirq]; + if (shift >= EINT_MAX_PER_REG) { + reg += 4; + shift -= EINT_MAX_PER_REG; + } + shift = EINT_CON_LEN * (shift / 2); + + val = readl(reg); + val &= ~(EINT_CON_MASK << shift); + val |= trigger << shift; + writel(val, reg); + + s3c64xx_irq_set_function(d, bank, irqd->hwirq); + + return 0; +} + +/* + * irq_chip for wakeup interrupts + */ +static struct irq_chip s3c64xx_eint0_irq_chip = { + .name = "EINT0", + .irq_unmask = s3c64xx_eint0_irq_unmask, + .irq_mask = s3c64xx_eint0_irq_mask, + .irq_ack = s3c64xx_eint0_irq_ack, + .irq_set_type = s3c64xx_eint0_irq_set_type, +}; + +static inline void s3c64xx_irq_demux_eint(struct irq_desc *desc, u32 range) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct s3c64xx_eint0_data *data = irq_desc_get_handler_data(desc); + struct samsung_pinctrl_drv_data *drvdata = data->drvdata; + unsigned int pend, mask; + + chained_irq_enter(chip, desc); + + pend = readl(drvdata->virt_base + EINT0PEND_REG); + mask = readl(drvdata->virt_base + EINT0MASK_REG); + + pend = pend & range & ~mask; + pend &= range; + + while (pend) { + unsigned int irq; + int ret; + + irq = fls(pend) - 1; + pend &= ~(1 << irq); + ret = generic_handle_domain_irq(data->domains[irq], data->pins[irq]); + /* + * Something must be really wrong if an unmapped EINT + * was unmasked... + */ + BUG_ON(ret); + } + + chained_irq_exit(chip, desc); +} + +static void s3c64xx_demux_eint0_3(struct irq_desc *desc) +{ + s3c64xx_irq_demux_eint(desc, 0xf); +} + +static void s3c64xx_demux_eint4_11(struct irq_desc *desc) +{ + s3c64xx_irq_demux_eint(desc, 0xff0); +} + +static void s3c64xx_demux_eint12_19(struct irq_desc *desc) +{ + s3c64xx_irq_demux_eint(desc, 0xff000); +} + +static void s3c64xx_demux_eint20_27(struct irq_desc *desc) +{ + s3c64xx_irq_demux_eint(desc, 0xff00000); +} + +static irq_flow_handler_t s3c64xx_eint0_handlers[NUM_EINT0_IRQ] = { + s3c64xx_demux_eint0_3, + s3c64xx_demux_eint4_11, + s3c64xx_demux_eint12_19, + s3c64xx_demux_eint20_27, +}; + +static int s3c64xx_eint0_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct s3c64xx_eint0_domain_data *ddata = h->host_data; + struct samsung_pin_bank *bank = ddata->bank; + + if (!(bank->eint_mask & (1 << hw))) + return -EINVAL; + + irq_set_chip_and_handler(virq, + &s3c64xx_eint0_irq_chip, handle_level_irq); + irq_set_chip_data(virq, ddata); + + return 0; +} + +/* + * irq domain callbacks for external wakeup interrupt controller. + */ +static const struct irq_domain_ops s3c64xx_eint0_irqd_ops = { + .map = s3c64xx_eint0_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +/* list of external wakeup controllers supported */ +static const struct of_device_id s3c64xx_eint0_irq_ids[] = { + { .compatible = "samsung,s3c64xx-wakeup-eint", }, + { } +}; + +/** + * s3c64xx_eint_eint0_init() - setup handling of external wakeup interrupts. + * @d: driver data of samsung pinctrl driver. + */ +static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d) +{ + struct device *dev = d->dev; + struct device_node *eint0_np = NULL; + struct device_node *np; + struct samsung_pin_bank *bank; + struct s3c64xx_eint0_data *data; + unsigned int i; + + for_each_child_of_node(dev->of_node, np) { + if (of_match_node(s3c64xx_eint0_irq_ids, np)) { + eint0_np = np; + break; + } + } + if (!eint0_np) + return -ENODEV; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) { + of_node_put(eint0_np); + return -ENOMEM; + } + data->drvdata = d; + + for (i = 0; i < NUM_EINT0_IRQ; ++i) { + unsigned int irq; + + irq = irq_of_parse_and_map(eint0_np, i); + if (!irq) { + dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i); + of_node_put(eint0_np); + return -ENXIO; + } + + irq_set_chained_handler_and_data(irq, + s3c64xx_eint0_handlers[i], + data); + } + of_node_put(eint0_np); + + bank = d->pin_banks; + for (i = 0; i < d->nr_banks; ++i, ++bank) { + struct s3c64xx_eint0_domain_data *ddata; + unsigned int nr_eints; + unsigned int mask; + unsigned int irq; + unsigned int pin; + + if (bank->eint_type != EINT_TYPE_WKUP) + continue; + + mask = bank->eint_mask; + nr_eints = fls(mask); + + ddata = devm_kzalloc(dev, + sizeof(*ddata) + nr_eints, GFP_KERNEL); + if (!ddata) + return -ENOMEM; + ddata->bank = bank; + + bank->irq_domain = irq_domain_create_linear(bank->fwnode, + nr_eints, &s3c64xx_eint0_irqd_ops, ddata); + if (!bank->irq_domain) { + dev_err(dev, "wkup irq domain add failed\n"); + return -ENXIO; + } + + irq = bank->eint_offset; + mask = bank->eint_mask; + for (pin = 0; mask; ++pin, mask >>= 1) { + if (!(mask & 1)) + continue; + data->domains[irq] = bank->irq_domain; + data->pins[irq] = pin; + ddata->eints[pin] = irq; + ++irq; + } + } + + return 0; +} + +/* pin banks of s3c64xx pin-controller 0 */ +static const struct samsung_pin_bank_data s3c64xx_pin_banks0[] __initconst = { + PIN_BANK_4BIT_EINTG(8, 0x000, "gpa", 0), + PIN_BANK_4BIT_EINTG(7, 0x020, "gpb", 8), + PIN_BANK_4BIT_EINTG(8, 0x040, "gpc", 16), + PIN_BANK_4BIT_EINTG(5, 0x060, "gpd", 32), + PIN_BANK_4BIT(5, 0x080, "gpe"), + PIN_BANK_2BIT_EINTG(16, 0x0a0, "gpf", 48, 0x3fff), + PIN_BANK_4BIT_EINTG(7, 0x0c0, "gpg", 64), + PIN_BANK_4BIT2_EINTG(10, 0x0e0, "gph", 80), + PIN_BANK_2BIT(16, 0x100, "gpi"), + PIN_BANK_2BIT(12, 0x120, "gpj"), + PIN_BANK_4BIT2_ALIVE(16, 0x800, "gpk"), + PIN_BANK_4BIT2_EINTW(15, 0x810, "gpl", 16, 0x7f00), + PIN_BANK_4BIT_EINTW(6, 0x820, "gpm", 23, 0x1f), + PIN_BANK_2BIT_EINTW(16, 0x830, "gpn", 0), + PIN_BANK_2BIT_EINTG(16, 0x140, "gpo", 96, 0xffff), + PIN_BANK_2BIT_EINTG(15, 0x160, "gpp", 112, 0x7fff), + PIN_BANK_2BIT_EINTG(9, 0x180, "gpq", 128, 0x1ff), +}; + +/* + * Samsung pinctrl driver data for S3C64xx SoC. S3C64xx SoC includes + * one gpio/pin-mux/pinconfig controller. + */ +static const struct samsung_pin_ctrl s3c64xx_pin_ctrl[] __initconst = { + { + /* pin-controller instance 1 data */ + .pin_banks = s3c64xx_pin_banks0, + .nr_banks = ARRAY_SIZE(s3c64xx_pin_banks0), + .eint_gpio_init = s3c64xx_eint_gpio_init, + .eint_wkup_init = s3c64xx_eint_eint0_init, + }, +}; + +const struct samsung_pinctrl_of_match_data s3c64xx_of_data __initconst = { + .ctrl = s3c64xx_pin_ctrl, + .num_ctrl = ARRAY_SIZE(s3c64xx_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c new file mode 100644 index 0000000000..e54847040b --- /dev/null +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -0,0 +1,1349 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's. +// +// Copyright (c) 2012 Samsung Electronics Co., Ltd. +// http://www.samsung.com +// Copyright (c) 2012 Linaro Ltd +// http://www.linaro.org +// +// Author: Thomas Abraham <thomas.ab@samsung.com> +// +// This driver implements the Samsung pinctrl driver. It supports setting up of +// pinmux and pinconf configurations. The gpiolib interface is also included. +// External interrupt (gpio and wakeup) support are not included in this driver +// but provides extensions to which platform specific implementation of the gpio +// and wakeup interrupts can be hooked to. + +#include <linux/err.h> +#include <linux/gpio/driver.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/irqdomain.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/property.h> +#include <linux/seq_file.h> +#include <linux/slab.h> +#include <linux/spinlock.h> + +#include "../core.h" +#include "pinctrl-samsung.h" + +/* maximum number of the memory resources */ +#define SAMSUNG_PINCTRL_NUM_RESOURCES 2 + +/* list of all possible config options supported */ +static struct pin_config { + const char *property; + enum pincfg_type param; +} cfg_params[] = { + { "samsung,pin-pud", PINCFG_TYPE_PUD }, + { "samsung,pin-drv", PINCFG_TYPE_DRV }, + { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN }, + { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN }, + { "samsung,pin-val", PINCFG_TYPE_DAT }, +}; + +static unsigned int pin_base; + +static int samsung_get_group_count(struct pinctrl_dev *pctldev) +{ + struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->nr_groups; +} + +static const char *samsung_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->pin_groups[group].name; +} + +static int samsung_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev); + + *pins = pmx->pin_groups[group].pins; + *num_pins = pmx->pin_groups[group].num_pins; + + return 0; +} + +static int reserve_map(struct device *dev, struct pinctrl_map **map, + unsigned *reserved_maps, unsigned *num_maps, + unsigned reserve) +{ + unsigned old_num = *reserved_maps; + unsigned new_num = *num_maps + reserve; + struct pinctrl_map *new_map; + + if (old_num >= new_num) + return 0; + + new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); + if (!new_map) + return -ENOMEM; + + memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); + + *map = new_map; + *reserved_maps = new_num; + + return 0; +} + +static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, + unsigned *num_maps, const char *group, + const char *function) +{ + if (WARN_ON(*num_maps == *reserved_maps)) + return -ENOSPC; + + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.group = group; + (*map)[*num_maps].data.mux.function = function; + (*num_maps)++; + + return 0; +} + +static int add_map_configs(struct device *dev, struct pinctrl_map **map, + unsigned *reserved_maps, unsigned *num_maps, + const char *group, unsigned long *configs, + unsigned num_configs) +{ + unsigned long *dup_configs; + + if (WARN_ON(*num_maps == *reserved_maps)) + return -ENOSPC; + + dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), + GFP_KERNEL); + if (!dup_configs) + return -ENOMEM; + + (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP; + (*map)[*num_maps].data.configs.group_or_pin = group; + (*map)[*num_maps].data.configs.configs = dup_configs; + (*map)[*num_maps].data.configs.num_configs = num_configs; + (*num_maps)++; + + return 0; +} + +static int add_config(struct device *dev, unsigned long **configs, + unsigned *num_configs, unsigned long config) +{ + unsigned old_num = *num_configs; + unsigned new_num = old_num + 1; + unsigned long *new_configs; + + new_configs = krealloc(*configs, sizeof(*new_configs) * new_num, + GFP_KERNEL); + if (!new_configs) + return -ENOMEM; + + new_configs[old_num] = config; + + *configs = new_configs; + *num_configs = new_num; + + return 0; +} + +static void samsung_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, + unsigned num_maps) +{ + int i; + + for (i = 0; i < num_maps; i++) + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) + kfree(map[i].data.configs.configs); + + kfree(map); +} + +static int samsung_dt_subnode_to_map(struct samsung_pinctrl_drv_data *drvdata, + struct device *dev, + struct device_node *np, + struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps) +{ + int ret, i; + u32 val; + unsigned long config; + unsigned long *configs = NULL; + unsigned num_configs = 0; + unsigned reserve; + struct property *prop; + const char *group; + bool has_func = false; + + ret = of_property_read_u32(np, "samsung,pin-function", &val); + if (!ret) + has_func = true; + + for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { + ret = of_property_read_u32(np, cfg_params[i].property, &val); + if (!ret) { + config = PINCFG_PACK(cfg_params[i].param, val); + ret = add_config(dev, &configs, &num_configs, config); + if (ret < 0) + goto exit; + /* EINVAL=missing, which is fine since it's optional */ + } else if (ret != -EINVAL) { + dev_err(dev, "could not parse property %s\n", + cfg_params[i].property); + } + } + + reserve = 0; + if (has_func) + reserve++; + if (num_configs) + reserve++; + ret = of_property_count_strings(np, "samsung,pins"); + if (ret < 0) { + dev_err(dev, "could not parse property samsung,pins\n"); + goto exit; + } + reserve *= ret; + + ret = reserve_map(dev, map, reserved_maps, num_maps, reserve); + if (ret < 0) + goto exit; + + of_property_for_each_string(np, "samsung,pins", prop, group) { + if (has_func) { + ret = add_map_mux(map, reserved_maps, + num_maps, group, np->full_name); + if (ret < 0) + goto exit; + } + + if (num_configs) { + ret = add_map_configs(dev, map, reserved_maps, + num_maps, group, configs, + num_configs); + if (ret < 0) + goto exit; + } + } + + ret = 0; + +exit: + kfree(configs); + return ret; +} + +static int samsung_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + unsigned *num_maps) +{ + struct samsung_pinctrl_drv_data *drvdata; + unsigned reserved_maps; + struct device_node *np; + int ret; + + drvdata = pinctrl_dev_get_drvdata(pctldev); + + reserved_maps = 0; + *map = NULL; + *num_maps = 0; + + if (!of_get_child_count(np_config)) + return samsung_dt_subnode_to_map(drvdata, pctldev->dev, + np_config, map, + &reserved_maps, + num_maps); + + for_each_child_of_node(np_config, np) { + ret = samsung_dt_subnode_to_map(drvdata, pctldev->dev, np, map, + &reserved_maps, num_maps); + if (ret < 0) { + samsung_dt_free_map(pctldev, *map, *num_maps); + of_node_put(np); + return ret; + } + } + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +/* Forward declaration which can be used by samsung_pin_dbg_show */ +static int samsung_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config); +static const char * const reg_names[] = {"CON", "DAT", "PUD", "DRV", "CON_PDN", + "PUD_PDN"}; + +static void samsung_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + enum pincfg_type cfg_type; + unsigned long config; + int ret; + + for (cfg_type = 0; cfg_type < PINCFG_TYPE_NUM; cfg_type++) { + config = PINCFG_PACK(cfg_type, 0); + ret = samsung_pinconf_get(pctldev, pin, &config); + if (ret < 0) + continue; + + seq_printf(s, " %s(0x%lx)", reg_names[cfg_type], + PINCFG_UNPACK_VALUE(config)); + } +} +#endif + +/* list of pinctrl callbacks for the pinctrl core */ +static const struct pinctrl_ops samsung_pctrl_ops = { + .get_groups_count = samsung_get_group_count, + .get_group_name = samsung_get_group_name, + .get_group_pins = samsung_get_group_pins, + .dt_node_to_map = samsung_dt_node_to_map, + .dt_free_map = samsung_dt_free_map, +#ifdef CONFIG_DEBUG_FS + .pin_dbg_show = samsung_pin_dbg_show, +#endif +}; + +/* check if the selector is a valid pin function selector */ +static int samsung_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct samsung_pinctrl_drv_data *drvdata; + + drvdata = pinctrl_dev_get_drvdata(pctldev); + return drvdata->nr_functions; +} + +/* return the name of the pin function specified */ +static const char *samsung_pinmux_get_fname(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct samsung_pinctrl_drv_data *drvdata; + + drvdata = pinctrl_dev_get_drvdata(pctldev); + return drvdata->pmx_functions[selector].name; +} + +/* return the groups associated for the specified function selector */ +static int samsung_pinmux_get_groups(struct pinctrl_dev *pctldev, + unsigned selector, const char * const **groups, + unsigned * const num_groups) +{ + struct samsung_pinctrl_drv_data *drvdata; + + drvdata = pinctrl_dev_get_drvdata(pctldev); + *groups = drvdata->pmx_functions[selector].groups; + *num_groups = drvdata->pmx_functions[selector].num_groups; + return 0; +} + +/* + * given a pin number that is local to a pin controller, find out the pin bank + * and the register base of the pin bank. + */ +static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata, + unsigned pin, void __iomem **reg, u32 *offset, + struct samsung_pin_bank **bank) +{ + struct samsung_pin_bank *b; + + b = drvdata->pin_banks; + + while ((pin >= b->pin_base) && + ((b->pin_base + b->nr_pins - 1) < pin)) + b++; + + *reg = b->pctl_base + b->pctl_offset; + *offset = pin - b->pin_base; + if (bank) + *bank = b; +} + +/* enable or disable a pinmux function */ +static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) +{ + struct samsung_pinctrl_drv_data *drvdata; + const struct samsung_pin_bank_type *type; + struct samsung_pin_bank *bank; + void __iomem *reg; + u32 mask, shift, data, pin_offset; + unsigned long flags; + const struct samsung_pmx_func *func; + const struct samsung_pin_group *grp; + + drvdata = pinctrl_dev_get_drvdata(pctldev); + func = &drvdata->pmx_functions[selector]; + grp = &drvdata->pin_groups[group]; + + pin_to_reg_bank(drvdata, grp->pins[0] - drvdata->pin_base, + ®, &pin_offset, &bank); + type = bank->type; + mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1; + shift = pin_offset * type->fld_width[PINCFG_TYPE_FUNC]; + if (shift >= 32) { + /* Some banks have two config registers */ + shift -= 32; + reg += 4; + } + + raw_spin_lock_irqsave(&bank->slock, flags); + + data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]); + data &= ~(mask << shift); + data |= func->val << shift; + writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]); + + raw_spin_unlock_irqrestore(&bank->slock, flags); +} + +/* enable a specified pinmux by writing to registers */ +static int samsung_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned selector, + unsigned group) +{ + samsung_pinmux_setup(pctldev, selector, group); + return 0; +} + +/* list of pinmux callbacks for the pinmux vertical in pinctrl core */ +static const struct pinmux_ops samsung_pinmux_ops = { + .get_functions_count = samsung_get_functions_count, + .get_function_name = samsung_pinmux_get_fname, + .get_function_groups = samsung_pinmux_get_groups, + .set_mux = samsung_pinmux_set_mux, +}; + +/* set or get the pin config settings for a specified pin */ +static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config, bool set) +{ + struct samsung_pinctrl_drv_data *drvdata; + const struct samsung_pin_bank_type *type; + struct samsung_pin_bank *bank; + void __iomem *reg_base; + enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config); + u32 data, width, pin_offset, mask, shift; + u32 cfg_value, cfg_reg; + unsigned long flags; + + drvdata = pinctrl_dev_get_drvdata(pctldev); + pin_to_reg_bank(drvdata, pin - drvdata->pin_base, ®_base, + &pin_offset, &bank); + type = bank->type; + + if (cfg_type >= PINCFG_TYPE_NUM || !type->fld_width[cfg_type]) + return -EINVAL; + + width = type->fld_width[cfg_type]; + cfg_reg = type->reg_offset[cfg_type]; + + raw_spin_lock_irqsave(&bank->slock, flags); + + mask = (1 << width) - 1; + shift = pin_offset * width; + data = readl(reg_base + cfg_reg); + + if (set) { + cfg_value = PINCFG_UNPACK_VALUE(*config); + data &= ~(mask << shift); + data |= (cfg_value << shift); + writel(data, reg_base + cfg_reg); + } else { + data >>= shift; + data &= mask; + *config = PINCFG_PACK(cfg_type, data); + } + + raw_spin_unlock_irqrestore(&bank->slock, flags); + + return 0; +} + +/* set the pin config settings for a specified pin */ +static int samsung_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned num_configs) +{ + int i, ret; + + for (i = 0; i < num_configs; i++) { + ret = samsung_pinconf_rw(pctldev, pin, &configs[i], true); + if (ret < 0) + return ret; + } /* for each config */ + + return 0; +} + +/* get the pin config settings for a specified pin */ +static int samsung_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + return samsung_pinconf_rw(pctldev, pin, config, false); +} + +/* set the pin config settings for a specified pin group */ +static int samsung_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned group, unsigned long *configs, + unsigned num_configs) +{ + struct samsung_pinctrl_drv_data *drvdata; + const unsigned int *pins; + unsigned int cnt; + + drvdata = pinctrl_dev_get_drvdata(pctldev); + pins = drvdata->pin_groups[group].pins; + + for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++) + samsung_pinconf_set(pctldev, pins[cnt], configs, num_configs); + + return 0; +} + +/* get the pin config settings for a specified pin group */ +static int samsung_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int group, unsigned long *config) +{ + struct samsung_pinctrl_drv_data *drvdata; + const unsigned int *pins; + + drvdata = pinctrl_dev_get_drvdata(pctldev); + pins = drvdata->pin_groups[group].pins; + samsung_pinconf_get(pctldev, pins[0], config); + return 0; +} + +/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */ +static const struct pinconf_ops samsung_pinconf_ops = { + .pin_config_get = samsung_pinconf_get, + .pin_config_set = samsung_pinconf_set, + .pin_config_group_get = samsung_pinconf_group_get, + .pin_config_group_set = samsung_pinconf_group_set, +}; + +/* + * The samsung_gpio_set_vlaue() should be called with "bank->slock" held + * to avoid race condition. + */ +static void samsung_gpio_set_value(struct gpio_chip *gc, + unsigned offset, int value) +{ + struct samsung_pin_bank *bank = gpiochip_get_data(gc); + const struct samsung_pin_bank_type *type = bank->type; + void __iomem *reg; + u32 data; + + reg = bank->pctl_base + bank->pctl_offset; + + data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]); + data &= ~(1 << offset); + if (value) + data |= 1 << offset; + writel(data, reg + type->reg_offset[PINCFG_TYPE_DAT]); +} + +/* gpiolib gpio_set callback function */ +static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value) +{ + struct samsung_pin_bank *bank = gpiochip_get_data(gc); + unsigned long flags; + + raw_spin_lock_irqsave(&bank->slock, flags); + samsung_gpio_set_value(gc, offset, value); + raw_spin_unlock_irqrestore(&bank->slock, flags); +} + +/* gpiolib gpio_get callback function */ +static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset) +{ + void __iomem *reg; + u32 data; + struct samsung_pin_bank *bank = gpiochip_get_data(gc); + const struct samsung_pin_bank_type *type = bank->type; + + reg = bank->pctl_base + bank->pctl_offset; + + data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]); + data >>= offset; + data &= 1; + return data; +} + +/* + * The samsung_gpio_set_direction() should be called with "bank->slock" held + * to avoid race condition. + * The calls to gpio_direction_output() and gpio_direction_input() + * leads to this function call. + */ +static int samsung_gpio_set_direction(struct gpio_chip *gc, + unsigned offset, bool input) +{ + const struct samsung_pin_bank_type *type; + struct samsung_pin_bank *bank; + void __iomem *reg; + u32 data, mask, shift; + + bank = gpiochip_get_data(gc); + type = bank->type; + + reg = bank->pctl_base + bank->pctl_offset + + type->reg_offset[PINCFG_TYPE_FUNC]; + + mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1; + shift = offset * type->fld_width[PINCFG_TYPE_FUNC]; + if (shift >= 32) { + /* Some banks have two config registers */ + shift -= 32; + reg += 4; + } + + data = readl(reg); + data &= ~(mask << shift); + if (!input) + data |= PIN_CON_FUNC_OUTPUT << shift; + writel(data, reg); + + return 0; +} + +/* gpiolib gpio_direction_input callback function. */ +static int samsung_gpio_direction_input(struct gpio_chip *gc, unsigned offset) +{ + struct samsung_pin_bank *bank = gpiochip_get_data(gc); + unsigned long flags; + int ret; + + raw_spin_lock_irqsave(&bank->slock, flags); + ret = samsung_gpio_set_direction(gc, offset, true); + raw_spin_unlock_irqrestore(&bank->slock, flags); + return ret; +} + +/* gpiolib gpio_direction_output callback function. */ +static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset, + int value) +{ + struct samsung_pin_bank *bank = gpiochip_get_data(gc); + unsigned long flags; + int ret; + + raw_spin_lock_irqsave(&bank->slock, flags); + samsung_gpio_set_value(gc, offset, value); + ret = samsung_gpio_set_direction(gc, offset, false); + raw_spin_unlock_irqrestore(&bank->slock, flags); + + return ret; +} + +/* + * gpiod_to_irq() callback function. Creates a mapping between a GPIO pin + * and a virtual IRQ, if not already present. + */ +static int samsung_gpio_to_irq(struct gpio_chip *gc, unsigned offset) +{ + struct samsung_pin_bank *bank = gpiochip_get_data(gc); + unsigned int virq; + + if (!bank->irq_domain) + return -ENXIO; + + virq = irq_create_mapping(bank->irq_domain, offset); + + return (virq) ? : -ENXIO; +} + +static struct samsung_pin_group *samsung_pinctrl_create_groups( + struct device *dev, + struct samsung_pinctrl_drv_data *drvdata, + unsigned int *cnt) +{ + struct pinctrl_desc *ctrldesc = &drvdata->pctl; + struct samsung_pin_group *groups, *grp; + const struct pinctrl_pin_desc *pdesc; + int i; + + groups = devm_kcalloc(dev, ctrldesc->npins, sizeof(*groups), + GFP_KERNEL); + if (!groups) + return ERR_PTR(-EINVAL); + grp = groups; + + pdesc = ctrldesc->pins; + for (i = 0; i < ctrldesc->npins; ++i, ++pdesc, ++grp) { + grp->name = pdesc->name; + grp->pins = &pdesc->number; + grp->num_pins = 1; + } + + *cnt = ctrldesc->npins; + return groups; +} + +static int samsung_pinctrl_create_function(struct device *dev, + struct samsung_pinctrl_drv_data *drvdata, + struct device_node *func_np, + struct samsung_pmx_func *func) +{ + int npins; + int ret; + int i; + + if (of_property_read_u32(func_np, "samsung,pin-function", &func->val)) + return 0; + + npins = of_property_count_strings(func_np, "samsung,pins"); + if (npins < 1) { + dev_err(dev, "invalid pin list in %pOFn node", func_np); + return -EINVAL; + } + + func->name = func_np->full_name; + + func->groups = devm_kcalloc(dev, npins, sizeof(char *), GFP_KERNEL); + if (!func->groups) + return -ENOMEM; + + for (i = 0; i < npins; ++i) { + const char *gname; + + ret = of_property_read_string_index(func_np, "samsung,pins", + i, &gname); + if (ret) { + dev_err(dev, + "failed to read pin name %d from %pOFn node\n", + i, func_np); + return ret; + } + + func->groups[i] = gname; + } + + func->num_groups = npins; + return 1; +} + +static struct samsung_pmx_func *samsung_pinctrl_create_functions( + struct device *dev, + struct samsung_pinctrl_drv_data *drvdata, + unsigned int *cnt) +{ + struct samsung_pmx_func *functions, *func; + struct device_node *dev_np = dev->of_node; + struct device_node *cfg_np; + unsigned int func_cnt = 0; + int ret; + + /* + * Iterate over all the child nodes of the pin controller node + * and create pin groups and pin function lists. + */ + for_each_child_of_node(dev_np, cfg_np) { + struct device_node *func_np; + + if (!of_get_child_count(cfg_np)) { + if (!of_find_property(cfg_np, + "samsung,pin-function", NULL)) + continue; + ++func_cnt; + continue; + } + + for_each_child_of_node(cfg_np, func_np) { + if (!of_find_property(func_np, + "samsung,pin-function", NULL)) + continue; + ++func_cnt; + } + } + + functions = devm_kcalloc(dev, func_cnt, sizeof(*functions), + GFP_KERNEL); + if (!functions) + return ERR_PTR(-ENOMEM); + func = functions; + + /* + * Iterate over all the child nodes of the pin controller node + * and create pin groups and pin function lists. + */ + func_cnt = 0; + for_each_child_of_node(dev_np, cfg_np) { + struct device_node *func_np; + + if (!of_get_child_count(cfg_np)) { + ret = samsung_pinctrl_create_function(dev, drvdata, + cfg_np, func); + if (ret < 0) { + of_node_put(cfg_np); + return ERR_PTR(ret); + } + if (ret > 0) { + ++func; + ++func_cnt; + } + continue; + } + + for_each_child_of_node(cfg_np, func_np) { + ret = samsung_pinctrl_create_function(dev, drvdata, + func_np, func); + if (ret < 0) { + of_node_put(func_np); + of_node_put(cfg_np); + return ERR_PTR(ret); + } + if (ret > 0) { + ++func; + ++func_cnt; + } + } + } + + *cnt = func_cnt; + return functions; +} + +/* + * Parse the information about all the available pin groups and pin functions + * from device node of the pin-controller. A pin group is formed with all + * the pins listed in the "samsung,pins" property. + */ + +static int samsung_pinctrl_parse_dt(struct platform_device *pdev, + struct samsung_pinctrl_drv_data *drvdata) +{ + struct device *dev = &pdev->dev; + struct samsung_pin_group *groups; + struct samsung_pmx_func *functions; + unsigned int grp_cnt = 0, func_cnt = 0; + + groups = samsung_pinctrl_create_groups(dev, drvdata, &grp_cnt); + if (IS_ERR(groups)) { + dev_err(dev, "failed to parse pin groups\n"); + return PTR_ERR(groups); + } + + functions = samsung_pinctrl_create_functions(dev, drvdata, &func_cnt); + if (IS_ERR(functions)) { + dev_err(dev, "failed to parse pin functions\n"); + return PTR_ERR(functions); + } + + drvdata->pin_groups = groups; + drvdata->nr_groups = grp_cnt; + drvdata->pmx_functions = functions; + drvdata->nr_functions = func_cnt; + + return 0; +} + +/* register the pinctrl interface with the pinctrl subsystem */ +static int samsung_pinctrl_register(struct platform_device *pdev, + struct samsung_pinctrl_drv_data *drvdata) +{ + struct pinctrl_desc *ctrldesc = &drvdata->pctl; + struct pinctrl_pin_desc *pindesc, *pdesc; + struct samsung_pin_bank *pin_bank; + char *pin_names; + int pin, bank, ret; + + ctrldesc->name = "samsung-pinctrl"; + ctrldesc->owner = THIS_MODULE; + ctrldesc->pctlops = &samsung_pctrl_ops; + ctrldesc->pmxops = &samsung_pinmux_ops; + ctrldesc->confops = &samsung_pinconf_ops; + + pindesc = devm_kcalloc(&pdev->dev, + drvdata->nr_pins, sizeof(*pindesc), + GFP_KERNEL); + if (!pindesc) + return -ENOMEM; + ctrldesc->pins = pindesc; + ctrldesc->npins = drvdata->nr_pins; + + /* dynamically populate the pin number and pin name for pindesc */ + for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++) + pdesc->number = pin + drvdata->pin_base; + + /* + * allocate space for storing the dynamically generated names for all + * the pins which belong to this pin-controller. + */ + pin_names = devm_kzalloc(&pdev->dev, + array3_size(sizeof(char), PIN_NAME_LENGTH, + drvdata->nr_pins), + GFP_KERNEL); + if (!pin_names) + return -ENOMEM; + + /* for each pin, the name of the pin is pin-bank name + pin number */ + for (bank = 0; bank < drvdata->nr_banks; bank++) { + pin_bank = &drvdata->pin_banks[bank]; + for (pin = 0; pin < pin_bank->nr_pins; pin++) { + sprintf(pin_names, "%s-%d", pin_bank->name, pin); + pdesc = pindesc + pin_bank->pin_base + pin; + pdesc->name = pin_names; + pin_names += PIN_NAME_LENGTH; + } + } + + ret = samsung_pinctrl_parse_dt(pdev, drvdata); + if (ret) + return ret; + + drvdata->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, + drvdata); + if (IS_ERR(drvdata->pctl_dev)) { + dev_err(&pdev->dev, "could not register pinctrl driver\n"); + return PTR_ERR(drvdata->pctl_dev); + } + + for (bank = 0; bank < drvdata->nr_banks; ++bank) { + pin_bank = &drvdata->pin_banks[bank]; + pin_bank->grange.name = pin_bank->name; + pin_bank->grange.id = bank; + pin_bank->grange.pin_base = drvdata->pin_base + + pin_bank->pin_base; + pin_bank->grange.base = pin_bank->grange.pin_base; + pin_bank->grange.npins = pin_bank->nr_pins; + pin_bank->grange.gc = &pin_bank->gpio_chip; + pinctrl_add_gpio_range(drvdata->pctl_dev, &pin_bank->grange); + } + + return 0; +} + +/* unregister the pinctrl interface with the pinctrl subsystem */ +static int samsung_pinctrl_unregister(struct platform_device *pdev, + struct samsung_pinctrl_drv_data *drvdata) +{ + struct samsung_pin_bank *bank = drvdata->pin_banks; + int i; + + for (i = 0; i < drvdata->nr_banks; ++i, ++bank) + pinctrl_remove_gpio_range(drvdata->pctl_dev, &bank->grange); + + return 0; +} + +static const struct gpio_chip samsung_gpiolib_chip = { + .request = gpiochip_generic_request, + .free = gpiochip_generic_free, + .set = samsung_gpio_set, + .get = samsung_gpio_get, + .direction_input = samsung_gpio_direction_input, + .direction_output = samsung_gpio_direction_output, + .to_irq = samsung_gpio_to_irq, + .owner = THIS_MODULE, +}; + +/* register the gpiolib interface with the gpiolib subsystem */ +static int samsung_gpiolib_register(struct platform_device *pdev, + struct samsung_pinctrl_drv_data *drvdata) +{ + struct samsung_pin_bank *bank = drvdata->pin_banks; + struct gpio_chip *gc; + int ret; + int i; + + for (i = 0; i < drvdata->nr_banks; ++i, ++bank) { + bank->gpio_chip = samsung_gpiolib_chip; + + gc = &bank->gpio_chip; + gc->base = bank->grange.base; + gc->ngpio = bank->nr_pins; + gc->parent = &pdev->dev; + gc->fwnode = bank->fwnode; + gc->label = bank->name; + + ret = devm_gpiochip_add_data(&pdev->dev, gc, bank); + if (ret) { + dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", + gc->label, ret); + return ret; + } + } + + return 0; +} + +static const struct samsung_pin_ctrl * +samsung_pinctrl_get_soc_data_for_of_alias(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + const struct samsung_pinctrl_of_match_data *of_data; + int id; + + id = of_alias_get_id(node, "pinctrl"); + if (id < 0) { + dev_err(&pdev->dev, "failed to get alias id\n"); + return NULL; + } + + of_data = of_device_get_match_data(&pdev->dev); + if (id >= of_data->num_ctrl) { + dev_err(&pdev->dev, "invalid alias id %d\n", id); + return NULL; + } + + return &(of_data->ctrl[id]); +} + +static void samsung_banks_node_put(struct samsung_pinctrl_drv_data *d) +{ + struct samsung_pin_bank *bank; + unsigned int i; + + bank = d->pin_banks; + for (i = 0; i < d->nr_banks; ++i, ++bank) + fwnode_handle_put(bank->fwnode); +} + +/* + * Iterate over all driver pin banks to find one matching the name of node, + * skipping optional "-gpio" node suffix. When found, assign node to the bank. + */ +static void samsung_banks_node_get(struct device *dev, struct samsung_pinctrl_drv_data *d) +{ + const char *suffix = "-gpio-bank"; + struct samsung_pin_bank *bank; + struct fwnode_handle *child; + /* Pin bank names are up to 4 characters */ + char node_name[20]; + unsigned int i; + size_t len; + + bank = d->pin_banks; + for (i = 0; i < d->nr_banks; ++i, ++bank) { + strscpy(node_name, bank->name, sizeof(node_name)); + len = strlcat(node_name, suffix, sizeof(node_name)); + if (len >= sizeof(node_name)) { + dev_err(dev, "Too long pin bank name '%s', ignoring\n", + bank->name); + continue; + } + + for_each_gpiochip_node(dev, child) { + struct device_node *np = to_of_node(child); + + if (of_node_name_eq(np, node_name)) + break; + if (of_node_name_eq(np, bank->name)) + break; + } + + if (child) + bank->fwnode = child; + else + dev_warn(dev, "Missing node for bank %s - invalid DTB\n", + bank->name); + /* child reference dropped in samsung_drop_banks_of_node() */ + } +} + +/* retrieve the soc specific data */ +static const struct samsung_pin_ctrl * +samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, + struct platform_device *pdev) +{ + const struct samsung_pin_bank_data *bdata; + const struct samsung_pin_ctrl *ctrl; + struct samsung_pin_bank *bank; + struct resource *res; + void __iomem *virt_base[SAMSUNG_PINCTRL_NUM_RESOURCES]; + unsigned int i; + + ctrl = samsung_pinctrl_get_soc_data_for_of_alias(pdev); + if (!ctrl) + return ERR_PTR(-ENOENT); + + d->suspend = ctrl->suspend; + d->resume = ctrl->resume; + d->nr_banks = ctrl->nr_banks; + d->pin_banks = devm_kcalloc(&pdev->dev, d->nr_banks, + sizeof(*d->pin_banks), GFP_KERNEL); + if (!d->pin_banks) + return ERR_PTR(-ENOMEM); + + if (ctrl->nr_ext_resources + 1 > SAMSUNG_PINCTRL_NUM_RESOURCES) + return ERR_PTR(-EINVAL); + + for (i = 0; i < ctrl->nr_ext_resources + 1; i++) { + res = platform_get_resource(pdev, IORESOURCE_MEM, i); + if (!res) { + dev_err(&pdev->dev, "failed to get mem%d resource\n", i); + return ERR_PTR(-EINVAL); + } + virt_base[i] = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (!virt_base[i]) { + dev_err(&pdev->dev, "failed to ioremap %pR\n", res); + return ERR_PTR(-EIO); + } + } + + bank = d->pin_banks; + bdata = ctrl->pin_banks; + for (i = 0; i < ctrl->nr_banks; ++i, ++bdata, ++bank) { + bank->type = bdata->type; + bank->pctl_offset = bdata->pctl_offset; + bank->nr_pins = bdata->nr_pins; + bank->eint_func = bdata->eint_func; + bank->eint_type = bdata->eint_type; + bank->eint_mask = bdata->eint_mask; + bank->eint_offset = bdata->eint_offset; + bank->name = bdata->name; + + raw_spin_lock_init(&bank->slock); + bank->drvdata = d; + bank->pin_base = d->nr_pins; + d->nr_pins += bank->nr_pins; + + bank->eint_base = virt_base[0]; + bank->pctl_base = virt_base[bdata->pctl_res_idx]; + } + /* + * Legacy platforms should provide only one resource with IO memory. + * Store it as virt_base because legacy driver needs to access it + * through samsung_pinctrl_drv_data. + */ + d->virt_base = virt_base[0]; + + samsung_banks_node_get(&pdev->dev, d); + + d->pin_base = pin_base; + pin_base += d->nr_pins; + + return ctrl; +} + +static int samsung_pinctrl_probe(struct platform_device *pdev) +{ + struct samsung_pinctrl_drv_data *drvdata; + const struct samsung_pin_ctrl *ctrl; + struct device *dev = &pdev->dev; + int ret; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + ctrl = samsung_pinctrl_get_soc_data(drvdata, pdev); + if (IS_ERR(ctrl)) { + dev_err(&pdev->dev, "driver data not available\n"); + return PTR_ERR(ctrl); + } + drvdata->dev = dev; + + ret = platform_get_irq_optional(pdev, 0); + if (ret < 0 && ret != -ENXIO) + return ret; + if (ret > 0) + drvdata->irq = ret; + + if (ctrl->retention_data) { + drvdata->retention_ctrl = ctrl->retention_data->init(drvdata, + ctrl->retention_data); + if (IS_ERR(drvdata->retention_ctrl)) { + ret = PTR_ERR(drvdata->retention_ctrl); + goto err_put_banks; + } + } + + ret = samsung_pinctrl_register(pdev, drvdata); + if (ret) + goto err_put_banks; + + if (ctrl->eint_gpio_init) + ctrl->eint_gpio_init(drvdata); + if (ctrl->eint_wkup_init) + ctrl->eint_wkup_init(drvdata); + + ret = samsung_gpiolib_register(pdev, drvdata); + if (ret) + goto err_unregister; + + platform_set_drvdata(pdev, drvdata); + + return 0; + +err_unregister: + samsung_pinctrl_unregister(pdev, drvdata); +err_put_banks: + samsung_banks_node_put(drvdata); + return ret; +} + +/* + * samsung_pinctrl_suspend - save pinctrl state for suspend + * + * Save data for all banks handled by this device. + */ +static int __maybe_unused samsung_pinctrl_suspend(struct device *dev) +{ + struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev); + int i; + + for (i = 0; i < drvdata->nr_banks; i++) { + struct samsung_pin_bank *bank = &drvdata->pin_banks[i]; + void __iomem *reg = bank->pctl_base + bank->pctl_offset; + const u8 *offs = bank->type->reg_offset; + const u8 *widths = bank->type->fld_width; + enum pincfg_type type; + + /* Registers without a powerdown config aren't lost */ + if (!widths[PINCFG_TYPE_CON_PDN]) + continue; + + for (type = 0; type < PINCFG_TYPE_NUM; type++) + if (widths[type]) + bank->pm_save[type] = readl(reg + offs[type]); + + if (widths[PINCFG_TYPE_FUNC] * bank->nr_pins > 32) { + /* Some banks have two config registers */ + bank->pm_save[PINCFG_TYPE_NUM] = + readl(reg + offs[PINCFG_TYPE_FUNC] + 4); + pr_debug("Save %s @ %p (con %#010x %08x)\n", + bank->name, reg, + bank->pm_save[PINCFG_TYPE_FUNC], + bank->pm_save[PINCFG_TYPE_NUM]); + } else { + pr_debug("Save %s @ %p (con %#010x)\n", bank->name, + reg, bank->pm_save[PINCFG_TYPE_FUNC]); + } + } + + if (drvdata->suspend) + drvdata->suspend(drvdata); + if (drvdata->retention_ctrl && drvdata->retention_ctrl->enable) + drvdata->retention_ctrl->enable(drvdata); + + return 0; +} + +/* + * samsung_pinctrl_resume - restore pinctrl state from suspend + * + * Restore one of the banks that was saved during suspend. + * + * We don't bother doing anything complicated to avoid glitching lines since + * we're called before pad retention is turned off. + */ +static int __maybe_unused samsung_pinctrl_resume(struct device *dev) +{ + struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev); + int i; + + if (drvdata->resume) + drvdata->resume(drvdata); + + for (i = 0; i < drvdata->nr_banks; i++) { + struct samsung_pin_bank *bank = &drvdata->pin_banks[i]; + void __iomem *reg = bank->pctl_base + bank->pctl_offset; + const u8 *offs = bank->type->reg_offset; + const u8 *widths = bank->type->fld_width; + enum pincfg_type type; + + /* Registers without a powerdown config aren't lost */ + if (!widths[PINCFG_TYPE_CON_PDN]) + continue; + + if (widths[PINCFG_TYPE_FUNC] * bank->nr_pins > 32) { + /* Some banks have two config registers */ + pr_debug("%s @ %p (con %#010x %08x => %#010x %08x)\n", + bank->name, reg, + readl(reg + offs[PINCFG_TYPE_FUNC]), + readl(reg + offs[PINCFG_TYPE_FUNC] + 4), + bank->pm_save[PINCFG_TYPE_FUNC], + bank->pm_save[PINCFG_TYPE_NUM]); + writel(bank->pm_save[PINCFG_TYPE_NUM], + reg + offs[PINCFG_TYPE_FUNC] + 4); + } else { + pr_debug("%s @ %p (con %#010x => %#010x)\n", bank->name, + reg, readl(reg + offs[PINCFG_TYPE_FUNC]), + bank->pm_save[PINCFG_TYPE_FUNC]); + } + for (type = 0; type < PINCFG_TYPE_NUM; type++) + if (widths[type]) + writel(bank->pm_save[type], reg + offs[type]); + } + + if (drvdata->retention_ctrl && drvdata->retention_ctrl->disable) + drvdata->retention_ctrl->disable(drvdata); + + return 0; +} + +static const struct of_device_id samsung_pinctrl_dt_match[] = { +#ifdef CONFIG_PINCTRL_EXYNOS_ARM + { .compatible = "samsung,exynos3250-pinctrl", + .data = &exynos3250_of_data }, + { .compatible = "samsung,exynos4210-pinctrl", + .data = &exynos4210_of_data }, + { .compatible = "samsung,exynos4x12-pinctrl", + .data = &exynos4x12_of_data }, + { .compatible = "samsung,exynos5250-pinctrl", + .data = &exynos5250_of_data }, + { .compatible = "samsung,exynos5260-pinctrl", + .data = &exynos5260_of_data }, + { .compatible = "samsung,exynos5410-pinctrl", + .data = &exynos5410_of_data }, + { .compatible = "samsung,exynos5420-pinctrl", + .data = &exynos5420_of_data }, + { .compatible = "samsung,s5pv210-pinctrl", + .data = &s5pv210_of_data }, +#endif +#ifdef CONFIG_PINCTRL_EXYNOS_ARM64 + { .compatible = "samsung,exynos5433-pinctrl", + .data = &exynos5433_of_data }, + { .compatible = "samsung,exynos7-pinctrl", + .data = &exynos7_of_data }, + { .compatible = "samsung,exynos7885-pinctrl", + .data = &exynos7885_of_data }, + { .compatible = "samsung,exynos850-pinctrl", + .data = &exynos850_of_data }, + { .compatible = "samsung,exynosautov9-pinctrl", + .data = &exynosautov9_of_data }, + { .compatible = "tesla,fsd-pinctrl", + .data = &fsd_of_data }, +#endif +#ifdef CONFIG_PINCTRL_S3C64XX + { .compatible = "samsung,s3c64xx-pinctrl", + .data = &s3c64xx_of_data }, +#endif + {}, +}; + +static const struct dev_pm_ops samsung_pinctrl_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(samsung_pinctrl_suspend, + samsung_pinctrl_resume) +}; + +static struct platform_driver samsung_pinctrl_driver = { + .probe = samsung_pinctrl_probe, + .driver = { + .name = "samsung-pinctrl", + .of_match_table = samsung_pinctrl_dt_match, + .suppress_bind_attrs = true, + .pm = &samsung_pinctrl_pm_ops, + }, +}; + +static int __init samsung_pinctrl_drv_register(void) +{ + return platform_driver_register(&samsung_pinctrl_driver); +} +postcore_initcall(samsung_pinctrl_drv_register); diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h new file mode 100644 index 0000000000..9af93e3d8d --- /dev/null +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -0,0 +1,361 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's. + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2012 Linaro Ltd + * http://www.linaro.org + * + * Author: Thomas Abraham <thomas.ab@samsung.com> + */ + +#ifndef __PINCTRL_SAMSUNG_H +#define __PINCTRL_SAMSUNG_H + +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/machine.h> + +#include <linux/gpio/driver.h> + +/** + * enum pincfg_type - possible pin configuration types supported. + * @PINCFG_TYPE_FUNC: Function configuration. + * @PINCFG_TYPE_DAT: Pin value configuration. + * @PINCFG_TYPE_PUD: Pull up/down configuration. + * @PINCFG_TYPE_DRV: Drive strength configuration. + * @PINCFG_TYPE_CON_PDN: Pin function in power down mode. + * @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode. + */ +enum pincfg_type { + PINCFG_TYPE_FUNC, + PINCFG_TYPE_DAT, + PINCFG_TYPE_PUD, + PINCFG_TYPE_DRV, + PINCFG_TYPE_CON_PDN, + PINCFG_TYPE_PUD_PDN, + + PINCFG_TYPE_NUM +}; + +/* + * pin configuration (pull up/down and drive strength) type and its value are + * packed together into a 16-bits. The upper 8-bits represent the configuration + * type and the lower 8-bits hold the value of the configuration type. + */ +#define PINCFG_TYPE_MASK 0xFF +#define PINCFG_VALUE_SHIFT 8 +#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT) +#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type) +#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK) +#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \ + PINCFG_VALUE_SHIFT) +/* + * Values for the pin CON register, choosing pin function. + * The basic set (input and output) are same between: S3C24xx, S3C64xx, S5PV210, + * Exynos ARMv7, Exynos ARMv8, Tesla FSD. + */ +#define PIN_CON_FUNC_INPUT 0x0 +#define PIN_CON_FUNC_OUTPUT 0x1 + +/** + * enum eint_type - possible external interrupt types. + * @EINT_TYPE_NONE: bank does not support external interrupts + * @EINT_TYPE_GPIO: bank supportes external gpio interrupts + * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts + * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts + * + * Samsung GPIO controller groups all the available pins into banks. The pins + * in a pin bank can support external gpio interrupts or external wakeup + * interrupts or no interrupts at all. From a software perspective, the only + * difference between external gpio and external wakeup interrupts is that + * the wakeup interrupts can additionally wakeup the system if it is in + * suspended state. + */ +enum eint_type { + EINT_TYPE_NONE, + EINT_TYPE_GPIO, + EINT_TYPE_WKUP, + EINT_TYPE_WKUP_MUX, +}; + +/* maximum length of a pin in pin descriptor (example: "gpa0-0") */ +#define PIN_NAME_LENGTH 10 + +#define PIN_GROUP(n, p, f) \ + { \ + .name = n, \ + .pins = p, \ + .num_pins = ARRAY_SIZE(p), \ + .func = f \ + } + +#define PMX_FUNC(n, g) \ + { \ + .name = n, \ + .groups = g, \ + .num_groups = ARRAY_SIZE(g), \ + } + +struct samsung_pinctrl_drv_data; + +/** + * struct samsung_pin_bank_type: pin bank type description + * @fld_width: widths of configuration bitfields (0 if unavailable) + * @reg_offset: offsets of configuration registers (don't care of width is 0) + */ +struct samsung_pin_bank_type { + u8 fld_width[PINCFG_TYPE_NUM]; + u8 reg_offset[PINCFG_TYPE_NUM]; +}; + +/** + * struct samsung_pin_bank_data: represent a controller pin-bank (init data). + * @type: type of the bank (register offsets and bitfield widths) + * @pctl_offset: starting offset of the pin-bank registers. + * @pctl_res_idx: index of base address for pin-bank registers. + * @nr_pins: number of pins included in this bank. + * @eint_func: function to set in CON register to configure pin as EINT. + * @eint_type: type of the external interrupt supported by the bank. + * @eint_mask: bit mask of pins which support EINT function. + * @eint_offset: SoC-specific EINT register or interrupt offset of bank. + * @name: name to be prefixed for each pin in this pin bank. + */ +struct samsung_pin_bank_data { + const struct samsung_pin_bank_type *type; + u32 pctl_offset; + u8 pctl_res_idx; + u8 nr_pins; + u8 eint_func; + enum eint_type eint_type; + u32 eint_mask; + u32 eint_offset; + const char *name; +}; + +/** + * struct samsung_pin_bank: represent a controller pin-bank. + * @type: type of the bank (register offsets and bitfield widths) + * @pctl_base: base address of the pin-bank registers + * @pctl_offset: starting offset of the pin-bank registers. + * @nr_pins: number of pins included in this bank. + * @eint_base: base address of the pin-bank EINT registers. + * @eint_func: function to set in CON register to configure pin as EINT. + * @eint_type: type of the external interrupt supported by the bank. + * @eint_mask: bit mask of pins which support EINT function. + * @eint_offset: SoC-specific EINT register or interrupt offset of bank. + * @name: name to be prefixed for each pin in this pin bank. + * @pin_base: starting pin number of the bank. + * @soc_priv: per-bank private data for SoC-specific code. + * @of_node: OF node of the bank. + * @drvdata: link to controller driver data + * @irq_domain: IRQ domain of the bank. + * @gpio_chip: GPIO chip of the bank. + * @grange: linux gpio pin range supported by this bank. + * @irq_chip: link to irq chip for external gpio and wakeup interrupts. + * @slock: spinlock protecting bank registers + * @pm_save: saved register values during suspend + */ +struct samsung_pin_bank { + const struct samsung_pin_bank_type *type; + void __iomem *pctl_base; + u32 pctl_offset; + u8 nr_pins; + void __iomem *eint_base; + u8 eint_func; + enum eint_type eint_type; + u32 eint_mask; + u32 eint_offset; + const char *name; + + u32 pin_base; + void *soc_priv; + struct fwnode_handle *fwnode; + struct samsung_pinctrl_drv_data *drvdata; + struct irq_domain *irq_domain; + struct gpio_chip gpio_chip; + struct pinctrl_gpio_range grange; + struct exynos_irq_chip *irq_chip; + raw_spinlock_t slock; + + u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/ +}; + +/** + * struct samsung_retention_data: runtime pin-bank retention control data. + * @regs: array of PMU registers to control pad retention. + * @nr_regs: number of registers in @regs array. + * @value: value to store to registers to turn off retention. + * @refcnt: atomic counter if retention control affects more than one bank. + * @priv: retention control code private data + * @enable: platform specific callback to enter retention mode. + * @disable: platform specific callback to exit retention mode. + **/ +struct samsung_retention_ctrl { + const u32 *regs; + int nr_regs; + u32 value; + atomic_t *refcnt; + void *priv; + void (*enable)(struct samsung_pinctrl_drv_data *); + void (*disable)(struct samsung_pinctrl_drv_data *); +}; + +/** + * struct samsung_retention_data: represent a pin-bank retention control data. + * @regs: array of PMU registers to control pad retention. + * @nr_regs: number of registers in @regs array. + * @value: value to store to registers to turn off retention. + * @refcnt: atomic counter if retention control affects more than one bank. + * @init: platform specific callback to initialize retention control. + **/ +struct samsung_retention_data { + const u32 *regs; + int nr_regs; + u32 value; + atomic_t *refcnt; + struct samsung_retention_ctrl *(*init)(struct samsung_pinctrl_drv_data *, + const struct samsung_retention_data *); +}; + +/** + * struct samsung_pin_ctrl: represent a pin controller. + * @pin_banks: list of pin banks included in this controller. + * @nr_banks: number of pin banks. + * @nr_ext_resources: number of the extra base address for pin banks. + * @retention_data: configuration data for retention control. + * @eint_gpio_init: platform specific callback to setup the external gpio + * interrupts for the controller. + * @eint_wkup_init: platform specific callback to setup the external wakeup + * interrupts for the controller. + * @suspend: platform specific suspend callback, executed during pin controller + * device suspend, see samsung_pinctrl_suspend() + * @resume: platform specific resume callback, executed during pin controller + * device suspend, see samsung_pinctrl_resume() + * + * External wakeup interrupts must define at least eint_wkup_init, + * retention_data and suspend in order for proper suspend/resume to work. + */ +struct samsung_pin_ctrl { + const struct samsung_pin_bank_data *pin_banks; + unsigned int nr_banks; + unsigned int nr_ext_resources; + const struct samsung_retention_data *retention_data; + + int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); + int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *); + void (*suspend)(struct samsung_pinctrl_drv_data *); + void (*resume)(struct samsung_pinctrl_drv_data *); +}; + +/** + * struct samsung_pinctrl_drv_data: wrapper for holding driver data together. + * @node: global list node + * @virt_base: register base address of the controller; this will be equal + * to each bank samsung_pin_bank->pctl_base and used on legacy + * platforms (like S3C24XX or S3C64XX) which has to access the base + * through samsung_pinctrl_drv_data, not samsung_pin_bank). + * @dev: device instance representing the controller. + * @irq: interrpt number used by the controller to notify gpio interrupts. + * @ctrl: pin controller instance managed by the driver. + * @pctl: pin controller descriptor registered with the pinctrl subsystem. + * @pctl_dev: cookie representing pinctrl device instance. + * @pin_groups: list of pin groups available to the driver. + * @nr_groups: number of such pin groups. + * @pmx_functions: list of pin functions available to the driver. + * @nr_function: number of such pin functions. + * @pin_base: starting system wide pin number. + * @nr_pins: number of pins supported by the controller. + * @retention_ctrl: retention control runtime data. + * @suspend: platform specific suspend callback, executed during pin controller + * device suspend, see samsung_pinctrl_suspend() + * @resume: platform specific resume callback, executed during pin controller + * device suspend, see samsung_pinctrl_resume() + */ +struct samsung_pinctrl_drv_data { + struct list_head node; + void __iomem *virt_base; + struct device *dev; + int irq; + + struct pinctrl_desc pctl; + struct pinctrl_dev *pctl_dev; + + const struct samsung_pin_group *pin_groups; + unsigned int nr_groups; + const struct samsung_pmx_func *pmx_functions; + unsigned int nr_functions; + + struct samsung_pin_bank *pin_banks; + unsigned int nr_banks; + unsigned int pin_base; + unsigned int nr_pins; + + struct samsung_retention_ctrl *retention_ctrl; + + void (*suspend)(struct samsung_pinctrl_drv_data *); + void (*resume)(struct samsung_pinctrl_drv_data *); +}; + +/** + * struct samsung_pinctrl_of_match_data: OF match device specific configuration data. + * @ctrl: array of pin controller data. + * @num_ctrl: size of array @ctrl. + */ +struct samsung_pinctrl_of_match_data { + const struct samsung_pin_ctrl *ctrl; + unsigned int num_ctrl; +}; + +/** + * struct samsung_pin_group: represent group of pins of a pinmux function. + * @name: name of the pin group, used to lookup the group. + * @pins: the pins included in this group. + * @num_pins: number of pins included in this group. + * @func: the function number to be programmed when selected. + */ +struct samsung_pin_group { + const char *name; + const unsigned int *pins; + u8 num_pins; + u8 func; +}; + +/** + * struct samsung_pmx_func: represent a pin function. + * @name: name of the pin function, used to lookup the function. + * @groups: one or more names of pin groups that provide this function. + * @num_groups: number of groups included in @groups. + */ +struct samsung_pmx_func { + const char *name; + const char **groups; + u8 num_groups; + u32 val; +}; + +/* list of all exported SoC specific data */ +extern const struct samsung_pinctrl_of_match_data exynos3250_of_data; +extern const struct samsung_pinctrl_of_match_data exynos4210_of_data; +extern const struct samsung_pinctrl_of_match_data exynos4x12_of_data; +extern const struct samsung_pinctrl_of_match_data exynos5250_of_data; +extern const struct samsung_pinctrl_of_match_data exynos5260_of_data; +extern const struct samsung_pinctrl_of_match_data exynos5410_of_data; +extern const struct samsung_pinctrl_of_match_data exynos5420_of_data; +extern const struct samsung_pinctrl_of_match_data exynos5433_of_data; +extern const struct samsung_pinctrl_of_match_data exynos7_of_data; +extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; +extern const struct samsung_pinctrl_of_match_data exynos850_of_data; +extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; +extern const struct samsung_pinctrl_of_match_data fsd_of_data; +extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; +extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; +extern const struct samsung_pinctrl_of_match_data s3c2416_of_data; +extern const struct samsung_pinctrl_of_match_data s3c2440_of_data; +extern const struct samsung_pinctrl_of_match_data s3c2450_of_data; +extern const struct samsung_pinctrl_of_match_data s5pv210_of_data; + +#endif /* __PINCTRL_SAMSUNG_H */ |