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path: root/drivers/thermal/mediatek/lvts_thermal.c
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Diffstat (limited to 'drivers/thermal/mediatek/lvts_thermal.c')
-rw-r--r--drivers/thermal/mediatek/lvts_thermal.c256
1 files changed, 234 insertions, 22 deletions
diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index effd9b00a4..98d9c80bd4 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -80,8 +80,10 @@
#define LVTS_SENSOR_MAX 4
#define LVTS_GOLDEN_TEMP_MAX 62
#define LVTS_GOLDEN_TEMP_DEFAULT 50
-#define LVTS_COEFF_A -250460
-#define LVTS_COEFF_B 250460
+#define LVTS_COEFF_A_MT8195 -250460
+#define LVTS_COEFF_B_MT8195 250460
+#define LVTS_COEFF_A_MT7988 -204650
+#define LVTS_COEFF_B_MT7988 204650
#define LVTS_MSR_IMMEDIATE_MODE 0
#define LVTS_MSR_FILTERED_MODE 1
@@ -89,12 +91,14 @@
#define LVTS_MSR_READ_TIMEOUT_US 400
#define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2)
+#define LVTS_HW_SHUTDOWN_MT7988 105000
+#define LVTS_HW_SHUTDOWN_MT8192 105000
#define LVTS_HW_SHUTDOWN_MT8195 105000
#define LVTS_MINIMUM_THRESHOLD 20000
static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
-static int coeff_b = LVTS_COEFF_B;
+static int golden_temp_offset;
struct lvts_sensor_data {
int dt_id;
@@ -112,6 +116,8 @@ struct lvts_ctrl_data {
struct lvts_data {
const struct lvts_ctrl_data *lvts_ctrl;
int num_lvts_ctrl;
+ int temp_factor;
+ int temp_offset;
};
struct lvts_sensor {
@@ -126,6 +132,7 @@ struct lvts_sensor {
struct lvts_ctrl {
struct lvts_sensor sensors[LVTS_SENSOR_MAX];
+ const struct lvts_data *lvts_data;
u32 calibration[LVTS_SENSOR_MAX];
u32 hw_tshut_raw_temp;
int num_lvts_sensor;
@@ -213,7 +220,7 @@ static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td)
sprintf(name, "controller%d", i);
dentry = debugfs_create_dir(name, lvts_td->dom_dentry);
- if (!dentry)
+ if (IS_ERR(dentry))
continue;
regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
@@ -247,21 +254,21 @@ static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { }
#endif
-static int lvts_raw_to_temp(u32 raw_temp)
+static int lvts_raw_to_temp(u32 raw_temp, int temp_factor)
{
int temperature;
- temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14;
- temperature += coeff_b;
+ temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14;
+ temperature += golden_temp_offset;
return temperature;
}
-static u32 lvts_temp_to_raw(int temperature)
+static u32 lvts_temp_to_raw(int temperature, int temp_factor)
{
- u32 raw_temp = ((s64)(coeff_b - temperature)) << 14;
+ u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14;
- raw_temp = div_s64(raw_temp, -LVTS_COEFF_A);
+ raw_temp = div_s64(raw_temp, -temp_factor);
return raw_temp;
}
@@ -269,6 +276,9 @@ static u32 lvts_temp_to_raw(int temperature)
static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
{
struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
+ struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
+ sensors[lvts_sensor->id]);
+ const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
void __iomem *msr = lvts_sensor->msr;
u32 value;
int rc;
@@ -301,7 +311,7 @@ static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
if (rc)
return -EAGAIN;
- *temp = lvts_raw_to_temp(value & 0xFFFF);
+ *temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor);
return 0;
}
@@ -348,10 +358,13 @@ static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high)
static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
{
struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
- struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]);
+ struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
+ sensors[lvts_sensor->id]);
+ const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
void __iomem *base = lvts_sensor->base;
- u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD);
- u32 raw_high = lvts_temp_to_raw(high);
+ u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD,
+ lvts_data->temp_factor);
+ u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor);
bool should_update_thresh;
lvts_sensor->low_thresh = low;
@@ -603,7 +616,34 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
* The efuse blob values follows the sensor enumeration per thermal
* controller. The decoding of the stream is as follow:
*
- * stream index map for MCU Domain :
+ * MT8192 :
+ * Stream index map for MCU Domain mt8192 :
+ *
+ * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
+ * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B
+ *
+ * <-----sensor#2-----> <-----sensor#3----->
+ * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13
+ *
+ * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
+ * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23
+ *
+ * Stream index map for AP Domain mt8192 :
+ *
+ * <-----sensor#0-----> <-----sensor#1----->
+ * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B
+ *
+ * <-----sensor#2-----> <-----sensor#3----->
+ * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
+ *
+ * <-----sensor#4-----> <-----sensor#5----->
+ * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B
+ *
+ * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8----->
+ * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47
+ *
+ * MT8195 :
+ * Stream index map for MCU Domain mt8195 :
*
* <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
* 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
@@ -614,7 +654,7 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
* <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
* 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
*
- * stream index map for AP Domain :
+ * Stream index map for AP Domain mt8195 :
*
* <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
* 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
@@ -692,7 +732,7 @@ static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td
return 0;
}
-static int lvts_golden_temp_init(struct device *dev, u32 *value)
+static int lvts_golden_temp_init(struct device *dev, u32 *value, int temp_offset)
{
u32 gt;
@@ -701,7 +741,7 @@ static int lvts_golden_temp_init(struct device *dev, u32 *value)
if (gt && gt < LVTS_GOLDEN_TEMP_MAX)
golden_temp = gt;
- coeff_b = golden_temp * 500 + LVTS_COEFF_B;
+ golden_temp_offset = golden_temp * 500 + temp_offset;
return 0;
}
@@ -724,7 +764,7 @@ static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td,
* The golden temp information is contained in the first chunk
* of efuse data.
*/
- ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib);
+ ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib, lvts_data->temp_offset);
if (ret)
return ret;
@@ -735,6 +775,7 @@ static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td,
for (i = 0; i < lvts_data->num_lvts_ctrl; i++) {
lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset;
+ lvts_ctrl[i].lvts_data = lvts_data;
ret = lvts_sensor_init(dev, &lvts_ctrl[i],
&lvts_data->lvts_ctrl[i]);
@@ -758,7 +799,8 @@ static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td,
* after initializing the calibration.
*/
lvts_ctrl[i].hw_tshut_raw_temp =
- lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp);
+ lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp,
+ lvts_data->temp_factor);
lvts_ctrl[i].low_thresh = INT_MIN;
lvts_ctrl[i].high_thresh = INT_MIN;
@@ -1223,6 +1265,8 @@ static int lvts_probe(struct platform_device *pdev)
if (irq < 0)
return irq;
+ golden_temp_offset = lvts_data->temp_offset;
+
ret = lvts_domain_init(dev, lvts_td, lvts_data);
if (ret)
return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n");
@@ -1241,7 +1285,7 @@ static int lvts_probe(struct platform_device *pdev)
return 0;
}
-static int lvts_remove(struct platform_device *pdev)
+static void lvts_remove(struct platform_device *pdev)
{
struct lvts_domain *lvts_td;
int i;
@@ -1252,10 +1296,149 @@ static int lvts_remove(struct platform_device *pdev)
lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
lvts_debugfs_exit(lvts_td);
+}
+
+static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = {
+ {
+ .cal_offset = { 0x00, 0x04, 0x08, 0x0c },
+ .lvts_sensor = {
+ { .dt_id = MT7988_CPU_0 },
+ { .dt_id = MT7988_CPU_1 },
+ { .dt_id = MT7988_ETH2P5G_0 },
+ { .dt_id = MT7988_ETH2P5G_1 }
+ },
+ .num_lvts_sensor = 4,
+ .offset = 0x0,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
+ },
+ {
+ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
+ .lvts_sensor = {
+ { .dt_id = MT7988_TOPS_0},
+ { .dt_id = MT7988_TOPS_1},
+ { .dt_id = MT7988_ETHWARP_0},
+ { .dt_id = MT7988_ETHWARP_1}
+ },
+ .num_lvts_sensor = 4,
+ .offset = 0x100,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
+ }
+};
+
+static int lvts_suspend(struct device *dev)
+{
+ struct lvts_domain *lvts_td;
+ int i;
+
+ lvts_td = dev_get_drvdata(dev);
+
+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
+ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
+
+ clk_disable_unprepare(lvts_td->clk);
return 0;
}
+static int lvts_resume(struct device *dev)
+{
+ struct lvts_domain *lvts_td;
+ int i, ret;
+
+ lvts_td = dev_get_drvdata(dev);
+
+ ret = clk_prepare_enable(lvts_td->clk);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
+ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true);
+
+ return 0;
+}
+
+static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
+ {
+ .cal_offset = { 0x04, 0x08 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_MCU_BIG_CPU0 },
+ { .dt_id = MT8192_MCU_BIG_CPU1 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x0,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ .mode = LVTS_MSR_FILTERED_MODE,
+ },
+ {
+ .cal_offset = { 0x0c, 0x10 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_MCU_BIG_CPU2 },
+ { .dt_id = MT8192_MCU_BIG_CPU3 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x100,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ .mode = LVTS_MSR_FILTERED_MODE,
+ },
+ {
+ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_MCU_LITTLE_CPU0 },
+ { .dt_id = MT8192_MCU_LITTLE_CPU1 },
+ { .dt_id = MT8192_MCU_LITTLE_CPU2 },
+ { .dt_id = MT8192_MCU_LITTLE_CPU3 }
+ },
+ .num_lvts_sensor = 4,
+ .offset = 0x200,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ .mode = LVTS_MSR_FILTERED_MODE,
+ }
+};
+
+static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
+ {
+ .cal_offset = { 0x24, 0x28 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_VPU0 },
+ { .dt_id = MT8192_AP_VPU1 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x0,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ },
+ {
+ .cal_offset = { 0x2c, 0x30 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_GPU0 },
+ { .dt_id = MT8192_AP_GPU1 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x100,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ },
+ {
+ .cal_offset = { 0x34, 0x38 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_INFRA },
+ { .dt_id = MT8192_AP_CAM },
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x200,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ },
+ {
+ .cal_offset = { 0x3c, 0x40, 0x44 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_MD0 },
+ { .dt_id = MT8192_AP_MD1 },
+ { .dt_id = MT8192_AP_MD2 }
+ },
+ .num_lvts_sensor = 3,
+ .offset = 0x300,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ }
+};
+
static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
{
.cal_offset = { 0x04, 0x07 },
@@ -1335,29 +1518,58 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
}
};
+static const struct lvts_data mt7988_lvts_ap_data = {
+ .lvts_ctrl = mt7988_lvts_ap_data_ctrl,
+ .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl),
+ .temp_factor = LVTS_COEFF_A_MT7988,
+ .temp_offset = LVTS_COEFF_B_MT7988,
+};
+
+static const struct lvts_data mt8192_lvts_mcu_data = {
+ .lvts_ctrl = mt8192_lvts_mcu_data_ctrl,
+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
+};
+
+static const struct lvts_data mt8192_lvts_ap_data = {
+ .lvts_ctrl = mt8192_lvts_ap_data_ctrl,
+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
+};
+
static const struct lvts_data mt8195_lvts_mcu_data = {
.lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
+ .temp_factor = LVTS_COEFF_A_MT8195,
+ .temp_offset = LVTS_COEFF_B_MT8195,
};
static const struct lvts_data mt8195_lvts_ap_data = {
.lvts_ctrl = mt8195_lvts_ap_data_ctrl,
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
+ .temp_factor = LVTS_COEFF_A_MT8195,
+ .temp_offset = LVTS_COEFF_B_MT8195,
};
static const struct of_device_id lvts_of_match[] = {
+ { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
+ { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data },
+ { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data },
{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
{},
};
MODULE_DEVICE_TABLE(of, lvts_of_match);
+static const struct dev_pm_ops lvts_pm_ops = {
+ NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume)
+};
+
static struct platform_driver lvts_driver = {
.probe = lvts_probe,
- .remove = lvts_remove,
+ .remove_new = lvts_remove,
.driver = {
.name = "mtk-lvts-thermal",
.of_match_table = lvts_of_match,
+ .pm = &lvts_pm_ops,
},
};
module_platform_driver(lvts_driver);
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-12 15:49:10 +0000