diff options
Diffstat (limited to 'drivers/tty/serial/8250/8250_pci1xxxx.c')
| -rw-r--r-- | drivers/tty/serial/8250/8250_pci1xxxx.c | 175 |
1 files changed, 162 insertions, 13 deletions
diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c index 2dda737b16..2fbb5851f7 100644 --- a/drivers/tty/serial/8250/8250_pci1xxxx.c +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c @@ -7,23 +7,31 @@ * Copyright (C) 2022 Microchip Technology Inc., All Rights Reserved. */ +#include <linux/array_size.h> #include <linux/bitfield.h> -#include <linux/bitops.h> -#include <linux/delay.h> +#include <linux/bits.h> +#include <linux/circ_buf.h> +#include <linux/device.h> +#include <linux/errno.h> +#include <linux/gfp_types.h> #include <linux/io.h> #include <linux/iopoll.h> -#include <linux/kernel.h> +#include <linux/minmax.h> #include <linux/module.h> +#include <linux/mutex.h> +#include <linux/overflow.h> #include <linux/pci.h> +#include <linux/pm.h> #include <linux/serial_core.h> #include <linux/serial_reg.h> #include <linux/serial_8250.h> -#include <linux/slab.h> +#include <linux/spinlock.h> #include <linux/string.h> -#include <linux/units.h> +#include <linux/time.h> #include <linux/tty.h> #include <linux/tty_flip.h> -#include <linux/8250_pci.h> +#include <linux/types.h> +#include <linux/units.h> #include <asm/byteorder.h> @@ -67,6 +75,7 @@ #define SYSLOCK_RETRY_CNT 1000 #define UART_RX_BYTE_FIFO 0x00 +#define UART_TX_BYTE_FIFO 0x00 #define UART_FIFO_CTL 0x02 #define UART_ACTV_REG 0x11 @@ -81,10 +90,10 @@ #define ADCL_CFG_PIN_SEL BIT(1) #define ADCL_CFG_EN BIT(0) -#define UART_BIT_SAMPLE_CNT 16 +#define UART_BIT_SAMPLE_CNT_8 8 +#define UART_BIT_SAMPLE_CNT_16 16 #define BAUD_CLOCK_DIV_INT_MSK GENMASK(31, 8) #define ADCL_CFG_RTS_DELAY_MASK GENMASK(11, 8) -#define UART_CLOCK_DEFAULT (62500 * HZ_PER_KHZ) #define UART_WAKE_REG 0x8C #define UART_WAKE_MASK_REG 0x90 @@ -95,13 +104,19 @@ (UART_WAKE_N_PIN | UART_WAKE_NCTS | UART_WAKE_INT) #define UART_BAUD_CLK_DIVISOR_REG 0x54 +#define FRAC_DIV_CFG_REG 0x58 #define UART_RESET_REG 0x94 #define UART_RESET_D3_RESET_DISABLE BIT(16) #define UART_BURST_STATUS_REG 0x9C +#define UART_TX_BURST_FIFO 0xA0 #define UART_RX_BURST_FIFO 0xA4 +#define UART_BIT_DIVISOR_8 0x26731000 +#define UART_BIT_DIVISOR_16 0x6ef71000 +#define UART_BAUD_4MBPS 4000000 + #define MAX_PORTS 4 #define PORT_OFFSET 0x100 #define RX_BUF_SIZE 512 @@ -109,6 +124,7 @@ #define UART_BURST_SIZE 4 #define UART_BST_STAT_RX_COUNT_MASK 0x00FF +#define UART_BST_STAT_TX_COUNT_MASK 0xFF00 #define UART_BST_STAT_IIR_INT_PEND 0x100000 #define UART_LSR_OVERRUN_ERR_CLR 0x43 #define UART_BST_STAT_LSR_RX_MASK 0x9F000000 @@ -116,6 +132,7 @@ #define UART_BST_STAT_LSR_OVERRUN_ERR 0x2000000 #define UART_BST_STAT_LSR_PARITY_ERR 0x4000000 #define UART_BST_STAT_LSR_FRAME_ERR 0x8000000 +#define UART_BST_STAT_LSR_THRE 0x20000000 struct pci1xxxx_8250 { unsigned int nr; @@ -206,15 +223,21 @@ static int pci1xxxx_get_num_ports(struct pci_dev *dev) static unsigned int pci1xxxx_get_divisor(struct uart_port *port, unsigned int baud, unsigned int *frac) { + unsigned int uart_sample_cnt; unsigned int quot; + if (baud >= UART_BAUD_4MBPS) + uart_sample_cnt = UART_BIT_SAMPLE_CNT_8; + else + uart_sample_cnt = UART_BIT_SAMPLE_CNT_16; + /* * Calculate baud rate sampling period in nanoseconds. * Fractional part x denotes x/255 parts of a nanosecond. */ - quot = NSEC_PER_SEC / (baud * UART_BIT_SAMPLE_CNT); - *frac = (NSEC_PER_SEC - quot * baud * UART_BIT_SAMPLE_CNT) * - 255 / UART_BIT_SAMPLE_CNT / baud; + quot = NSEC_PER_SEC / (baud * uart_sample_cnt); + *frac = (NSEC_PER_SEC - quot * baud * uart_sample_cnt) * + 255 / uart_sample_cnt / baud; return quot; } @@ -222,6 +245,11 @@ static unsigned int pci1xxxx_get_divisor(struct uart_port *port, static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud, unsigned int quot, unsigned int frac) { + if (baud >= UART_BAUD_4MBPS) + writel(UART_BIT_DIVISOR_8, port->membase + FRAC_DIV_CFG_REG); + else + writel(UART_BIT_DIVISOR_16, port->membase + FRAC_DIV_CFG_REG); + writel(FIELD_PREP(BAUD_CLOCK_DIV_INT_MSK, quot) | frac, port->membase + UART_BAUD_CLK_DIVISOR_REG); } @@ -233,7 +261,16 @@ static int pci1xxxx_rs485_config(struct uart_port *port, u32 delay_in_baud_periods; u32 baud_period_in_ns; u32 mode_cfg = 0; + u32 sample_cnt; u32 clock_div; + u32 frac_div; + + frac_div = readl(port->membase + FRAC_DIV_CFG_REG); + + if (frac_div == UART_BIT_DIVISOR_16) + sample_cnt = UART_BIT_SAMPLE_CNT_16; + else + sample_cnt = UART_BIT_SAMPLE_CNT_8; /* * pci1xxxx's uart hardware supports only RTS delay after @@ -249,7 +286,7 @@ static int pci1xxxx_rs485_config(struct uart_port *port, clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG); baud_period_in_ns = FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) * - UART_BIT_SAMPLE_CNT; + sample_cnt; delay_in_baud_periods = rs485->delay_rts_after_send * NSEC_PER_MSEC / baud_period_in_ns; @@ -344,6 +381,105 @@ static void pci1xxxx_rx_burst(struct uart_port *port, u32 uart_status) } } +static void pci1xxxx_process_write_data(struct uart_port *port, + struct circ_buf *xmit, + int *data_empty_count, + u32 *valid_byte_count) +{ + u32 valid_burst_count = *valid_byte_count / UART_BURST_SIZE; + + /* + * Each transaction transfers data in DWORDs. If there are less than + * four remaining valid_byte_count to transfer or if the circular + * buffer has insufficient space for a DWORD, the data is transferred + * one byte at a time. + */ + while (valid_burst_count) { + if (*data_empty_count - UART_BURST_SIZE < 0) + break; + if (xmit->tail > (UART_XMIT_SIZE - UART_BURST_SIZE)) + break; + writel(*(unsigned int *)&xmit->buf[xmit->tail], + port->membase + UART_TX_BURST_FIFO); + *valid_byte_count -= UART_BURST_SIZE; + *data_empty_count -= UART_BURST_SIZE; + valid_burst_count -= UART_BYTE_SIZE; + + xmit->tail = (xmit->tail + UART_BURST_SIZE) & + (UART_XMIT_SIZE - 1); + } + + while (*valid_byte_count) { + if (*data_empty_count - UART_BYTE_SIZE < 0) + break; + writeb(xmit->buf[xmit->tail], port->membase + + UART_TX_BYTE_FIFO); + *data_empty_count -= UART_BYTE_SIZE; + *valid_byte_count -= UART_BYTE_SIZE; + + /* + * When the tail of the circular buffer is reached, the next + * byte is transferred to the beginning of the buffer. + */ + xmit->tail = (xmit->tail + UART_BYTE_SIZE) & + (UART_XMIT_SIZE - 1); + + /* + * If there are any pending burst count, data is handled by + * transmitting DWORDs at a time. + */ + if (valid_burst_count && (xmit->tail < + (UART_XMIT_SIZE - UART_BURST_SIZE))) + break; + } +} + +static void pci1xxxx_tx_burst(struct uart_port *port, u32 uart_status) +{ + struct uart_8250_port *up = up_to_u8250p(port); + u32 valid_byte_count; + int data_empty_count; + struct circ_buf *xmit; + + xmit = &port->state->xmit; + + if (port->x_char) { + writeb(port->x_char, port->membase + UART_TX); + port->icount.tx++; + port->x_char = 0; + return; + } + + if ((uart_tx_stopped(port)) || (uart_circ_empty(xmit))) { + port->ops->stop_tx(port); + } else { + data_empty_count = (pci1xxxx_read_burst_status(port) & + UART_BST_STAT_TX_COUNT_MASK) >> 8; + do { + valid_byte_count = uart_circ_chars_pending(xmit); + + pci1xxxx_process_write_data(port, xmit, + &data_empty_count, + &valid_byte_count); + + port->icount.tx++; + if (uart_circ_empty(xmit)) + break; + } while (data_empty_count && valid_byte_count); + } + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(port); + + /* + * With RPM enabled, we have to wait until the FIFO is empty before + * the HW can go idle. So we get here once again with empty FIFO and + * disable the interrupt and RPM in __stop_tx() + */ + if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM)) + port->ops->stop_tx(port); +} + static int pci1xxxx_handle_irq(struct uart_port *port) { unsigned long flags; @@ -359,6 +495,9 @@ static int pci1xxxx_handle_irq(struct uart_port *port) if (status & UART_BST_STAT_LSR_RX_MASK) pci1xxxx_rx_burst(port, status); + if (status & UART_BST_STAT_LSR_THRE) + pci1xxxx_tx_burst(port, status); + spin_unlock_irqrestore(&port->lock, flags); return 1; @@ -481,6 +620,17 @@ static int pci1xxxx_setup(struct pci_dev *pdev, port->port.flags |= UPF_FIXED_TYPE | UPF_SKIP_TEST; port->port.type = PORT_MCHP16550A; + /* + * 8250 core considers prescaller value to be always 16. + * The MCHP ports support downscaled mode and hence the + * functional UART clock can be lower, i.e. 62.5MHz, than + * software expects in order to support higher baud rates. + * Assign here 64MHz to support 4Mbps. + * + * The value itself is not really used anywhere except baud + * rate calculations, so we can mangle it as we wish. + */ + port->port.uartclk = 64 * HZ_PER_MHZ; port->port.set_termios = serial8250_do_set_termios; port->port.get_divisor = pci1xxxx_get_divisor; port->port.set_divisor = pci1xxxx_set_divisor; @@ -594,7 +744,6 @@ static int pci1xxxx_serial_probe(struct pci_dev *pdev, memset(&uart, 0, sizeof(uart)); uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; - uart.port.uartclk = UART_CLOCK_DEFAULT; uart.port.dev = dev; if (num_vectors == max_vec_reqd) |