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-rw-r--r--sound/soc/sunxi/Kconfig70
-rw-r--r--sound/soc/sunxi/Makefile9
-rw-r--r--sound/soc/sunxi/sun4i-codec.c1854
-rw-r--r--sound/soc/sunxi/sun4i-i2s.c1673
-rw-r--r--sound/soc/sunxi/sun4i-spdif.c734
-rw-r--r--sound/soc/sunxi/sun50i-codec-analog.c548
-rw-r--r--sound/soc/sunxi/sun50i-dmic.c403
-rw-r--r--sound/soc/sunxi/sun8i-adda-pr-regmap.c102
-rw-r--r--sound/soc/sunxi/sun8i-adda-pr-regmap.h7
-rw-r--r--sound/soc/sunxi/sun8i-codec-analog.c854
-rw-r--r--sound/soc/sunxi/sun8i-codec.c1393
11 files changed, 7647 insertions, 0 deletions
diff --git a/sound/soc/sunxi/Kconfig b/sound/soc/sunxi/Kconfig
new file mode 100644
index 000000000..1f18f016a
--- /dev/null
+++ b/sound/soc/sunxi/Kconfig
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-only
+menu "Allwinner SoC Audio support"
+ depends on ARCH_SUNXI || COMPILE_TEST
+
+config SND_SUN4I_CODEC
+ tristate "Allwinner A10 Codec Support"
+ select SND_SOC_GENERIC_DMAENGINE_PCM
+ select REGMAP_MMIO
+ help
+ Select Y or M to add support for the Codec embedded in the Allwinner
+ A10 and affiliated SoCs.
+
+config SND_SUN8I_CODEC
+ tristate "Allwinner SUN8I audio codec"
+ depends on OF
+ depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+ depends on COMMON_CLK
+ select REGMAP_MMIO
+ help
+ This option enables the digital part of the internal audio codec for
+ Allwinner sun8i SoC (and particularly A33).
+
+ Say Y or M if you want to add sun8i digital audio codec support.
+
+config SND_SUN8I_CODEC_ANALOG
+ tristate "Allwinner sun8i Codec Analog Controls Support"
+ depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+ select SND_SUN8I_ADDA_PR_REGMAP
+ help
+ Say Y or M if you want to add support for the analog controls for
+ the codec embedded in newer Allwinner SoCs.
+
+config SND_SUN50I_CODEC_ANALOG
+ tristate "Allwinner sun50i Codec Analog Controls Support"
+ depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+ select SND_SUN8I_ADDA_PR_REGMAP
+ help
+ Say Y or M if you want to add support for the analog controls for
+ the codec embedded in Allwinner A64 SoC.
+
+config SND_SUN4I_I2S
+ tristate "Allwinner A10 I2S Support"
+ select SND_SOC_GENERIC_DMAENGINE_PCM
+ select REGMAP_MMIO
+ help
+ Say Y or M if you want to add support for codecs attached to
+ the Allwinner A10 I2S. You will also need to select the
+ individual machine drivers to support below.
+
+config SND_SUN4I_SPDIF
+ tristate "Allwinner A10 SPDIF Support"
+ depends on OF
+ select SND_SOC_GENERIC_DMAENGINE_PCM
+ select REGMAP_MMIO
+ help
+ Say Y or M to add support for the S/PDIF audio block in the Allwinner
+ A10 and affiliated SoCs.
+
+config SND_SUN50I_DMIC
+ tristate "Allwinner H6 DMIC Support"
+ select SND_SOC_GENERIC_DMAENGINE_PCM
+ help
+ Say Y or M to add support for the DMIC audio block in the Allwinner
+ H6 and affiliated SoCs.
+
+config SND_SUN8I_ADDA_PR_REGMAP
+ tristate
+ select REGMAP
+
+endmenu
diff --git a/sound/soc/sunxi/Makefile b/sound/soc/sunxi/Makefile
new file mode 100644
index 000000000..4483fe9c9
--- /dev/null
+++ b/sound/soc/sunxi/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_SND_SUN4I_CODEC) += sun4i-codec.o
+obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s.o
+obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o
+obj-$(CONFIG_SND_SUN8I_CODEC_ANALOG) += sun8i-codec-analog.o
+obj-$(CONFIG_SND_SUN50I_CODEC_ANALOG) += sun50i-codec-analog.o
+obj-$(CONFIG_SND_SUN8I_CODEC) += sun8i-codec.o
+obj-$(CONFIG_SND_SUN8I_ADDA_PR_REGMAP) += sun8i-adda-pr-regmap.o
+obj-$(CONFIG_SND_SUN50I_DMIC) += sun50i-dmic.o
diff --git a/sound/soc/sunxi/sun4i-codec.c b/sound/soc/sunxi/sun4i-codec.c
new file mode 100644
index 000000000..f0a5fd901
--- /dev/null
+++ b/sound/soc/sunxi/sun4i-codec.c
@@ -0,0 +1,1854 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2014 Emilio López <emilio@elopez.com.ar>
+ * Copyright 2014 Jon Smirl <jonsmirl@gmail.com>
+ * Copyright 2015 Maxime Ripard <maxime.ripard@free-electrons.com>
+ * Copyright 2015 Adam Sampson <ats@offog.org>
+ * Copyright 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * Based on the Allwinner SDK driver, released under the GPL.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/clk.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/gpio/consumer.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/tlv.h>
+#include <sound/initval.h>
+#include <sound/dmaengine_pcm.h>
+
+/* Codec DAC digital controls and FIFO registers */
+#define SUN4I_CODEC_DAC_DPC (0x00)
+#define SUN4I_CODEC_DAC_DPC_EN_DA (31)
+#define SUN4I_CODEC_DAC_DPC_DVOL (12)
+#define SUN4I_CODEC_DAC_FIFOC (0x04)
+#define SUN4I_CODEC_DAC_FIFOC_DAC_FS (29)
+#define SUN4I_CODEC_DAC_FIFOC_FIR_VERSION (28)
+#define SUN4I_CODEC_DAC_FIFOC_SEND_LASAT (26)
+#define SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE (24)
+#define SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT (21)
+#define SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL (8)
+#define SUN4I_CODEC_DAC_FIFOC_MONO_EN (6)
+#define SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS (5)
+#define SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN (4)
+#define SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH (0)
+#define SUN4I_CODEC_DAC_FIFOS (0x08)
+#define SUN4I_CODEC_DAC_TXDATA (0x0c)
+
+/* Codec DAC side analog signal controls */
+#define SUN4I_CODEC_DAC_ACTL (0x10)
+#define SUN4I_CODEC_DAC_ACTL_DACAENR (31)
+#define SUN4I_CODEC_DAC_ACTL_DACAENL (30)
+#define SUN4I_CODEC_DAC_ACTL_MIXEN (29)
+#define SUN4I_CODEC_DAC_ACTL_LNG (26)
+#define SUN4I_CODEC_DAC_ACTL_FMG (23)
+#define SUN4I_CODEC_DAC_ACTL_MICG (20)
+#define SUN4I_CODEC_DAC_ACTL_LLNS (19)
+#define SUN4I_CODEC_DAC_ACTL_RLNS (18)
+#define SUN4I_CODEC_DAC_ACTL_LFMS (17)
+#define SUN4I_CODEC_DAC_ACTL_RFMS (16)
+#define SUN4I_CODEC_DAC_ACTL_LDACLMIXS (15)
+#define SUN4I_CODEC_DAC_ACTL_RDACRMIXS (14)
+#define SUN4I_CODEC_DAC_ACTL_LDACRMIXS (13)
+#define SUN4I_CODEC_DAC_ACTL_MIC1LS (12)
+#define SUN4I_CODEC_DAC_ACTL_MIC1RS (11)
+#define SUN4I_CODEC_DAC_ACTL_MIC2LS (10)
+#define SUN4I_CODEC_DAC_ACTL_MIC2RS (9)
+#define SUN4I_CODEC_DAC_ACTL_DACPAS (8)
+#define SUN4I_CODEC_DAC_ACTL_MIXPAS (7)
+#define SUN4I_CODEC_DAC_ACTL_PA_MUTE (6)
+#define SUN4I_CODEC_DAC_ACTL_PA_VOL (0)
+#define SUN4I_CODEC_DAC_TUNE (0x14)
+#define SUN4I_CODEC_DAC_DEBUG (0x18)
+
+/* Codec ADC digital controls and FIFO registers */
+#define SUN4I_CODEC_ADC_FIFOC (0x1c)
+#define SUN4I_CODEC_ADC_FIFOC_ADC_FS (29)
+#define SUN4I_CODEC_ADC_FIFOC_EN_AD (28)
+#define SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE (24)
+#define SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL (8)
+#define SUN4I_CODEC_ADC_FIFOC_MONO_EN (7)
+#define SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS (6)
+#define SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN (4)
+#define SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH (0)
+#define SUN4I_CODEC_ADC_FIFOS (0x20)
+#define SUN4I_CODEC_ADC_RXDATA (0x24)
+
+/* Codec ADC side analog signal controls */
+#define SUN4I_CODEC_ADC_ACTL (0x28)
+#define SUN4I_CODEC_ADC_ACTL_ADC_R_EN (31)
+#define SUN4I_CODEC_ADC_ACTL_ADC_L_EN (30)
+#define SUN4I_CODEC_ADC_ACTL_PREG1EN (29)
+#define SUN4I_CODEC_ADC_ACTL_PREG2EN (28)
+#define SUN4I_CODEC_ADC_ACTL_VMICEN (27)
+#define SUN4I_CODEC_ADC_ACTL_PREG1 (25)
+#define SUN4I_CODEC_ADC_ACTL_PREG2 (23)
+#define SUN4I_CODEC_ADC_ACTL_VADCG (20)
+#define SUN4I_CODEC_ADC_ACTL_ADCIS (17)
+#define SUN4I_CODEC_ADC_ACTL_LNPREG (13)
+#define SUN4I_CODEC_ADC_ACTL_PA_EN (4)
+#define SUN4I_CODEC_ADC_ACTL_DDE (3)
+#define SUN4I_CODEC_ADC_DEBUG (0x2c)
+
+/* FIFO counters */
+#define SUN4I_CODEC_DAC_TXCNT (0x30)
+#define SUN4I_CODEC_ADC_RXCNT (0x34)
+
+/* Calibration register (sun7i only) */
+#define SUN7I_CODEC_AC_DAC_CAL (0x38)
+
+/* Microphone controls (sun7i only) */
+#define SUN7I_CODEC_AC_MIC_PHONE_CAL (0x3c)
+
+#define SUN7I_CODEC_AC_MIC_PHONE_CAL_PREG1 (29)
+#define SUN7I_CODEC_AC_MIC_PHONE_CAL_PREG2 (26)
+
+/*
+ * sun6i specific registers
+ *
+ * sun6i shares the same digital control and FIFO registers as sun4i,
+ * but only the DAC digital controls are at the same offset. The others
+ * have been moved around to accommodate extra analog controls.
+ */
+
+/* Codec DAC digital controls and FIFO registers */
+#define SUN6I_CODEC_ADC_FIFOC (0x10)
+#define SUN6I_CODEC_ADC_FIFOC_EN_AD (28)
+#define SUN6I_CODEC_ADC_FIFOS (0x14)
+#define SUN6I_CODEC_ADC_RXDATA (0x18)
+
+/* Output mixer and gain controls */
+#define SUN6I_CODEC_OM_DACA_CTRL (0x20)
+#define SUN6I_CODEC_OM_DACA_CTRL_DACAREN (31)
+#define SUN6I_CODEC_OM_DACA_CTRL_DACALEN (30)
+#define SUN6I_CODEC_OM_DACA_CTRL_RMIXEN (29)
+#define SUN6I_CODEC_OM_DACA_CTRL_LMIXEN (28)
+#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC1 (23)
+#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC2 (22)
+#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_PHONE (21)
+#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_PHONEP (20)
+#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_LINEINR (19)
+#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACR (18)
+#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACL (17)
+#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC1 (16)
+#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC2 (15)
+#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_PHONE (14)
+#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_PHONEN (13)
+#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_LINEINL (12)
+#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACL (11)
+#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACR (10)
+#define SUN6I_CODEC_OM_DACA_CTRL_RHPIS (9)
+#define SUN6I_CODEC_OM_DACA_CTRL_LHPIS (8)
+#define SUN6I_CODEC_OM_DACA_CTRL_RHPPAMUTE (7)
+#define SUN6I_CODEC_OM_DACA_CTRL_LHPPAMUTE (6)
+#define SUN6I_CODEC_OM_DACA_CTRL_HPVOL (0)
+#define SUN6I_CODEC_OM_PA_CTRL (0x24)
+#define SUN6I_CODEC_OM_PA_CTRL_HPPAEN (31)
+#define SUN6I_CODEC_OM_PA_CTRL_HPCOM_CTL (29)
+#define SUN6I_CODEC_OM_PA_CTRL_COMPTEN (28)
+#define SUN6I_CODEC_OM_PA_CTRL_MIC1G (15)
+#define SUN6I_CODEC_OM_PA_CTRL_MIC2G (12)
+#define SUN6I_CODEC_OM_PA_CTRL_LINEING (9)
+#define SUN6I_CODEC_OM_PA_CTRL_PHONEG (6)
+#define SUN6I_CODEC_OM_PA_CTRL_PHONEPG (3)
+#define SUN6I_CODEC_OM_PA_CTRL_PHONENG (0)
+
+/* Microphone, line out and phone out controls */
+#define SUN6I_CODEC_MIC_CTRL (0x28)
+#define SUN6I_CODEC_MIC_CTRL_HBIASEN (31)
+#define SUN6I_CODEC_MIC_CTRL_MBIASEN (30)
+#define SUN6I_CODEC_MIC_CTRL_MIC1AMPEN (28)
+#define SUN6I_CODEC_MIC_CTRL_MIC1BOOST (25)
+#define SUN6I_CODEC_MIC_CTRL_MIC2AMPEN (24)
+#define SUN6I_CODEC_MIC_CTRL_MIC2BOOST (21)
+#define SUN6I_CODEC_MIC_CTRL_MIC2SLT (20)
+#define SUN6I_CODEC_MIC_CTRL_LINEOUTLEN (19)
+#define SUN6I_CODEC_MIC_CTRL_LINEOUTREN (18)
+#define SUN6I_CODEC_MIC_CTRL_LINEOUTLSRC (17)
+#define SUN6I_CODEC_MIC_CTRL_LINEOUTRSRC (16)
+#define SUN6I_CODEC_MIC_CTRL_LINEOUTVC (11)
+#define SUN6I_CODEC_MIC_CTRL_PHONEPREG (8)
+
+/* ADC mixer controls */
+#define SUN6I_CODEC_ADC_ACTL (0x2c)
+#define SUN6I_CODEC_ADC_ACTL_ADCREN (31)
+#define SUN6I_CODEC_ADC_ACTL_ADCLEN (30)
+#define SUN6I_CODEC_ADC_ACTL_ADCRG (27)
+#define SUN6I_CODEC_ADC_ACTL_ADCLG (24)
+#define SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC1 (13)
+#define SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC2 (12)
+#define SUN6I_CODEC_ADC_ACTL_RADCMIX_PHONE (11)
+#define SUN6I_CODEC_ADC_ACTL_RADCMIX_PHONEP (10)
+#define SUN6I_CODEC_ADC_ACTL_RADCMIX_LINEINR (9)
+#define SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXR (8)
+#define SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXL (7)
+#define SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC1 (6)
+#define SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC2 (5)
+#define SUN6I_CODEC_ADC_ACTL_LADCMIX_PHONE (4)
+#define SUN6I_CODEC_ADC_ACTL_LADCMIX_PHONEN (3)
+#define SUN6I_CODEC_ADC_ACTL_LADCMIX_LINEINL (2)
+#define SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXL (1)
+#define SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXR (0)
+
+/* Analog performance tuning controls */
+#define SUN6I_CODEC_ADDA_TUNE (0x30)
+
+/* Calibration controls */
+#define SUN6I_CODEC_CALIBRATION (0x34)
+
+/* FIFO counters */
+#define SUN6I_CODEC_DAC_TXCNT (0x40)
+#define SUN6I_CODEC_ADC_RXCNT (0x44)
+
+/* headset jack detection and button support registers */
+#define SUN6I_CODEC_HMIC_CTL (0x50)
+#define SUN6I_CODEC_HMIC_DATA (0x54)
+
+/* TODO sun6i DAP (Digital Audio Processing) bits */
+
+/* FIFO counters moved on A23 */
+#define SUN8I_A23_CODEC_DAC_TXCNT (0x1c)
+#define SUN8I_A23_CODEC_ADC_RXCNT (0x20)
+
+/* TX FIFO moved on H3 */
+#define SUN8I_H3_CODEC_DAC_TXDATA (0x20)
+#define SUN8I_H3_CODEC_DAC_DBG (0x48)
+#define SUN8I_H3_CODEC_ADC_DBG (0x4c)
+
+/* TODO H3 DAP (Digital Audio Processing) bits */
+
+struct sun4i_codec {
+ struct device *dev;
+ struct regmap *regmap;
+ struct clk *clk_apb;
+ struct clk *clk_module;
+ struct reset_control *rst;
+ struct gpio_desc *gpio_pa;
+
+ /* ADC_FIFOC register is at different offset on different SoCs */
+ struct regmap_field *reg_adc_fifoc;
+
+ struct snd_dmaengine_dai_dma_data capture_dma_data;
+ struct snd_dmaengine_dai_dma_data playback_dma_data;
+};
+
+static void sun4i_codec_start_playback(struct sun4i_codec *scodec)
+{
+ /* Flush TX FIFO */
+ regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+ BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
+
+ /* Enable DAC DRQ */
+ regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+ BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
+}
+
+static void sun4i_codec_stop_playback(struct sun4i_codec *scodec)
+{
+ /* Disable DAC DRQ */
+ regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+ BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
+}
+
+static void sun4i_codec_start_capture(struct sun4i_codec *scodec)
+{
+ /* Enable ADC DRQ */
+ regmap_field_set_bits(scodec->reg_adc_fifoc,
+ BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN));
+}
+
+static void sun4i_codec_stop_capture(struct sun4i_codec *scodec)
+{
+ /* Disable ADC DRQ */
+ regmap_field_clear_bits(scodec->reg_adc_fifoc,
+ BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN));
+}
+
+static int sun4i_codec_trigger(struct snd_pcm_substream *substream, int cmd,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ sun4i_codec_start_playback(scodec);
+ else
+ sun4i_codec_start_capture(scodec);
+ break;
+
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ sun4i_codec_stop_playback(scodec);
+ else
+ sun4i_codec_stop_capture(scodec);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int sun4i_codec_prepare_capture(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
+
+
+ /* Flush RX FIFO */
+ regmap_field_set_bits(scodec->reg_adc_fifoc,
+ BIT(SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH));
+
+
+ /* Set RX FIFO trigger level */
+ regmap_field_update_bits(scodec->reg_adc_fifoc,
+ 0xf << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
+ 0x7 << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL);
+
+ /*
+ * FIXME: Undocumented in the datasheet, but
+ * Allwinner's code mentions that it is
+ * related to microphone gain
+ */
+ if (of_device_is_compatible(scodec->dev->of_node,
+ "allwinner,sun4i-a10-codec") ||
+ of_device_is_compatible(scodec->dev->of_node,
+ "allwinner,sun7i-a20-codec")) {
+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_ADC_ACTL,
+ 0x3 << 25,
+ 0x1 << 25);
+ }
+
+ if (of_device_is_compatible(scodec->dev->of_node,
+ "allwinner,sun7i-a20-codec"))
+ /* FIXME: Undocumented bits */
+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_TUNE,
+ 0x3 << 8,
+ 0x1 << 8);
+
+ return 0;
+}
+
+static int sun4i_codec_prepare_playback(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
+ u32 val;
+
+ /* Flush the TX FIFO */
+ regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+ BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
+
+ /* Set TX FIFO Empty Trigger Level */
+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+ 0x3f << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL,
+ 0xf << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL);
+
+ if (substream->runtime->rate > 32000)
+ /* Use 64 bits FIR filter */
+ val = 0;
+ else
+ /* Use 32 bits FIR filter */
+ val = BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION);
+
+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+ BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION),
+ val);
+
+ /* Send zeros when we have an underrun */
+ regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+ BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT));
+
+ return 0;
+};
+
+static int sun4i_codec_prepare(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ return sun4i_codec_prepare_playback(substream, dai);
+
+ return sun4i_codec_prepare_capture(substream, dai);
+}
+
+static unsigned long sun4i_codec_get_mod_freq(struct snd_pcm_hw_params *params)
+{
+ unsigned int rate = params_rate(params);
+
+ switch (rate) {
+ case 176400:
+ case 88200:
+ case 44100:
+ case 33075:
+ case 22050:
+ case 14700:
+ case 11025:
+ case 7350:
+ return 22579200;
+
+ case 192000:
+ case 96000:
+ case 48000:
+ case 32000:
+ case 24000:
+ case 16000:
+ case 12000:
+ case 8000:
+ return 24576000;
+
+ default:
+ return 0;
+ }
+}
+
+static int sun4i_codec_get_hw_rate(struct snd_pcm_hw_params *params)
+{
+ unsigned int rate = params_rate(params);
+
+ switch (rate) {
+ case 192000:
+ case 176400:
+ return 6;
+
+ case 96000:
+ case 88200:
+ return 7;
+
+ case 48000:
+ case 44100:
+ return 0;
+
+ case 32000:
+ case 33075:
+ return 1;
+
+ case 24000:
+ case 22050:
+ return 2;
+
+ case 16000:
+ case 14700:
+ return 3;
+
+ case 12000:
+ case 11025:
+ return 4;
+
+ case 8000:
+ case 7350:
+ return 5;
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static int sun4i_codec_hw_params_capture(struct sun4i_codec *scodec,
+ struct snd_pcm_hw_params *params,
+ unsigned int hwrate)
+{
+ /* Set ADC sample rate */
+ regmap_field_update_bits(scodec->reg_adc_fifoc,
+ 7 << SUN4I_CODEC_ADC_FIFOC_ADC_FS,
+ hwrate << SUN4I_CODEC_ADC_FIFOC_ADC_FS);
+
+ /* Set the number of channels we want to use */
+ if (params_channels(params) == 1)
+ regmap_field_set_bits(scodec->reg_adc_fifoc,
+ BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN));
+ else
+ regmap_field_clear_bits(scodec->reg_adc_fifoc,
+ BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN));
+
+ /* Set the number of sample bits to either 16 or 24 bits */
+ if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) {
+ regmap_field_set_bits(scodec->reg_adc_fifoc,
+ BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS));
+
+ regmap_field_clear_bits(scodec->reg_adc_fifoc,
+ BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE));
+
+ scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ } else {
+ regmap_field_clear_bits(scodec->reg_adc_fifoc,
+ BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS));
+
+ /* Fill most significant bits with valid data MSB */
+ regmap_field_set_bits(scodec->reg_adc_fifoc,
+ BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE));
+
+ scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+ }
+
+ return 0;
+}
+
+static int sun4i_codec_hw_params_playback(struct sun4i_codec *scodec,
+ struct snd_pcm_hw_params *params,
+ unsigned int hwrate)
+{
+ u32 val;
+
+ /* Set DAC sample rate */
+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+ 7 << SUN4I_CODEC_DAC_FIFOC_DAC_FS,
+ hwrate << SUN4I_CODEC_DAC_FIFOC_DAC_FS);
+
+ /* Set the number of channels we want to use */
+ if (params_channels(params) == 1)
+ val = BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN);
+ else
+ val = 0;
+
+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+ BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN),
+ val);
+
+ /* Set the number of sample bits to either 16 or 24 bits */
+ if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) {
+ regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+ BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
+
+ /* Set TX FIFO mode to padding the LSBs with 0 */
+ regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+ BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
+
+ scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ } else {
+ regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+ BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
+
+ /* Set TX FIFO mode to repeat the MSB */
+ regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+ BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
+
+ scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+ }
+
+ return 0;
+}
+
+static int sun4i_codec_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
+ unsigned long clk_freq;
+ int ret, hwrate;
+
+ clk_freq = sun4i_codec_get_mod_freq(params);
+ if (!clk_freq)
+ return -EINVAL;
+
+ ret = clk_set_rate(scodec->clk_module, clk_freq);
+ if (ret)
+ return ret;
+
+ hwrate = sun4i_codec_get_hw_rate(params);
+ if (hwrate < 0)
+ return hwrate;
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ return sun4i_codec_hw_params_playback(scodec, params,
+ hwrate);
+
+ return sun4i_codec_hw_params_capture(scodec, params,
+ hwrate);
+}
+
+
+static unsigned int sun4i_codec_src_rates[] = {
+ 8000, 11025, 12000, 16000, 22050, 24000, 32000,
+ 44100, 48000, 96000, 192000
+};
+
+
+static struct snd_pcm_hw_constraint_list sun4i_codec_constraints = {
+ .count = ARRAY_SIZE(sun4i_codec_src_rates),
+ .list = sun4i_codec_src_rates,
+};
+
+
+static int sun4i_codec_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
+
+ snd_pcm_hw_constraint_list(substream->runtime, 0,
+ SNDRV_PCM_HW_PARAM_RATE, &sun4i_codec_constraints);
+
+ /*
+ * Stop issuing DRQ when we have room for less than 16 samples
+ * in our TX FIFO
+ */
+ regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+ 3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT);
+
+ return clk_prepare_enable(scodec->clk_module);
+}
+
+static void sun4i_codec_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
+
+ clk_disable_unprepare(scodec->clk_module);
+}
+
+static const struct snd_soc_dai_ops sun4i_codec_dai_ops = {
+ .startup = sun4i_codec_startup,
+ .shutdown = sun4i_codec_shutdown,
+ .trigger = sun4i_codec_trigger,
+ .hw_params = sun4i_codec_hw_params,
+ .prepare = sun4i_codec_prepare,
+};
+
+static struct snd_soc_dai_driver sun4i_codec_dai = {
+ .name = "Codec",
+ .ops = &sun4i_codec_dai_ops,
+ .playback = {
+ .stream_name = "Codec Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ .rates = SNDRV_PCM_RATE_CONTINUOUS,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE |
+ SNDRV_PCM_FMTBIT_S32_LE,
+ .sig_bits = 24,
+ },
+ .capture = {
+ .stream_name = "Codec Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ .rates = SNDRV_PCM_RATE_CONTINUOUS,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE |
+ SNDRV_PCM_FMTBIT_S32_LE,
+ .sig_bits = 24,
+ },
+};
+
+/*** sun4i Codec ***/
+static const struct snd_kcontrol_new sun4i_codec_pa_mute =
+ SOC_DAPM_SINGLE("Switch", SUN4I_CODEC_DAC_ACTL,
+ SUN4I_CODEC_DAC_ACTL_PA_MUTE, 1, 0);
+
+static DECLARE_TLV_DB_SCALE(sun4i_codec_pa_volume_scale, -6300, 100, 1);
+static DECLARE_TLV_DB_SCALE(sun4i_codec_linein_loopback_gain_scale, -150, 150,
+ 0);
+static DECLARE_TLV_DB_SCALE(sun4i_codec_linein_preamp_gain_scale, -1200, 300,
+ 0);
+static DECLARE_TLV_DB_SCALE(sun4i_codec_fmin_loopback_gain_scale, -450, 150,
+ 0);
+static DECLARE_TLV_DB_SCALE(sun4i_codec_micin_loopback_gain_scale, -450, 150,
+ 0);
+static DECLARE_TLV_DB_RANGE(sun4i_codec_micin_preamp_gain_scale,
+ 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
+ 1, 7, TLV_DB_SCALE_ITEM(3500, 300, 0));
+static DECLARE_TLV_DB_RANGE(sun7i_codec_micin_preamp_gain_scale,
+ 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
+ 1, 7, TLV_DB_SCALE_ITEM(2400, 300, 0));
+
+static const struct snd_kcontrol_new sun4i_codec_controls[] = {
+ SOC_SINGLE_TLV("Power Amplifier Volume", SUN4I_CODEC_DAC_ACTL,
+ SUN4I_CODEC_DAC_ACTL_PA_VOL, 0x3F, 0,
+ sun4i_codec_pa_volume_scale),
+ SOC_SINGLE_TLV("Line Playback Volume", SUN4I_CODEC_DAC_ACTL,
+ SUN4I_CODEC_DAC_ACTL_LNG, 1, 0,
+ sun4i_codec_linein_loopback_gain_scale),
+ SOC_SINGLE_TLV("Line Boost Volume", SUN4I_CODEC_ADC_ACTL,
+ SUN4I_CODEC_ADC_ACTL_LNPREG, 7, 0,
+ sun4i_codec_linein_preamp_gain_scale),
+ SOC_SINGLE_TLV("FM Playback Volume", SUN4I_CODEC_DAC_ACTL,
+ SUN4I_CODEC_DAC_ACTL_FMG, 3, 0,
+ sun4i_codec_fmin_loopback_gain_scale),
+ SOC_SINGLE_TLV("Mic Playback Volume", SUN4I_CODEC_DAC_ACTL,
+ SUN4I_CODEC_DAC_ACTL_MICG, 7, 0,
+ sun4i_codec_micin_loopback_gain_scale),
+ SOC_SINGLE_TLV("Mic1 Boost Volume", SUN4I_CODEC_ADC_ACTL,
+ SUN4I_CODEC_ADC_ACTL_PREG1, 3, 0,
+ sun4i_codec_micin_preamp_gain_scale),
+ SOC_SINGLE_TLV("Mic2 Boost Volume", SUN4I_CODEC_ADC_ACTL,
+ SUN4I_CODEC_ADC_ACTL_PREG2, 3, 0,
+ sun4i_codec_micin_preamp_gain_scale),
+};
+
+static const struct snd_kcontrol_new sun7i_codec_controls[] = {
+ SOC_SINGLE_TLV("Power Amplifier Volume", SUN4I_CODEC_DAC_ACTL,
+ SUN4I_CODEC_DAC_ACTL_PA_VOL, 0x3F, 0,
+ sun4i_codec_pa_volume_scale),
+ SOC_SINGLE_TLV("Line Playback Volume", SUN4I_CODEC_DAC_ACTL,
+ SUN4I_CODEC_DAC_ACTL_LNG, 1, 0,
+ sun4i_codec_linein_loopback_gain_scale),
+ SOC_SINGLE_TLV("Line Boost Volume", SUN4I_CODEC_ADC_ACTL,
+ SUN4I_CODEC_ADC_ACTL_LNPREG, 7, 0,
+ sun4i_codec_linein_preamp_gain_scale),
+ SOC_SINGLE_TLV("FM Playback Volume", SUN4I_CODEC_DAC_ACTL,
+ SUN4I_CODEC_DAC_ACTL_FMG, 3, 0,
+ sun4i_codec_fmin_loopback_gain_scale),
+ SOC_SINGLE_TLV("Mic Playback Volume", SUN4I_CODEC_DAC_ACTL,
+ SUN4I_CODEC_DAC_ACTL_MICG, 7, 0,
+ sun4i_codec_micin_loopback_gain_scale),
+ SOC_SINGLE_TLV("Mic1 Boost Volume", SUN7I_CODEC_AC_MIC_PHONE_CAL,
+ SUN7I_CODEC_AC_MIC_PHONE_CAL_PREG1, 7, 0,
+ sun7i_codec_micin_preamp_gain_scale),
+ SOC_SINGLE_TLV("Mic2 Boost Volume", SUN7I_CODEC_AC_MIC_PHONE_CAL,
+ SUN7I_CODEC_AC_MIC_PHONE_CAL_PREG2, 7, 0,
+ sun7i_codec_micin_preamp_gain_scale),
+};
+
+static const struct snd_kcontrol_new sun4i_codec_mixer_controls[] = {
+ SOC_DAPM_SINGLE("Left Mixer Left DAC Playback Switch",
+ SUN4I_CODEC_DAC_ACTL, SUN4I_CODEC_DAC_ACTL_LDACLMIXS,
+ 1, 0),
+ SOC_DAPM_SINGLE("Right Mixer Right DAC Playback Switch",
+ SUN4I_CODEC_DAC_ACTL, SUN4I_CODEC_DAC_ACTL_RDACRMIXS,
+ 1, 0),
+ SOC_DAPM_SINGLE("Right Mixer Left DAC Playback Switch",
+ SUN4I_CODEC_DAC_ACTL,
+ SUN4I_CODEC_DAC_ACTL_LDACRMIXS, 1, 0),
+ SOC_DAPM_DOUBLE("Line Playback Switch", SUN4I_CODEC_DAC_ACTL,
+ SUN4I_CODEC_DAC_ACTL_LLNS,
+ SUN4I_CODEC_DAC_ACTL_RLNS, 1, 0),
+ SOC_DAPM_DOUBLE("FM Playback Switch", SUN4I_CODEC_DAC_ACTL,
+ SUN4I_CODEC_DAC_ACTL_LFMS,
+ SUN4I_CODEC_DAC_ACTL_RFMS, 1, 0),
+ SOC_DAPM_DOUBLE("Mic1 Playback Switch", SUN4I_CODEC_DAC_ACTL,
+ SUN4I_CODEC_DAC_ACTL_MIC1LS,
+ SUN4I_CODEC_DAC_ACTL_MIC1RS, 1, 0),
+ SOC_DAPM_DOUBLE("Mic2 Playback Switch", SUN4I_CODEC_DAC_ACTL,
+ SUN4I_CODEC_DAC_ACTL_MIC2LS,
+ SUN4I_CODEC_DAC_ACTL_MIC2RS, 1, 0),
+};
+
+static const struct snd_kcontrol_new sun4i_codec_pa_mixer_controls[] = {
+ SOC_DAPM_SINGLE("DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
+ SUN4I_CODEC_DAC_ACTL_DACPAS, 1, 0),
+ SOC_DAPM_SINGLE("Mixer Playback Switch", SUN4I_CODEC_DAC_ACTL,
+ SUN4I_CODEC_DAC_ACTL_MIXPAS, 1, 0),
+};
+
+static const struct snd_soc_dapm_widget sun4i_codec_codec_dapm_widgets[] = {
+ /* Digital parts of the ADCs */
+ SND_SOC_DAPM_SUPPLY("ADC", SUN4I_CODEC_ADC_FIFOC,
+ SUN4I_CODEC_ADC_FIFOC_EN_AD, 0,
+ NULL, 0),
+
+ /* Digital parts of the DACs */
+ SND_SOC_DAPM_SUPPLY("DAC", SUN4I_CODEC_DAC_DPC,
+ SUN4I_CODEC_DAC_DPC_EN_DA, 0,
+ NULL, 0),
+
+ /* Analog parts of the ADCs */
+ SND_SOC_DAPM_ADC("Left ADC", "Codec Capture", SUN4I_CODEC_ADC_ACTL,
+ SUN4I_CODEC_ADC_ACTL_ADC_L_EN, 0),
+ SND_SOC_DAPM_ADC("Right ADC", "Codec Capture", SUN4I_CODEC_ADC_ACTL,
+ SUN4I_CODEC_ADC_ACTL_ADC_R_EN, 0),
+
+ /* Analog parts of the DACs */
+ SND_SOC_DAPM_DAC("Left DAC", "Codec Playback", SUN4I_CODEC_DAC_ACTL,
+ SUN4I_CODEC_DAC_ACTL_DACAENL, 0),
+ SND_SOC_DAPM_DAC("Right DAC", "Codec Playback", SUN4I_CODEC_DAC_ACTL,
+ SUN4I_CODEC_DAC_ACTL_DACAENR, 0),
+
+ /* Mixers */
+ SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
+ sun4i_codec_mixer_controls,
+ ARRAY_SIZE(sun4i_codec_mixer_controls)),
+ SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
+ sun4i_codec_mixer_controls,
+ ARRAY_SIZE(sun4i_codec_mixer_controls)),
+
+ /* Global Mixer Enable */
+ SND_SOC_DAPM_SUPPLY("Mixer Enable", SUN4I_CODEC_DAC_ACTL,
+ SUN4I_CODEC_DAC_ACTL_MIXEN, 0, NULL, 0),
+
+ /* VMIC */
+ SND_SOC_DAPM_SUPPLY("VMIC", SUN4I_CODEC_ADC_ACTL,
+ SUN4I_CODEC_ADC_ACTL_VMICEN, 0, NULL, 0),
+
+ /* Mic Pre-Amplifiers */
+ SND_SOC_DAPM_PGA("MIC1 Pre-Amplifier", SUN4I_CODEC_ADC_ACTL,
+ SUN4I_CODEC_ADC_ACTL_PREG1EN, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("MIC2 Pre-Amplifier", SUN4I_CODEC_ADC_ACTL,
+ SUN4I_CODEC_ADC_ACTL_PREG2EN, 0, NULL, 0),
+
+ /* Power Amplifier */
+ SND_SOC_DAPM_MIXER("Power Amplifier", SUN4I_CODEC_ADC_ACTL,
+ SUN4I_CODEC_ADC_ACTL_PA_EN, 0,
+ sun4i_codec_pa_mixer_controls,
+ ARRAY_SIZE(sun4i_codec_pa_mixer_controls)),
+ SND_SOC_DAPM_SWITCH("Power Amplifier Mute", SND_SOC_NOPM, 0, 0,
+ &sun4i_codec_pa_mute),
+
+ SND_SOC_DAPM_INPUT("Line Right"),
+ SND_SOC_DAPM_INPUT("Line Left"),
+ SND_SOC_DAPM_INPUT("FM Right"),
+ SND_SOC_DAPM_INPUT("FM Left"),
+ SND_SOC_DAPM_INPUT("Mic1"),
+ SND_SOC_DAPM_INPUT("Mic2"),
+
+ SND_SOC_DAPM_OUTPUT("HP Right"),
+ SND_SOC_DAPM_OUTPUT("HP Left"),
+};
+
+static const struct snd_soc_dapm_route sun4i_codec_codec_dapm_routes[] = {
+ /* Left ADC / DAC Routes */
+ { "Left ADC", NULL, "ADC" },
+ { "Left DAC", NULL, "DAC" },
+
+ /* Right ADC / DAC Routes */
+ { "Right ADC", NULL, "ADC" },
+ { "Right DAC", NULL, "DAC" },
+
+ /* Right Mixer Routes */
+ { "Right Mixer", NULL, "Mixer Enable" },
+ { "Right Mixer", "Right Mixer Left DAC Playback Switch", "Left DAC" },
+ { "Right Mixer", "Right Mixer Right DAC Playback Switch", "Right DAC" },
+ { "Right Mixer", "Line Playback Switch", "Line Right" },
+ { "Right Mixer", "FM Playback Switch", "FM Right" },
+ { "Right Mixer", "Mic1 Playback Switch", "MIC1 Pre-Amplifier" },
+ { "Right Mixer", "Mic2 Playback Switch", "MIC2 Pre-Amplifier" },
+
+ /* Left Mixer Routes */
+ { "Left Mixer", NULL, "Mixer Enable" },
+ { "Left Mixer", "Left Mixer Left DAC Playback Switch", "Left DAC" },
+ { "Left Mixer", "Line Playback Switch", "Line Left" },
+ { "Left Mixer", "FM Playback Switch", "FM Left" },
+ { "Left Mixer", "Mic1 Playback Switch", "MIC1 Pre-Amplifier" },
+ { "Left Mixer", "Mic2 Playback Switch", "MIC2 Pre-Amplifier" },
+
+ /* Power Amplifier Routes */
+ { "Power Amplifier", "Mixer Playback Switch", "Left Mixer" },
+ { "Power Amplifier", "Mixer Playback Switch", "Right Mixer" },
+ { "Power Amplifier", "DAC Playback Switch", "Left DAC" },
+ { "Power Amplifier", "DAC Playback Switch", "Right DAC" },
+
+ /* Headphone Output Routes */
+ { "Power Amplifier Mute", "Switch", "Power Amplifier" },
+ { "HP Right", NULL, "Power Amplifier Mute" },
+ { "HP Left", NULL, "Power Amplifier Mute" },
+
+ /* Mic1 Routes */
+ { "Left ADC", NULL, "MIC1 Pre-Amplifier" },
+ { "Right ADC", NULL, "MIC1 Pre-Amplifier" },
+ { "MIC1 Pre-Amplifier", NULL, "Mic1"},
+ { "Mic1", NULL, "VMIC" },
+
+ /* Mic2 Routes */
+ { "Left ADC", NULL, "MIC2 Pre-Amplifier" },
+ { "Right ADC", NULL, "MIC2 Pre-Amplifier" },
+ { "MIC2 Pre-Amplifier", NULL, "Mic2"},
+ { "Mic2", NULL, "VMIC" },
+};
+
+static const struct snd_soc_component_driver sun4i_codec_codec = {
+ .controls = sun4i_codec_controls,
+ .num_controls = ARRAY_SIZE(sun4i_codec_controls),
+ .dapm_widgets = sun4i_codec_codec_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(sun4i_codec_codec_dapm_widgets),
+ .dapm_routes = sun4i_codec_codec_dapm_routes,
+ .num_dapm_routes = ARRAY_SIZE(sun4i_codec_codec_dapm_routes),
+ .idle_bias_on = 1,
+ .use_pmdown_time = 1,
+ .endianness = 1,
+};
+
+static const struct snd_soc_component_driver sun7i_codec_codec = {
+ .controls = sun7i_codec_controls,
+ .num_controls = ARRAY_SIZE(sun7i_codec_controls),
+ .dapm_widgets = sun4i_codec_codec_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(sun4i_codec_codec_dapm_widgets),
+ .dapm_routes = sun4i_codec_codec_dapm_routes,
+ .num_dapm_routes = ARRAY_SIZE(sun4i_codec_codec_dapm_routes),
+ .idle_bias_on = 1,
+ .use_pmdown_time = 1,
+ .endianness = 1,
+};
+
+/*** sun6i Codec ***/
+
+/* mixer controls */
+static const struct snd_kcontrol_new sun6i_codec_mixer_controls[] = {
+ SOC_DAPM_DOUBLE("DAC Playback Switch",
+ SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACL,
+ SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACR, 1, 0),
+ SOC_DAPM_DOUBLE("DAC Reversed Playback Switch",
+ SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACR,
+ SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACL, 1, 0),
+ SOC_DAPM_DOUBLE("Line In Playback Switch",
+ SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_LMIX_LINEINL,
+ SUN6I_CODEC_OM_DACA_CTRL_RMIX_LINEINR, 1, 0),
+ SOC_DAPM_DOUBLE("Mic1 Playback Switch",
+ SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC1,
+ SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC1, 1, 0),
+ SOC_DAPM_DOUBLE("Mic2 Playback Switch",
+ SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC2,
+ SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC2, 1, 0),
+};
+
+/* ADC mixer controls */
+static const struct snd_kcontrol_new sun6i_codec_adc_mixer_controls[] = {
+ SOC_DAPM_DOUBLE("Mixer Capture Switch",
+ SUN6I_CODEC_ADC_ACTL,
+ SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXL,
+ SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXR, 1, 0),
+ SOC_DAPM_DOUBLE("Mixer Reversed Capture Switch",
+ SUN6I_CODEC_ADC_ACTL,
+ SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXR,
+ SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXL, 1, 0),
+ SOC_DAPM_DOUBLE("Line In Capture Switch",
+ SUN6I_CODEC_ADC_ACTL,
+ SUN6I_CODEC_ADC_ACTL_LADCMIX_LINEINL,
+ SUN6I_CODEC_ADC_ACTL_RADCMIX_LINEINR, 1, 0),
+ SOC_DAPM_DOUBLE("Mic1 Capture Switch",
+ SUN6I_CODEC_ADC_ACTL,
+ SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC1,
+ SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC1, 1, 0),
+ SOC_DAPM_DOUBLE("Mic2 Capture Switch",
+ SUN6I_CODEC_ADC_ACTL,
+ SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC2,
+ SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC2, 1, 0),
+};
+
+/* headphone controls */
+static const char * const sun6i_codec_hp_src_enum_text[] = {
+ "DAC", "Mixer",
+};
+
+static SOC_ENUM_DOUBLE_DECL(sun6i_codec_hp_src_enum,
+ SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_LHPIS,
+ SUN6I_CODEC_OM_DACA_CTRL_RHPIS,
+ sun6i_codec_hp_src_enum_text);
+
+static const struct snd_kcontrol_new sun6i_codec_hp_src[] = {
+ SOC_DAPM_ENUM("Headphone Source Playback Route",
+ sun6i_codec_hp_src_enum),
+};
+
+/* microphone controls */
+static const char * const sun6i_codec_mic2_src_enum_text[] = {
+ "Mic2", "Mic3",
+};
+
+static SOC_ENUM_SINGLE_DECL(sun6i_codec_mic2_src_enum,
+ SUN6I_CODEC_MIC_CTRL,
+ SUN6I_CODEC_MIC_CTRL_MIC2SLT,
+ sun6i_codec_mic2_src_enum_text);
+
+static const struct snd_kcontrol_new sun6i_codec_mic2_src[] = {
+ SOC_DAPM_ENUM("Mic2 Amplifier Source Route",
+ sun6i_codec_mic2_src_enum),
+};
+
+/* line out controls */
+static const char * const sun6i_codec_lineout_src_enum_text[] = {
+ "Stereo", "Mono Differential",
+};
+
+static SOC_ENUM_DOUBLE_DECL(sun6i_codec_lineout_src_enum,
+ SUN6I_CODEC_MIC_CTRL,
+ SUN6I_CODEC_MIC_CTRL_LINEOUTLSRC,
+ SUN6I_CODEC_MIC_CTRL_LINEOUTRSRC,
+ sun6i_codec_lineout_src_enum_text);
+
+static const struct snd_kcontrol_new sun6i_codec_lineout_src[] = {
+ SOC_DAPM_ENUM("Line Out Source Playback Route",
+ sun6i_codec_lineout_src_enum),
+};
+
+/* volume / mute controls */
+static const DECLARE_TLV_DB_SCALE(sun6i_codec_dvol_scale, -7308, 116, 0);
+static const DECLARE_TLV_DB_SCALE(sun6i_codec_hp_vol_scale, -6300, 100, 1);
+static const DECLARE_TLV_DB_SCALE(sun6i_codec_out_mixer_pregain_scale,
+ -450, 150, 0);
+static const DECLARE_TLV_DB_RANGE(sun6i_codec_lineout_vol_scale,
+ 0, 1, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
+ 2, 31, TLV_DB_SCALE_ITEM(-4350, 150, 0),
+);
+static const DECLARE_TLV_DB_RANGE(sun6i_codec_mic_gain_scale,
+ 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
+ 1, 7, TLV_DB_SCALE_ITEM(2400, 300, 0),
+);
+
+static const struct snd_kcontrol_new sun6i_codec_codec_widgets[] = {
+ SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC,
+ SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1,
+ sun6i_codec_dvol_scale),
+ SOC_SINGLE_TLV("Headphone Playback Volume",
+ SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_HPVOL, 0x3f, 0,
+ sun6i_codec_hp_vol_scale),
+ SOC_SINGLE_TLV("Line Out Playback Volume",
+ SUN6I_CODEC_MIC_CTRL,
+ SUN6I_CODEC_MIC_CTRL_LINEOUTVC, 0x1f, 0,
+ sun6i_codec_lineout_vol_scale),
+ SOC_DOUBLE("Headphone Playback Switch",
+ SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_LHPPAMUTE,
+ SUN6I_CODEC_OM_DACA_CTRL_RHPPAMUTE, 1, 0),
+ SOC_DOUBLE("Line Out Playback Switch",
+ SUN6I_CODEC_MIC_CTRL,
+ SUN6I_CODEC_MIC_CTRL_LINEOUTLEN,
+ SUN6I_CODEC_MIC_CTRL_LINEOUTREN, 1, 0),
+ /* Mixer pre-gains */
+ SOC_SINGLE_TLV("Line In Playback Volume",
+ SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_LINEING,
+ 0x7, 0, sun6i_codec_out_mixer_pregain_scale),
+ SOC_SINGLE_TLV("Mic1 Playback Volume",
+ SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_MIC1G,
+ 0x7, 0, sun6i_codec_out_mixer_pregain_scale),
+ SOC_SINGLE_TLV("Mic2 Playback Volume",
+ SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_MIC2G,
+ 0x7, 0, sun6i_codec_out_mixer_pregain_scale),
+
+ /* Microphone Amp boost gains */
+ SOC_SINGLE_TLV("Mic1 Boost Volume", SUN6I_CODEC_MIC_CTRL,
+ SUN6I_CODEC_MIC_CTRL_MIC1BOOST, 0x7, 0,
+ sun6i_codec_mic_gain_scale),
+ SOC_SINGLE_TLV("Mic2 Boost Volume", SUN6I_CODEC_MIC_CTRL,
+ SUN6I_CODEC_MIC_CTRL_MIC2BOOST, 0x7, 0,
+ sun6i_codec_mic_gain_scale),
+ SOC_DOUBLE_TLV("ADC Capture Volume",
+ SUN6I_CODEC_ADC_ACTL, SUN6I_CODEC_ADC_ACTL_ADCLG,
+ SUN6I_CODEC_ADC_ACTL_ADCRG, 0x7, 0,
+ sun6i_codec_out_mixer_pregain_scale),
+};
+
+static const struct snd_soc_dapm_widget sun6i_codec_codec_dapm_widgets[] = {
+ /* Microphone inputs */
+ SND_SOC_DAPM_INPUT("MIC1"),
+ SND_SOC_DAPM_INPUT("MIC2"),
+ SND_SOC_DAPM_INPUT("MIC3"),
+
+ /* Microphone Bias */
+ SND_SOC_DAPM_SUPPLY("HBIAS", SUN6I_CODEC_MIC_CTRL,
+ SUN6I_CODEC_MIC_CTRL_HBIASEN, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("MBIAS", SUN6I_CODEC_MIC_CTRL,
+ SUN6I_CODEC_MIC_CTRL_MBIASEN, 0, NULL, 0),
+
+ /* Mic input path */
+ SND_SOC_DAPM_MUX("Mic2 Amplifier Source Route",
+ SND_SOC_NOPM, 0, 0, sun6i_codec_mic2_src),
+ SND_SOC_DAPM_PGA("Mic1 Amplifier", SUN6I_CODEC_MIC_CTRL,
+ SUN6I_CODEC_MIC_CTRL_MIC1AMPEN, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("Mic2 Amplifier", SUN6I_CODEC_MIC_CTRL,
+ SUN6I_CODEC_MIC_CTRL_MIC2AMPEN, 0, NULL, 0),
+
+ /* Line In */
+ SND_SOC_DAPM_INPUT("LINEIN"),
+
+ /* Digital parts of the ADCs */
+ SND_SOC_DAPM_SUPPLY("ADC Enable", SUN6I_CODEC_ADC_FIFOC,
+ SUN6I_CODEC_ADC_FIFOC_EN_AD, 0,
+ NULL, 0),
+
+ /* Analog parts of the ADCs */
+ SND_SOC_DAPM_ADC("Left ADC", "Codec Capture", SUN6I_CODEC_ADC_ACTL,
+ SUN6I_CODEC_ADC_ACTL_ADCLEN, 0),
+ SND_SOC_DAPM_ADC("Right ADC", "Codec Capture", SUN6I_CODEC_ADC_ACTL,
+ SUN6I_CODEC_ADC_ACTL_ADCREN, 0),
+
+ /* ADC Mixers */
+ SOC_MIXER_ARRAY("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
+ sun6i_codec_adc_mixer_controls),
+ SOC_MIXER_ARRAY("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
+ sun6i_codec_adc_mixer_controls),
+
+ /* Digital parts of the DACs */
+ SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC,
+ SUN4I_CODEC_DAC_DPC_EN_DA, 0,
+ NULL, 0),
+
+ /* Analog parts of the DACs */
+ SND_SOC_DAPM_DAC("Left DAC", "Codec Playback",
+ SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_DACALEN, 0),
+ SND_SOC_DAPM_DAC("Right DAC", "Codec Playback",
+ SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_DACAREN, 0),
+
+ /* Mixers */
+ SOC_MIXER_ARRAY("Left Mixer", SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_LMIXEN, 0,
+ sun6i_codec_mixer_controls),
+ SOC_MIXER_ARRAY("Right Mixer", SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_RMIXEN, 0,
+ sun6i_codec_mixer_controls),
+
+ /* Headphone output path */
+ SND_SOC_DAPM_MUX("Headphone Source Playback Route",
+ SND_SOC_NOPM, 0, 0, sun6i_codec_hp_src),
+ SND_SOC_DAPM_OUT_DRV("Headphone Amp", SUN6I_CODEC_OM_PA_CTRL,
+ SUN6I_CODEC_OM_PA_CTRL_HPPAEN, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("HPCOM Protection", SUN6I_CODEC_OM_PA_CTRL,
+ SUN6I_CODEC_OM_PA_CTRL_COMPTEN, 0, NULL, 0),
+ SND_SOC_DAPM_REG(snd_soc_dapm_supply, "HPCOM", SUN6I_CODEC_OM_PA_CTRL,
+ SUN6I_CODEC_OM_PA_CTRL_HPCOM_CTL, 0x3, 0x3, 0),
+ SND_SOC_DAPM_OUTPUT("HP"),
+
+ /* Line Out path */
+ SND_SOC_DAPM_MUX("Line Out Source Playback Route",
+ SND_SOC_NOPM, 0, 0, sun6i_codec_lineout_src),
+ SND_SOC_DAPM_OUTPUT("LINEOUT"),
+};
+
+static const struct snd_soc_dapm_route sun6i_codec_codec_dapm_routes[] = {
+ /* DAC Routes */
+ { "Left DAC", NULL, "DAC Enable" },
+ { "Right DAC", NULL, "DAC Enable" },
+
+ /* Microphone Routes */
+ { "Mic1 Amplifier", NULL, "MIC1"},
+ { "Mic2 Amplifier Source Route", "Mic2", "MIC2" },
+ { "Mic2 Amplifier Source Route", "Mic3", "MIC3" },
+ { "Mic2 Amplifier", NULL, "Mic2 Amplifier Source Route"},
+
+ /* Left Mixer Routes */
+ { "Left Mixer", "DAC Playback Switch", "Left DAC" },
+ { "Left Mixer", "DAC Reversed Playback Switch", "Right DAC" },
+ { "Left Mixer", "Line In Playback Switch", "LINEIN" },
+ { "Left Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
+ { "Left Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
+
+ /* Right Mixer Routes */
+ { "Right Mixer", "DAC Playback Switch", "Right DAC" },
+ { "Right Mixer", "DAC Reversed Playback Switch", "Left DAC" },
+ { "Right Mixer", "Line In Playback Switch", "LINEIN" },
+ { "Right Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
+ { "Right Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
+
+ /* Left ADC Mixer Routes */
+ { "Left ADC Mixer", "Mixer Capture Switch", "Left Mixer" },
+ { "Left ADC Mixer", "Mixer Reversed Capture Switch", "Right Mixer" },
+ { "Left ADC Mixer", "Line In Capture Switch", "LINEIN" },
+ { "Left ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
+ { "Left ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
+
+ /* Right ADC Mixer Routes */
+ { "Right ADC Mixer", "Mixer Capture Switch", "Right Mixer" },
+ { "Right ADC Mixer", "Mixer Reversed Capture Switch", "Left Mixer" },
+ { "Right ADC Mixer", "Line In Capture Switch", "LINEIN" },
+ { "Right ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
+ { "Right ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
+
+ /* Headphone Routes */
+ { "Headphone Source Playback Route", "DAC", "Left DAC" },
+ { "Headphone Source Playback Route", "DAC", "Right DAC" },
+ { "Headphone Source Playback Route", "Mixer", "Left Mixer" },
+ { "Headphone Source Playback Route", "Mixer", "Right Mixer" },
+ { "Headphone Amp", NULL, "Headphone Source Playback Route" },
+ { "HP", NULL, "Headphone Amp" },
+ { "HPCOM", NULL, "HPCOM Protection" },
+
+ /* Line Out Routes */
+ { "Line Out Source Playback Route", "Stereo", "Left Mixer" },
+ { "Line Out Source Playback Route", "Stereo", "Right Mixer" },
+ { "Line Out Source Playback Route", "Mono Differential", "Left Mixer" },
+ { "Line Out Source Playback Route", "Mono Differential", "Right Mixer" },
+ { "LINEOUT", NULL, "Line Out Source Playback Route" },
+
+ /* ADC Routes */
+ { "Left ADC", NULL, "ADC Enable" },
+ { "Right ADC", NULL, "ADC Enable" },
+ { "Left ADC", NULL, "Left ADC Mixer" },
+ { "Right ADC", NULL, "Right ADC Mixer" },
+};
+
+static const struct snd_soc_component_driver sun6i_codec_codec = {
+ .controls = sun6i_codec_codec_widgets,
+ .num_controls = ARRAY_SIZE(sun6i_codec_codec_widgets),
+ .dapm_widgets = sun6i_codec_codec_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(sun6i_codec_codec_dapm_widgets),
+ .dapm_routes = sun6i_codec_codec_dapm_routes,
+ .num_dapm_routes = ARRAY_SIZE(sun6i_codec_codec_dapm_routes),
+ .idle_bias_on = 1,
+ .use_pmdown_time = 1,
+ .endianness = 1,
+};
+
+/* sun8i A23 codec */
+static const struct snd_kcontrol_new sun8i_a23_codec_codec_controls[] = {
+ SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC,
+ SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1,
+ sun6i_codec_dvol_scale),
+};
+
+static const struct snd_soc_dapm_widget sun8i_a23_codec_codec_widgets[] = {
+ /* Digital parts of the ADCs */
+ SND_SOC_DAPM_SUPPLY("ADC Enable", SUN6I_CODEC_ADC_FIFOC,
+ SUN6I_CODEC_ADC_FIFOC_EN_AD, 0, NULL, 0),
+ /* Digital parts of the DACs */
+ SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC,
+ SUN4I_CODEC_DAC_DPC_EN_DA, 0, NULL, 0),
+
+};
+
+static const struct snd_soc_component_driver sun8i_a23_codec_codec = {
+ .controls = sun8i_a23_codec_codec_controls,
+ .num_controls = ARRAY_SIZE(sun8i_a23_codec_codec_controls),
+ .dapm_widgets = sun8i_a23_codec_codec_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(sun8i_a23_codec_codec_widgets),
+ .idle_bias_on = 1,
+ .use_pmdown_time = 1,
+ .endianness = 1,
+};
+
+static const struct snd_soc_component_driver sun4i_codec_component = {
+ .name = "sun4i-codec",
+ .legacy_dai_naming = 1,
+#ifdef CONFIG_DEBUG_FS
+ .debugfs_prefix = "cpu",
+#endif
+};
+
+#define SUN4I_CODEC_RATES SNDRV_PCM_RATE_CONTINUOUS
+#define SUN4I_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE)
+
+static int sun4i_codec_dai_probe(struct snd_soc_dai *dai)
+{
+ struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
+ struct sun4i_codec *scodec = snd_soc_card_get_drvdata(card);
+
+ snd_soc_dai_init_dma_data(dai, &scodec->playback_dma_data,
+ &scodec->capture_dma_data);
+
+ return 0;
+}
+
+static const struct snd_soc_dai_ops dummy_dai_ops = {
+ .probe = sun4i_codec_dai_probe,
+};
+
+static struct snd_soc_dai_driver dummy_cpu_dai = {
+ .name = "sun4i-codec-cpu-dai",
+ .playback = {
+ .stream_name = "Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SUN4I_CODEC_RATES,
+ .formats = SUN4I_CODEC_FORMATS,
+ .sig_bits = 24,
+ },
+ .capture = {
+ .stream_name = "Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SUN4I_CODEC_RATES,
+ .formats = SUN4I_CODEC_FORMATS,
+ .sig_bits = 24,
+ },
+ .ops = &dummy_dai_ops,
+};
+
+static struct snd_soc_dai_link *sun4i_codec_create_link(struct device *dev,
+ int *num_links)
+{
+ struct snd_soc_dai_link *link = devm_kzalloc(dev, sizeof(*link),
+ GFP_KERNEL);
+ struct snd_soc_dai_link_component *dlc = devm_kzalloc(dev,
+ 3 * sizeof(*dlc), GFP_KERNEL);
+ if (!link || !dlc)
+ return NULL;
+
+ link->cpus = &dlc[0];
+ link->codecs = &dlc[1];
+ link->platforms = &dlc[2];
+
+ link->num_cpus = 1;
+ link->num_codecs = 1;
+ link->num_platforms = 1;
+
+ link->name = "cdc";
+ link->stream_name = "CDC PCM";
+ link->codecs->dai_name = "Codec";
+ link->cpus->dai_name = dev_name(dev);
+ link->codecs->name = dev_name(dev);
+ link->platforms->name = dev_name(dev);
+ link->dai_fmt = SND_SOC_DAIFMT_I2S;
+
+ *num_links = 1;
+
+ return link;
+};
+
+static int sun4i_codec_spk_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *k, int event)
+{
+ struct sun4i_codec *scodec = snd_soc_card_get_drvdata(w->dapm->card);
+
+ gpiod_set_value_cansleep(scodec->gpio_pa,
+ !!SND_SOC_DAPM_EVENT_ON(event));
+
+ if (SND_SOC_DAPM_EVENT_ON(event)) {
+ /*
+ * Need a delay to wait for DAC to push the data. 700ms seems
+ * to be the best compromise not to feel this delay while
+ * playing a sound.
+ */
+ msleep(700);
+ }
+
+ return 0;
+}
+
+static const struct snd_soc_dapm_widget sun4i_codec_card_dapm_widgets[] = {
+ SND_SOC_DAPM_SPK("Speaker", sun4i_codec_spk_event),
+};
+
+static const struct snd_soc_dapm_route sun4i_codec_card_dapm_routes[] = {
+ { "Speaker", NULL, "HP Right" },
+ { "Speaker", NULL, "HP Left" },
+};
+
+static struct snd_soc_card *sun4i_codec_create_card(struct device *dev)
+{
+ struct snd_soc_card *card;
+
+ card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
+ if (!card)
+ return ERR_PTR(-ENOMEM);
+
+ card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
+ if (!card->dai_link)
+ return ERR_PTR(-ENOMEM);
+
+ card->dev = dev;
+ card->owner = THIS_MODULE;
+ card->name = "sun4i-codec";
+ card->dapm_widgets = sun4i_codec_card_dapm_widgets;
+ card->num_dapm_widgets = ARRAY_SIZE(sun4i_codec_card_dapm_widgets);
+ card->dapm_routes = sun4i_codec_card_dapm_routes;
+ card->num_dapm_routes = ARRAY_SIZE(sun4i_codec_card_dapm_routes);
+
+ return card;
+};
+
+static const struct snd_soc_dapm_widget sun6i_codec_card_dapm_widgets[] = {
+ SND_SOC_DAPM_HP("Headphone", NULL),
+ SND_SOC_DAPM_LINE("Line In", NULL),
+ SND_SOC_DAPM_LINE("Line Out", NULL),
+ SND_SOC_DAPM_MIC("Headset Mic", NULL),
+ SND_SOC_DAPM_MIC("Mic", NULL),
+ SND_SOC_DAPM_SPK("Speaker", sun4i_codec_spk_event),
+};
+
+static struct snd_soc_card *sun6i_codec_create_card(struct device *dev)
+{
+ struct snd_soc_card *card;
+ int ret;
+
+ card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
+ if (!card)
+ return ERR_PTR(-ENOMEM);
+
+ card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
+ if (!card->dai_link)
+ return ERR_PTR(-ENOMEM);
+
+ card->dev = dev;
+ card->owner = THIS_MODULE;
+ card->name = "A31 Audio Codec";
+ card->dapm_widgets = sun6i_codec_card_dapm_widgets;
+ card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
+ card->fully_routed = true;
+
+ ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
+ if (ret)
+ dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
+
+ return card;
+};
+
+/* Connect digital side enables to analog side widgets */
+static const struct snd_soc_dapm_route sun8i_codec_card_routes[] = {
+ /* ADC Routes */
+ { "Left ADC", NULL, "ADC Enable" },
+ { "Right ADC", NULL, "ADC Enable" },
+ { "Codec Capture", NULL, "Left ADC" },
+ { "Codec Capture", NULL, "Right ADC" },
+
+ /* DAC Routes */
+ { "Left DAC", NULL, "DAC Enable" },
+ { "Right DAC", NULL, "DAC Enable" },
+ { "Left DAC", NULL, "Codec Playback" },
+ { "Right DAC", NULL, "Codec Playback" },
+};
+
+static struct snd_soc_aux_dev aux_dev = {
+ .dlc = COMP_EMPTY(),
+};
+
+static struct snd_soc_card *sun8i_a23_codec_create_card(struct device *dev)
+{
+ struct snd_soc_card *card;
+ int ret;
+
+ card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
+ if (!card)
+ return ERR_PTR(-ENOMEM);
+
+ aux_dev.dlc.of_node = of_parse_phandle(dev->of_node,
+ "allwinner,codec-analog-controls",
+ 0);
+ if (!aux_dev.dlc.of_node) {
+ dev_err(dev, "Can't find analog controls for codec.\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
+ if (!card->dai_link)
+ return ERR_PTR(-ENOMEM);
+
+ card->dev = dev;
+ card->owner = THIS_MODULE;
+ card->name = "A23 Audio Codec";
+ card->dapm_widgets = sun6i_codec_card_dapm_widgets;
+ card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
+ card->dapm_routes = sun8i_codec_card_routes;
+ card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes);
+ card->aux_dev = &aux_dev;
+ card->num_aux_devs = 1;
+ card->fully_routed = true;
+
+ ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
+ if (ret)
+ dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
+
+ return card;
+};
+
+static struct snd_soc_card *sun8i_h3_codec_create_card(struct device *dev)
+{
+ struct snd_soc_card *card;
+ int ret;
+
+ card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
+ if (!card)
+ return ERR_PTR(-ENOMEM);
+
+ aux_dev.dlc.of_node = of_parse_phandle(dev->of_node,
+ "allwinner,codec-analog-controls",
+ 0);
+ if (!aux_dev.dlc.of_node) {
+ dev_err(dev, "Can't find analog controls for codec.\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
+ if (!card->dai_link)
+ return ERR_PTR(-ENOMEM);
+
+ card->dev = dev;
+ card->owner = THIS_MODULE;
+ card->name = "H3 Audio Codec";
+ card->dapm_widgets = sun6i_codec_card_dapm_widgets;
+ card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
+ card->dapm_routes = sun8i_codec_card_routes;
+ card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes);
+ card->aux_dev = &aux_dev;
+ card->num_aux_devs = 1;
+ card->fully_routed = true;
+
+ ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
+ if (ret)
+ dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
+
+ return card;
+};
+
+static struct snd_soc_card *sun8i_v3s_codec_create_card(struct device *dev)
+{
+ struct snd_soc_card *card;
+ int ret;
+
+ card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
+ if (!card)
+ return ERR_PTR(-ENOMEM);
+
+ aux_dev.dlc.of_node = of_parse_phandle(dev->of_node,
+ "allwinner,codec-analog-controls",
+ 0);
+ if (!aux_dev.dlc.of_node) {
+ dev_err(dev, "Can't find analog controls for codec.\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
+ if (!card->dai_link)
+ return ERR_PTR(-ENOMEM);
+
+ card->dev = dev;
+ card->owner = THIS_MODULE;
+ card->name = "V3s Audio Codec";
+ card->dapm_widgets = sun6i_codec_card_dapm_widgets;
+ card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
+ card->dapm_routes = sun8i_codec_card_routes;
+ card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes);
+ card->aux_dev = &aux_dev;
+ card->num_aux_devs = 1;
+ card->fully_routed = true;
+
+ ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
+ if (ret)
+ dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
+
+ return card;
+};
+
+static const struct regmap_config sun4i_codec_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = SUN4I_CODEC_ADC_RXCNT,
+};
+
+static const struct regmap_config sun6i_codec_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = SUN6I_CODEC_HMIC_DATA,
+};
+
+static const struct regmap_config sun7i_codec_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = SUN7I_CODEC_AC_MIC_PHONE_CAL,
+};
+
+static const struct regmap_config sun8i_a23_codec_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = SUN8I_A23_CODEC_ADC_RXCNT,
+};
+
+static const struct regmap_config sun8i_h3_codec_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = SUN8I_H3_CODEC_ADC_DBG,
+};
+
+static const struct regmap_config sun8i_v3s_codec_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = SUN8I_H3_CODEC_ADC_DBG,
+};
+
+struct sun4i_codec_quirks {
+ const struct regmap_config *regmap_config;
+ const struct snd_soc_component_driver *codec;
+ struct snd_soc_card * (*create_card)(struct device *dev);
+ struct reg_field reg_adc_fifoc; /* used for regmap_field */
+ unsigned int reg_dac_txdata; /* TX FIFO offset for DMA config */
+ unsigned int reg_adc_rxdata; /* RX FIFO offset for DMA config */
+ bool has_reset;
+};
+
+static const struct sun4i_codec_quirks sun4i_codec_quirks = {
+ .regmap_config = &sun4i_codec_regmap_config,
+ .codec = &sun4i_codec_codec,
+ .create_card = sun4i_codec_create_card,
+ .reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31),
+ .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
+ .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA,
+};
+
+static const struct sun4i_codec_quirks sun6i_a31_codec_quirks = {
+ .regmap_config = &sun6i_codec_regmap_config,
+ .codec = &sun6i_codec_codec,
+ .create_card = sun6i_codec_create_card,
+ .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
+ .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
+ .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
+ .has_reset = true,
+};
+
+static const struct sun4i_codec_quirks sun7i_codec_quirks = {
+ .regmap_config = &sun7i_codec_regmap_config,
+ .codec = &sun7i_codec_codec,
+ .create_card = sun4i_codec_create_card,
+ .reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31),
+ .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
+ .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA,
+};
+
+static const struct sun4i_codec_quirks sun8i_a23_codec_quirks = {
+ .regmap_config = &sun8i_a23_codec_regmap_config,
+ .codec = &sun8i_a23_codec_codec,
+ .create_card = sun8i_a23_codec_create_card,
+ .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
+ .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
+ .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
+ .has_reset = true,
+};
+
+static const struct sun4i_codec_quirks sun8i_h3_codec_quirks = {
+ .regmap_config = &sun8i_h3_codec_regmap_config,
+ /*
+ * TODO Share the codec structure with A23 for now.
+ * This should be split out when adding digital audio
+ * processing support for the H3.
+ */
+ .codec = &sun8i_a23_codec_codec,
+ .create_card = sun8i_h3_codec_create_card,
+ .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
+ .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA,
+ .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
+ .has_reset = true,
+};
+
+static const struct sun4i_codec_quirks sun8i_v3s_codec_quirks = {
+ .regmap_config = &sun8i_v3s_codec_regmap_config,
+ /*
+ * TODO The codec structure should be split out, like
+ * H3, when adding digital audio processing support.
+ */
+ .codec = &sun8i_a23_codec_codec,
+ .create_card = sun8i_v3s_codec_create_card,
+ .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
+ .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA,
+ .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
+ .has_reset = true,
+};
+
+static const struct of_device_id sun4i_codec_of_match[] = {
+ {
+ .compatible = "allwinner,sun4i-a10-codec",
+ .data = &sun4i_codec_quirks,
+ },
+ {
+ .compatible = "allwinner,sun6i-a31-codec",
+ .data = &sun6i_a31_codec_quirks,
+ },
+ {
+ .compatible = "allwinner,sun7i-a20-codec",
+ .data = &sun7i_codec_quirks,
+ },
+ {
+ .compatible = "allwinner,sun8i-a23-codec",
+ .data = &sun8i_a23_codec_quirks,
+ },
+ {
+ .compatible = "allwinner,sun8i-h3-codec",
+ .data = &sun8i_h3_codec_quirks,
+ },
+ {
+ .compatible = "allwinner,sun8i-v3s-codec",
+ .data = &sun8i_v3s_codec_quirks,
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, sun4i_codec_of_match);
+
+static int sun4i_codec_probe(struct platform_device *pdev)
+{
+ struct snd_soc_card *card;
+ struct sun4i_codec *scodec;
+ const struct sun4i_codec_quirks *quirks;
+ struct resource *res;
+ void __iomem *base;
+ int ret;
+
+ scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
+ if (!scodec)
+ return -ENOMEM;
+
+ scodec->dev = &pdev->dev;
+
+ base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ quirks = of_device_get_match_data(&pdev->dev);
+ if (quirks == NULL) {
+ dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
+ return -ENODEV;
+ }
+
+ scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ quirks->regmap_config);
+ if (IS_ERR(scodec->regmap)) {
+ dev_err(&pdev->dev, "Failed to create our regmap\n");
+ return PTR_ERR(scodec->regmap);
+ }
+
+ /* Get the clocks from the DT */
+ scodec->clk_apb = devm_clk_get(&pdev->dev, "apb");
+ if (IS_ERR(scodec->clk_apb)) {
+ dev_err(&pdev->dev, "Failed to get the APB clock\n");
+ return PTR_ERR(scodec->clk_apb);
+ }
+
+ scodec->clk_module = devm_clk_get(&pdev->dev, "codec");
+ if (IS_ERR(scodec->clk_module)) {
+ dev_err(&pdev->dev, "Failed to get the module clock\n");
+ return PTR_ERR(scodec->clk_module);
+ }
+
+ if (quirks->has_reset) {
+ scodec->rst = devm_reset_control_get_exclusive(&pdev->dev,
+ NULL);
+ if (IS_ERR(scodec->rst)) {
+ dev_err(&pdev->dev, "Failed to get reset control\n");
+ return PTR_ERR(scodec->rst);
+ }
+ }
+
+ scodec->gpio_pa = devm_gpiod_get_optional(&pdev->dev, "allwinner,pa",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(scodec->gpio_pa)) {
+ ret = PTR_ERR(scodec->gpio_pa);
+ dev_err_probe(&pdev->dev, ret, "Failed to get pa gpio\n");
+ return ret;
+ }
+
+ /* reg_field setup */
+ scodec->reg_adc_fifoc = devm_regmap_field_alloc(&pdev->dev,
+ scodec->regmap,
+ quirks->reg_adc_fifoc);
+ if (IS_ERR(scodec->reg_adc_fifoc)) {
+ ret = PTR_ERR(scodec->reg_adc_fifoc);
+ dev_err(&pdev->dev, "Failed to create regmap fields: %d\n",
+ ret);
+ return ret;
+ }
+
+ /* Enable the bus clock */
+ if (clk_prepare_enable(scodec->clk_apb)) {
+ dev_err(&pdev->dev, "Failed to enable the APB clock\n");
+ return -EINVAL;
+ }
+
+ /* Deassert the reset control */
+ if (scodec->rst) {
+ ret = reset_control_deassert(scodec->rst);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "Failed to deassert the reset control\n");
+ goto err_clk_disable;
+ }
+ }
+
+ /* DMA configuration for TX FIFO */
+ scodec->playback_dma_data.addr = res->start + quirks->reg_dac_txdata;
+ scodec->playback_dma_data.maxburst = 8;
+ scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+
+ /* DMA configuration for RX FIFO */
+ scodec->capture_dma_data.addr = res->start + quirks->reg_adc_rxdata;
+ scodec->capture_dma_data.maxburst = 8;
+ scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+
+ ret = devm_snd_soc_register_component(&pdev->dev, quirks->codec,
+ &sun4i_codec_dai, 1);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to register our codec\n");
+ goto err_assert_reset;
+ }
+
+ ret = devm_snd_soc_register_component(&pdev->dev,
+ &sun4i_codec_component,
+ &dummy_cpu_dai, 1);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to register our DAI\n");
+ goto err_assert_reset;
+ }
+
+ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to register against DMAEngine\n");
+ goto err_assert_reset;
+ }
+
+ card = quirks->create_card(&pdev->dev);
+ if (IS_ERR(card)) {
+ ret = PTR_ERR(card);
+ dev_err(&pdev->dev, "Failed to create our card\n");
+ goto err_assert_reset;
+ }
+
+ snd_soc_card_set_drvdata(card, scodec);
+
+ ret = snd_soc_register_card(card);
+ if (ret) {
+ dev_err_probe(&pdev->dev, ret, "Failed to register our card\n");
+ goto err_assert_reset;
+ }
+
+ return 0;
+
+err_assert_reset:
+ if (scodec->rst)
+ reset_control_assert(scodec->rst);
+err_clk_disable:
+ clk_disable_unprepare(scodec->clk_apb);
+ return ret;
+}
+
+static void sun4i_codec_remove(struct platform_device *pdev)
+{
+ struct snd_soc_card *card = platform_get_drvdata(pdev);
+ struct sun4i_codec *scodec = snd_soc_card_get_drvdata(card);
+
+ snd_soc_unregister_card(card);
+ if (scodec->rst)
+ reset_control_assert(scodec->rst);
+ clk_disable_unprepare(scodec->clk_apb);
+}
+
+static struct platform_driver sun4i_codec_driver = {
+ .driver = {
+ .name = "sun4i-codec",
+ .of_match_table = sun4i_codec_of_match,
+ },
+ .probe = sun4i_codec_probe,
+ .remove_new = sun4i_codec_remove,
+};
+module_platform_driver(sun4i_codec_driver);
+
+MODULE_DESCRIPTION("Allwinner A10 codec driver");
+MODULE_AUTHOR("Emilio López <emilio@elopez.com.ar>");
+MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>");
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
+MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
new file mode 100644
index 000000000..5124b6c9c
--- /dev/null
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -0,0 +1,1673 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2015 Andrea Venturi
+ * Andrea Venturi <be17068@iperbole.bo.it>
+ *
+ * Copyright (C) 2016 Maxime Ripard
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/dmaengine.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#include <sound/dmaengine_pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dai.h>
+
+#define SUN4I_I2S_CTRL_REG 0x00
+#define SUN4I_I2S_CTRL_SDO_EN_MASK GENMASK(11, 8)
+#define SUN4I_I2S_CTRL_SDO_EN(sdo) BIT(8 + (sdo))
+#define SUN4I_I2S_CTRL_MODE_MASK BIT(5)
+#define SUN4I_I2S_CTRL_MODE_SLAVE (1 << 5)
+#define SUN4I_I2S_CTRL_MODE_MASTER (0 << 5)
+#define SUN4I_I2S_CTRL_TX_EN BIT(2)
+#define SUN4I_I2S_CTRL_RX_EN BIT(1)
+#define SUN4I_I2S_CTRL_GL_EN BIT(0)
+
+#define SUN4I_I2S_FMT0_REG 0x04
+#define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(7)
+#define SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 7)
+#define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 7)
+#define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK BIT(6)
+#define SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 6)
+#define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 6)
+#define SUN4I_I2S_FMT0_SR_MASK GENMASK(5, 4)
+#define SUN4I_I2S_FMT0_SR(sr) ((sr) << 4)
+#define SUN4I_I2S_FMT0_WSS_MASK GENMASK(3, 2)
+#define SUN4I_I2S_FMT0_WSS(wss) ((wss) << 2)
+#define SUN4I_I2S_FMT0_FMT_MASK GENMASK(1, 0)
+#define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0)
+#define SUN4I_I2S_FMT0_FMT_LEFT_J (1 << 0)
+#define SUN4I_I2S_FMT0_FMT_I2S (0 << 0)
+
+#define SUN4I_I2S_FMT1_REG 0x08
+#define SUN4I_I2S_FMT1_REG_SEXT_MASK BIT(8)
+#define SUN4I_I2S_FMT1_REG_SEXT(sext) ((sext) << 8)
+
+#define SUN4I_I2S_FIFO_TX_REG 0x0c
+#define SUN4I_I2S_FIFO_RX_REG 0x10
+
+#define SUN4I_I2S_FIFO_CTRL_REG 0x14
+#define SUN4I_I2S_FIFO_CTRL_FLUSH_TX BIT(25)
+#define SUN4I_I2S_FIFO_CTRL_FLUSH_RX BIT(24)
+#define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK BIT(2)
+#define SUN4I_I2S_FIFO_CTRL_TX_MODE(mode) ((mode) << 2)
+#define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK GENMASK(1, 0)
+#define SUN4I_I2S_FIFO_CTRL_RX_MODE(mode) (mode)
+
+#define SUN4I_I2S_FIFO_STA_REG 0x18
+
+#define SUN4I_I2S_DMA_INT_CTRL_REG 0x1c
+#define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN BIT(7)
+#define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN BIT(3)
+
+#define SUN4I_I2S_INT_STA_REG 0x20
+
+#define SUN4I_I2S_CLK_DIV_REG 0x24
+#define SUN4I_I2S_CLK_DIV_MCLK_EN BIT(7)
+#define SUN4I_I2S_CLK_DIV_BCLK_MASK GENMASK(6, 4)
+#define SUN4I_I2S_CLK_DIV_BCLK(bclk) ((bclk) << 4)
+#define SUN4I_I2S_CLK_DIV_MCLK_MASK GENMASK(3, 0)
+#define SUN4I_I2S_CLK_DIV_MCLK(mclk) ((mclk) << 0)
+
+#define SUN4I_I2S_TX_CNT_REG 0x28
+#define SUN4I_I2S_RX_CNT_REG 0x2c
+
+#define SUN4I_I2S_TX_CHAN_SEL_REG 0x30
+#define SUN4I_I2S_CHAN_SEL_MASK GENMASK(2, 0)
+#define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0)
+
+#define SUN4I_I2S_TX_CHAN_MAP_REG 0x34
+#define SUN4I_I2S_TX_CHAN_MAP(chan, sample) ((sample) << (chan << 2))
+
+#define SUN4I_I2S_RX_CHAN_SEL_REG 0x38
+#define SUN4I_I2S_RX_CHAN_MAP_REG 0x3c
+
+/* Defines required for sun8i-h3 support */
+#define SUN8I_I2S_CTRL_BCLK_OUT BIT(18)
+#define SUN8I_I2S_CTRL_LRCK_OUT BIT(17)
+
+#define SUN8I_I2S_CTRL_MODE_MASK GENMASK(5, 4)
+#define SUN8I_I2S_CTRL_MODE_RIGHT (2 << 4)
+#define SUN8I_I2S_CTRL_MODE_LEFT (1 << 4)
+#define SUN8I_I2S_CTRL_MODE_PCM (0 << 4)
+
+#define SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(19)
+#define SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 19)
+#define SUN8I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 19)
+#define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8)
+#define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)
+#define SUN8I_I2S_FMT0_BCLK_POLARITY_MASK BIT(7)
+#define SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 7)
+#define SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 7)
+
+#define SUN8I_I2S_FMT1_REG_SEXT_MASK GENMASK(5, 4)
+#define SUN8I_I2S_FMT1_REG_SEXT(sext) ((sext) << 4)
+
+#define SUN8I_I2S_INT_STA_REG 0x0c
+#define SUN8I_I2S_FIFO_TX_REG 0x20
+
+#define SUN8I_I2S_CHAN_CFG_REG 0x30
+#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK GENMASK(7, 4)
+#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4)
+#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK GENMASK(3, 0)
+#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1)
+
+#define SUN8I_I2S_TX_CHAN_MAP_REG 0x44
+#define SUN8I_I2S_TX_CHAN_SEL_REG 0x34
+#define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13, 12)
+#define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 12)
+#define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4)
+#define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4)
+
+#define SUN8I_I2S_RX_CHAN_SEL_REG 0x54
+#define SUN8I_I2S_RX_CHAN_MAP_REG 0x58
+
+/* Defines required for sun50i-h6 support */
+#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK GENMASK(21, 20)
+#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset) ((offset) << 20)
+#define SUN50I_H6_I2S_TX_CHAN_SEL_MASK GENMASK(19, 16)
+#define SUN50I_H6_I2S_TX_CHAN_SEL(chan) ((chan - 1) << 16)
+#define SUN50I_H6_I2S_TX_CHAN_EN_MASK GENMASK(15, 0)
+#define SUN50I_H6_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1))
+
+#define SUN50I_H6_I2S_TX_CHAN_SEL_REG(pin) (0x34 + 4 * (pin))
+#define SUN50I_H6_I2S_TX_CHAN_MAP0_REG(pin) (0x44 + 8 * (pin))
+#define SUN50I_H6_I2S_TX_CHAN_MAP1_REG(pin) (0x48 + 8 * (pin))
+
+#define SUN50I_H6_I2S_RX_CHAN_SEL_REG 0x64
+#define SUN50I_H6_I2S_RX_CHAN_MAP0_REG 0x68
+#define SUN50I_H6_I2S_RX_CHAN_MAP1_REG 0x6C
+
+#define SUN50I_R329_I2S_RX_CHAN_MAP0_REG 0x68
+#define SUN50I_R329_I2S_RX_CHAN_MAP1_REG 0x6c
+#define SUN50I_R329_I2S_RX_CHAN_MAP2_REG 0x70
+#define SUN50I_R329_I2S_RX_CHAN_MAP3_REG 0x74
+
+struct sun4i_i2s;
+
+/**
+ * struct sun4i_i2s_quirks - Differences between SoC variants.
+ * @has_reset: SoC needs reset deasserted.
+ * @reg_offset_txdata: offset of the tx fifo.
+ * @sun4i_i2s_regmap: regmap config to use.
+ * @field_clkdiv_mclk_en: regmap field to enable mclk output.
+ * @field_fmt_wss: regmap field to set word select size.
+ * @field_fmt_sr: regmap field to set sample resolution.
+ * @num_din_pins: input pins
+ * @num_dout_pins: output pins (currently set but unused)
+ * @bclk_dividers: bit clock dividers array
+ * @num_bclk_dividers: number of bit clock dividers
+ * @mclk_dividers: mclk dividers array
+ * @num_mclk_dividers: number of mclk dividers
+ * @get_bclk_parent_rate: callback to get bclk parent rate
+ * @get_sr: callback to get sample resolution
+ * @get_wss: callback to get word select size
+ * @set_chan_cfg: callback to set channel configuration
+ * @set_fmt: callback to set format
+ */
+struct sun4i_i2s_quirks {
+ bool has_reset;
+ unsigned int reg_offset_txdata; /* TX FIFO */
+ const struct regmap_config *sun4i_i2s_regmap;
+
+ /* Register fields for i2s */
+ struct reg_field field_clkdiv_mclk_en;
+ struct reg_field field_fmt_wss;
+ struct reg_field field_fmt_sr;
+
+ unsigned int num_din_pins;
+ unsigned int num_dout_pins;
+
+ const struct sun4i_i2s_clk_div *bclk_dividers;
+ unsigned int num_bclk_dividers;
+ const struct sun4i_i2s_clk_div *mclk_dividers;
+ unsigned int num_mclk_dividers;
+
+ unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *i2s);
+ int (*get_sr)(unsigned int width);
+ int (*get_wss)(unsigned int width);
+
+ /*
+ * In the set_chan_cfg() function pointer:
+ * @slots: channels per frame + padding slots, regardless of format
+ * @slot_width: bits per sample + padding bits, regardless of format
+ */
+ int (*set_chan_cfg)(const struct sun4i_i2s *i2s,
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width);
+ int (*set_fmt)(const struct sun4i_i2s *i2s, unsigned int fmt);
+};
+
+struct sun4i_i2s {
+ struct clk *bus_clk;
+ struct clk *mod_clk;
+ struct regmap *regmap;
+ struct reset_control *rst;
+
+ unsigned int format;
+ unsigned int mclk_freq;
+ unsigned int slots;
+ unsigned int slot_width;
+
+ struct snd_dmaengine_dai_dma_data capture_dma_data;
+ struct snd_dmaengine_dai_dma_data playback_dma_data;
+
+ /* Register fields for i2s */
+ struct regmap_field *field_clkdiv_mclk_en;
+ struct regmap_field *field_fmt_wss;
+ struct regmap_field *field_fmt_sr;
+
+ const struct sun4i_i2s_quirks *variant;
+};
+
+struct sun4i_i2s_clk_div {
+ u8 div;
+ u8 val;
+};
+
+static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] = {
+ { .div = 2, .val = 0 },
+ { .div = 4, .val = 1 },
+ { .div = 6, .val = 2 },
+ { .div = 8, .val = 3 },
+ { .div = 12, .val = 4 },
+ { .div = 16, .val = 5 },
+ /* TODO - extend divide ratio supported by newer SoCs */
+};
+
+static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = {
+ { .div = 1, .val = 0 },
+ { .div = 2, .val = 1 },
+ { .div = 4, .val = 2 },
+ { .div = 6, .val = 3 },
+ { .div = 8, .val = 4 },
+ { .div = 12, .val = 5 },
+ { .div = 16, .val = 6 },
+ { .div = 24, .val = 7 },
+ /* TODO - extend divide ratio supported by newer SoCs */
+};
+
+static const struct sun4i_i2s_clk_div sun8i_i2s_clk_div[] = {
+ { .div = 1, .val = 1 },
+ { .div = 2, .val = 2 },
+ { .div = 4, .val = 3 },
+ { .div = 6, .val = 4 },
+ { .div = 8, .val = 5 },
+ { .div = 12, .val = 6 },
+ { .div = 16, .val = 7 },
+ { .div = 24, .val = 8 },
+ { .div = 32, .val = 9 },
+ { .div = 48, .val = 10 },
+ { .div = 64, .val = 11 },
+ { .div = 96, .val = 12 },
+ { .div = 128, .val = 13 },
+ { .div = 176, .val = 14 },
+ { .div = 192, .val = 15 },
+};
+
+static unsigned long sun4i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s)
+{
+ return i2s->mclk_freq;
+}
+
+static unsigned long sun8i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s)
+{
+ return clk_get_rate(i2s->mod_clk);
+}
+
+static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s,
+ unsigned long parent_rate,
+ unsigned int sampling_rate,
+ unsigned int channels,
+ unsigned int word_size)
+{
+ const struct sun4i_i2s_clk_div *dividers = i2s->variant->bclk_dividers;
+ int div = parent_rate / sampling_rate / word_size / channels;
+ int i;
+
+ for (i = 0; i < i2s->variant->num_bclk_dividers; i++) {
+ const struct sun4i_i2s_clk_div *bdiv = &dividers[i];
+
+ if (bdiv->div == div)
+ return bdiv->val;
+ }
+
+ return -EINVAL;
+}
+
+static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s,
+ unsigned long parent_rate,
+ unsigned long mclk_rate)
+{
+ const struct sun4i_i2s_clk_div *dividers = i2s->variant->mclk_dividers;
+ int div = parent_rate / mclk_rate;
+ int i;
+
+ for (i = 0; i < i2s->variant->num_mclk_dividers; i++) {
+ const struct sun4i_i2s_clk_div *mdiv = &dividers[i];
+
+ if (mdiv->div == div)
+ return mdiv->val;
+ }
+
+ return -EINVAL;
+}
+
+static int sun4i_i2s_oversample_rates[] = { 128, 192, 256, 384, 512, 768 };
+static bool sun4i_i2s_oversample_is_valid(unsigned int oversample)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++)
+ if (sun4i_i2s_oversample_rates[i] == oversample)
+ return true;
+
+ return false;
+}
+
+static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
+ unsigned int rate,
+ unsigned int slots,
+ unsigned int slot_width)
+{
+ struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
+ unsigned int oversample_rate, clk_rate, bclk_parent_rate;
+ int bclk_div, mclk_div;
+ int ret;
+
+ switch (rate) {
+ case 176400:
+ case 88200:
+ case 44100:
+ case 22050:
+ case 11025:
+ clk_rate = 22579200;
+ break;
+
+ case 192000:
+ case 128000:
+ case 96000:
+ case 64000:
+ case 48000:
+ case 32000:
+ case 24000:
+ case 16000:
+ case 12000:
+ case 8000:
+ clk_rate = 24576000;
+ break;
+
+ default:
+ dev_err(dai->dev, "Unsupported sample rate: %u\n", rate);
+ return -EINVAL;
+ }
+
+ ret = clk_set_rate(i2s->mod_clk, clk_rate);
+ if (ret)
+ return ret;
+
+ oversample_rate = i2s->mclk_freq / rate;
+ if (!sun4i_i2s_oversample_is_valid(oversample_rate)) {
+ dev_err(dai->dev, "Unsupported oversample rate: %d\n",
+ oversample_rate);
+ return -EINVAL;
+ }
+
+ bclk_parent_rate = i2s->variant->get_bclk_parent_rate(i2s);
+ bclk_div = sun4i_i2s_get_bclk_div(i2s, bclk_parent_rate,
+ rate, slots, slot_width);
+ if (bclk_div < 0) {
+ dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div);
+ return -EINVAL;
+ }
+
+ mclk_div = sun4i_i2s_get_mclk_div(i2s, clk_rate, i2s->mclk_freq);
+ if (mclk_div < 0) {
+ dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div);
+ return -EINVAL;
+ }
+
+ regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG,
+ SUN4I_I2S_CLK_DIV_BCLK(bclk_div) |
+ SUN4I_I2S_CLK_DIV_MCLK(mclk_div));
+
+ regmap_field_write(i2s->field_clkdiv_mclk_en, 1);
+
+ return 0;
+}
+
+static int sun4i_i2s_get_sr(unsigned int width)
+{
+ switch (width) {
+ case 16:
+ return 0;
+ case 20:
+ return 1;
+ case 24:
+ return 2;
+ }
+
+ return -EINVAL;
+}
+
+static int sun4i_i2s_get_wss(unsigned int width)
+{
+ switch (width) {
+ case 16:
+ return 0;
+ case 20:
+ return 1;
+ case 24:
+ return 2;
+ case 32:
+ return 3;
+ }
+
+ return -EINVAL;
+}
+
+static int sun8i_i2s_get_sr_wss(unsigned int width)
+{
+ switch (width) {
+ case 8:
+ return 1;
+ case 12:
+ return 2;
+ case 16:
+ return 3;
+ case 20:
+ return 4;
+ case 24:
+ return 5;
+ case 28:
+ return 6;
+ case 32:
+ return 7;
+ }
+
+ return -EINVAL;
+}
+
+static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width)
+{
+ /* Map the channels for playback and capture */
+ regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210);
+ regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210);
+
+ /* Configure the channels */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_TX_CHAN_SEL_REG,
+ SUN4I_I2S_CHAN_SEL_MASK,
+ SUN4I_I2S_CHAN_SEL(channels));
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_RX_CHAN_SEL_REG,
+ SUN4I_I2S_CHAN_SEL_MASK,
+ SUN4I_I2S_CHAN_SEL(channels));
+
+ return 0;
+}
+
+static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width)
+{
+ unsigned int lrck_period;
+
+ /* Map the channels for playback and capture */
+ regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210);
+ regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210);
+
+ /* Configure the channels */
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
+ SUN4I_I2S_CHAN_SEL_MASK,
+ SUN4I_I2S_CHAN_SEL(channels));
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
+ SUN4I_I2S_CHAN_SEL_MASK,
+ SUN4I_I2S_CHAN_SEL(channels));
+
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
+ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
+ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
+ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
+ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
+
+ switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_DSP_A:
+ case SND_SOC_DAIFMT_DSP_B:
+ lrck_period = slot_width * slots;
+ break;
+
+ case SND_SOC_DAIFMT_LEFT_J:
+ case SND_SOC_DAIFMT_RIGHT_J:
+ case SND_SOC_DAIFMT_I2S:
+ lrck_period = slot_width;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
+ SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
+ SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period));
+
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
+ SUN8I_I2S_TX_CHAN_EN_MASK,
+ SUN8I_I2S_TX_CHAN_EN(channels));
+
+ return 0;
+}
+
+static int sun50i_h6_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
+ unsigned int channels, unsigned int slots,
+ unsigned int slot_width)
+{
+ unsigned int lrck_period;
+
+ /* Map the channels for playback and capture */
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP0_REG(0), 0xFEDCBA98);
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG(0), 0x76543210);
+ if (i2s->variant->num_din_pins > 1) {
+ regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP0_REG, 0x0F0E0D0C);
+ regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP1_REG, 0x0B0A0908);
+ regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP2_REG, 0x07060504);
+ regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP3_REG, 0x03020100);
+ } else {
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0xFEDCBA98);
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x76543210);
+ }
+
+ /* Configure the channels */
+ regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0),
+ SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
+ SUN50I_H6_I2S_TX_CHAN_SEL(channels));
+ regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG,
+ SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
+ SUN50I_H6_I2S_TX_CHAN_SEL(channels));
+
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
+ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
+ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
+ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
+ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
+
+ switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_DSP_A:
+ case SND_SOC_DAIFMT_DSP_B:
+ lrck_period = slot_width * slots;
+ break;
+
+ case SND_SOC_DAIFMT_LEFT_J:
+ case SND_SOC_DAIFMT_RIGHT_J:
+ case SND_SOC_DAIFMT_I2S:
+ lrck_period = slot_width;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
+ SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
+ SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period));
+
+ regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0),
+ SUN50I_H6_I2S_TX_CHAN_EN_MASK,
+ SUN50I_H6_I2S_TX_CHAN_EN(channels));
+
+ return 0;
+}
+
+static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
+ unsigned int word_size = params_width(params);
+ unsigned int slot_width = params_physical_width(params);
+ unsigned int channels = params_channels(params);
+
+ unsigned int slots = channels;
+
+ int ret, sr, wss;
+ u32 width;
+
+ if (i2s->slots)
+ slots = i2s->slots;
+
+ if (i2s->slot_width)
+ slot_width = i2s->slot_width;
+
+ ret = i2s->variant->set_chan_cfg(i2s, channels, slots, slot_width);
+ if (ret < 0) {
+ dev_err(dai->dev, "Invalid channel configuration\n");
+ return ret;
+ }
+
+ /* Set significant bits in our FIFOs */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
+ SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
+ SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
+ SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
+ SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
+
+ switch (params_physical_width(params)) {
+ case 16:
+ width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+ break;
+ case 32:
+ width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ break;
+ default:
+ dev_err(dai->dev, "Unsupported physical sample width: %d\n",
+ params_physical_width(params));
+ return -EINVAL;
+ }
+ i2s->playback_dma_data.addr_width = width;
+
+ sr = i2s->variant->get_sr(word_size);
+ if (sr < 0)
+ return -EINVAL;
+
+ wss = i2s->variant->get_wss(slot_width);
+ if (wss < 0)
+ return -EINVAL;
+
+ regmap_field_write(i2s->field_fmt_wss, wss);
+ regmap_field_write(i2s->field_fmt_sr, sr);
+
+ return sun4i_i2s_set_clk_rate(dai, params_rate(params),
+ slots, slot_width);
+}
+
+static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
+ unsigned int fmt)
+{
+ u32 val;
+
+ /* DAI clock polarity */
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_IB_IF:
+ /* Invert both clocks */
+ val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED |
+ SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ /* Invert bit clock */
+ val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED;
+ break;
+ case SND_SOC_DAIFMT_NB_IF:
+ /* Invert frame clock */
+ val = SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
+ break;
+ case SND_SOC_DAIFMT_NB_NF:
+ val = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
+ SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK |
+ SUN4I_I2S_FMT0_BCLK_POLARITY_MASK,
+ val);
+
+ /* DAI Mode */
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_I2S:
+ val = SUN4I_I2S_FMT0_FMT_I2S;
+ break;
+
+ case SND_SOC_DAIFMT_LEFT_J:
+ val = SUN4I_I2S_FMT0_FMT_LEFT_J;
+ break;
+
+ case SND_SOC_DAIFMT_RIGHT_J:
+ val = SUN4I_I2S_FMT0_FMT_RIGHT_J;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
+ SUN4I_I2S_FMT0_FMT_MASK, val);
+
+ /* DAI clock master masks */
+ switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
+ case SND_SOC_DAIFMT_BP_FP:
+ /* BCLK and LRCLK master */
+ val = SUN4I_I2S_CTRL_MODE_MASTER;
+ break;
+
+ case SND_SOC_DAIFMT_BC_FC:
+ /* BCLK and LRCLK slave */
+ val = SUN4I_I2S_CTRL_MODE_SLAVE;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+ SUN4I_I2S_CTRL_MODE_MASK, val);
+
+ return 0;
+}
+
+static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
+ unsigned int fmt)
+{
+ u32 mode, val;
+ u8 offset;
+
+ /*
+ * DAI clock polarity
+ *
+ * The setup for LRCK contradicts the datasheet, but under a
+ * scope it's clear that the LRCK polarity is reversed
+ * compared to the expected polarity on the bus.
+ */
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_IB_IF:
+ /* Invert both clocks */
+ val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ /* Invert bit clock */
+ val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED |
+ SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
+ break;
+ case SND_SOC_DAIFMT_NB_IF:
+ /* Invert frame clock */
+ val = 0;
+ break;
+ case SND_SOC_DAIFMT_NB_NF:
+ val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
+ SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK |
+ SUN8I_I2S_FMT0_BCLK_POLARITY_MASK,
+ val);
+
+ /* DAI Mode */
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_DSP_A:
+ mode = SUN8I_I2S_CTRL_MODE_PCM;
+ offset = 1;
+ break;
+
+ case SND_SOC_DAIFMT_DSP_B:
+ mode = SUN8I_I2S_CTRL_MODE_PCM;
+ offset = 0;
+ break;
+
+ case SND_SOC_DAIFMT_I2S:
+ mode = SUN8I_I2S_CTRL_MODE_LEFT;
+ offset = 1;
+ break;
+
+ case SND_SOC_DAIFMT_LEFT_J:
+ mode = SUN8I_I2S_CTRL_MODE_LEFT;
+ offset = 0;
+ break;
+
+ case SND_SOC_DAIFMT_RIGHT_J:
+ mode = SUN8I_I2S_CTRL_MODE_RIGHT;
+ offset = 0;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+ SUN8I_I2S_CTRL_MODE_MASK, mode);
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
+ SUN8I_I2S_TX_CHAN_OFFSET_MASK,
+ SUN8I_I2S_TX_CHAN_OFFSET(offset));
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
+ SUN8I_I2S_TX_CHAN_OFFSET_MASK,
+ SUN8I_I2S_TX_CHAN_OFFSET(offset));
+
+ /* DAI clock master masks */
+ switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
+ case SND_SOC_DAIFMT_BP_FP:
+ /* BCLK and LRCLK master */
+ val = SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT;
+ break;
+
+ case SND_SOC_DAIFMT_BC_FC:
+ /* BCLK and LRCLK slave */
+ val = 0;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+ SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT,
+ val);
+
+ /* Set sign extension to pad out LSB with 0 */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG,
+ SUN8I_I2S_FMT1_REG_SEXT_MASK,
+ SUN8I_I2S_FMT1_REG_SEXT(0));
+
+ return 0;
+}
+
+static int sun50i_h6_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
+ unsigned int fmt)
+{
+ u32 mode, val;
+ u8 offset;
+
+ /*
+ * DAI clock polarity
+ *
+ * The setup for LRCK contradicts the datasheet, but under a
+ * scope it's clear that the LRCK polarity is reversed
+ * compared to the expected polarity on the bus.
+ */
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_IB_IF:
+ /* Invert both clocks */
+ val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ /* Invert bit clock */
+ val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED |
+ SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
+ break;
+ case SND_SOC_DAIFMT_NB_IF:
+ /* Invert frame clock */
+ val = 0;
+ break;
+ case SND_SOC_DAIFMT_NB_NF:
+ val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
+ SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK |
+ SUN8I_I2S_FMT0_BCLK_POLARITY_MASK,
+ val);
+
+ /* DAI Mode */
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_DSP_A:
+ mode = SUN8I_I2S_CTRL_MODE_PCM;
+ offset = 1;
+ break;
+
+ case SND_SOC_DAIFMT_DSP_B:
+ mode = SUN8I_I2S_CTRL_MODE_PCM;
+ offset = 0;
+ break;
+
+ case SND_SOC_DAIFMT_I2S:
+ mode = SUN8I_I2S_CTRL_MODE_LEFT;
+ offset = 1;
+ break;
+
+ case SND_SOC_DAIFMT_LEFT_J:
+ mode = SUN8I_I2S_CTRL_MODE_LEFT;
+ offset = 0;
+ break;
+
+ case SND_SOC_DAIFMT_RIGHT_J:
+ mode = SUN8I_I2S_CTRL_MODE_RIGHT;
+ offset = 0;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+ SUN8I_I2S_CTRL_MODE_MASK, mode);
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
+ SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK,
+ SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset));
+ regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG,
+ SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK,
+ SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset));
+
+ /* DAI clock master masks */
+ switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
+ case SND_SOC_DAIFMT_BP_FP:
+ /* BCLK and LRCLK master */
+ val = SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT;
+ break;
+
+ case SND_SOC_DAIFMT_BC_FC:
+ /* BCLK and LRCLK slave */
+ val = 0;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+ SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT,
+ val);
+
+ /* Set sign extension to pad out LSB with 0 */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG,
+ SUN8I_I2S_FMT1_REG_SEXT_MASK,
+ SUN8I_I2S_FMT1_REG_SEXT(0));
+
+ return 0;
+}
+
+static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+ struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
+ int ret;
+
+ ret = i2s->variant->set_fmt(i2s, fmt);
+ if (ret) {
+ dev_err(dai->dev, "Unsupported format configuration\n");
+ return ret;
+ }
+
+ i2s->format = fmt;
+
+ return 0;
+}
+
+static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s)
+{
+ /* Flush RX FIFO */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
+ SUN4I_I2S_FIFO_CTRL_FLUSH_RX,
+ SUN4I_I2S_FIFO_CTRL_FLUSH_RX);
+
+ /* Clear RX counter */
+ regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0);
+
+ /* Enable RX Block */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+ SUN4I_I2S_CTRL_RX_EN,
+ SUN4I_I2S_CTRL_RX_EN);
+
+ /* Enable RX DRQ */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
+ SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
+ SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN);
+}
+
+static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s)
+{
+ /* Flush TX FIFO */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
+ SUN4I_I2S_FIFO_CTRL_FLUSH_TX,
+ SUN4I_I2S_FIFO_CTRL_FLUSH_TX);
+
+ /* Clear TX counter */
+ regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0);
+
+ /* Enable TX Block */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+ SUN4I_I2S_CTRL_TX_EN,
+ SUN4I_I2S_CTRL_TX_EN);
+
+ /* Enable TX DRQ */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
+ SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
+ SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN);
+}
+
+static void sun4i_i2s_stop_capture(struct sun4i_i2s *i2s)
+{
+ /* Disable RX Block */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+ SUN4I_I2S_CTRL_RX_EN,
+ 0);
+
+ /* Disable RX DRQ */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
+ SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
+ 0);
+}
+
+static void sun4i_i2s_stop_playback(struct sun4i_i2s *i2s)
+{
+ /* Disable TX Block */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+ SUN4I_I2S_CTRL_TX_EN,
+ 0);
+
+ /* Disable TX DRQ */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
+ SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
+ 0);
+}
+
+static int sun4i_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
+ struct snd_soc_dai *dai)
+{
+ struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ sun4i_i2s_start_playback(i2s);
+ else
+ sun4i_i2s_start_capture(i2s);
+ break;
+
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ sun4i_i2s_stop_playback(i2s);
+ else
+ sun4i_i2s_stop_capture(i2s);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
+ unsigned int freq, int dir)
+{
+ struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
+
+ if (clk_id != 0)
+ return -EINVAL;
+
+ i2s->mclk_freq = freq;
+
+ return 0;
+}
+
+static int sun4i_i2s_set_tdm_slot(struct snd_soc_dai *dai,
+ unsigned int tx_mask, unsigned int rx_mask,
+ int slots, int slot_width)
+{
+ struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
+
+ if (slots > 8)
+ return -EINVAL;
+
+ i2s->slots = slots;
+ i2s->slot_width = slot_width;
+
+ return 0;
+}
+
+static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)
+{
+ struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
+
+ snd_soc_dai_init_dma_data(dai,
+ &i2s->playback_dma_data,
+ &i2s->capture_dma_data);
+
+ return 0;
+}
+
+static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = {
+ .probe = sun4i_i2s_dai_probe,
+ .hw_params = sun4i_i2s_hw_params,
+ .set_fmt = sun4i_i2s_set_fmt,
+ .set_sysclk = sun4i_i2s_set_sysclk,
+ .set_tdm_slot = sun4i_i2s_set_tdm_slot,
+ .trigger = sun4i_i2s_trigger,
+};
+
+#define SUN4I_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+ SNDRV_PCM_FMTBIT_S20_LE | \
+ SNDRV_PCM_FMTBIT_S24_LE)
+
+static struct snd_soc_dai_driver sun4i_i2s_dai = {
+ .capture = {
+ .stream_name = "Capture",
+ .channels_min = 1,
+ .channels_max = 8,
+ .rates = SNDRV_PCM_RATE_8000_192000,
+ .formats = SUN4I_FORMATS,
+ },
+ .playback = {
+ .stream_name = "Playback",
+ .channels_min = 1,
+ .channels_max = 8,
+ .rates = SNDRV_PCM_RATE_8000_192000,
+ .formats = SUN4I_FORMATS,
+ },
+ .ops = &sun4i_i2s_dai_ops,
+ .symmetric_rate = 1,
+};
+
+static const struct snd_soc_component_driver sun4i_i2s_component = {
+ .name = "sun4i-dai",
+ .legacy_dai_naming = 1,
+};
+
+static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case SUN4I_I2S_FIFO_TX_REG:
+ return false;
+
+ default:
+ return true;
+ }
+}
+
+static bool sun4i_i2s_wr_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case SUN4I_I2S_FIFO_RX_REG:
+ case SUN4I_I2S_FIFO_STA_REG:
+ return false;
+
+ default:
+ return true;
+ }
+}
+
+static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case SUN4I_I2S_FIFO_RX_REG:
+ case SUN4I_I2S_INT_STA_REG:
+ case SUN4I_I2S_RX_CNT_REG:
+ case SUN4I_I2S_TX_CNT_REG:
+ return true;
+
+ default:
+ return false;
+ }
+}
+
+static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case SUN8I_I2S_FIFO_TX_REG:
+ return false;
+
+ default:
+ return true;
+ }
+}
+
+static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case SUN4I_I2S_FIFO_CTRL_REG:
+ case SUN4I_I2S_FIFO_RX_REG:
+ case SUN4I_I2S_FIFO_STA_REG:
+ case SUN4I_I2S_RX_CNT_REG:
+ case SUN4I_I2S_TX_CNT_REG:
+ case SUN8I_I2S_FIFO_TX_REG:
+ case SUN8I_I2S_INT_STA_REG:
+ return true;
+
+ default:
+ return false;
+ }
+}
+
+static const struct reg_default sun4i_i2s_reg_defaults[] = {
+ { SUN4I_I2S_CTRL_REG, 0x00000000 },
+ { SUN4I_I2S_FMT0_REG, 0x0000000c },
+ { SUN4I_I2S_FMT1_REG, 0x00004020 },
+ { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
+ { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
+ { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
+ { SUN4I_I2S_TX_CHAN_SEL_REG, 0x00000001 },
+ { SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210 },
+ { SUN4I_I2S_RX_CHAN_SEL_REG, 0x00000001 },
+ { SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 },
+};
+
+static const struct reg_default sun8i_i2s_reg_defaults[] = {
+ { SUN4I_I2S_CTRL_REG, 0x00060000 },
+ { SUN4I_I2S_FMT0_REG, 0x00000033 },
+ { SUN4I_I2S_FMT1_REG, 0x00000030 },
+ { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
+ { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
+ { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
+ { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
+ { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 },
+ { SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 },
+ { SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 },
+ { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 },
+};
+
+static const struct reg_default sun50i_h6_i2s_reg_defaults[] = {
+ { SUN4I_I2S_CTRL_REG, 0x00060000 },
+ { SUN4I_I2S_FMT0_REG, 0x00000033 },
+ { SUN4I_I2S_FMT1_REG, 0x00000030 },
+ { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
+ { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
+ { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
+ { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
+ { SUN50I_H6_I2S_TX_CHAN_SEL_REG(0), 0x00000000 },
+ { SUN50I_H6_I2S_TX_CHAN_MAP0_REG(0), 0x00000000 },
+ { SUN50I_H6_I2S_TX_CHAN_MAP1_REG(0), 0x00000000 },
+ { SUN50I_H6_I2S_RX_CHAN_SEL_REG, 0x00000000 },
+ { SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0x00000000 },
+ { SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x00000000 },
+};
+
+static const struct regmap_config sun4i_i2s_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = SUN4I_I2S_RX_CHAN_MAP_REG,
+
+ .cache_type = REGCACHE_FLAT,
+ .reg_defaults = sun4i_i2s_reg_defaults,
+ .num_reg_defaults = ARRAY_SIZE(sun4i_i2s_reg_defaults),
+ .writeable_reg = sun4i_i2s_wr_reg,
+ .readable_reg = sun4i_i2s_rd_reg,
+ .volatile_reg = sun4i_i2s_volatile_reg,
+};
+
+static const struct regmap_config sun8i_i2s_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = SUN8I_I2S_RX_CHAN_MAP_REG,
+ .cache_type = REGCACHE_FLAT,
+ .reg_defaults = sun8i_i2s_reg_defaults,
+ .num_reg_defaults = ARRAY_SIZE(sun8i_i2s_reg_defaults),
+ .writeable_reg = sun4i_i2s_wr_reg,
+ .readable_reg = sun8i_i2s_rd_reg,
+ .volatile_reg = sun8i_i2s_volatile_reg,
+};
+
+static const struct regmap_config sun50i_h6_i2s_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = SUN50I_R329_I2S_RX_CHAN_MAP3_REG,
+ .cache_type = REGCACHE_FLAT,
+ .reg_defaults = sun50i_h6_i2s_reg_defaults,
+ .num_reg_defaults = ARRAY_SIZE(sun50i_h6_i2s_reg_defaults),
+ .writeable_reg = sun4i_i2s_wr_reg,
+ .readable_reg = sun8i_i2s_rd_reg,
+ .volatile_reg = sun8i_i2s_volatile_reg,
+};
+
+static int sun4i_i2s_runtime_resume(struct device *dev)
+{
+ struct sun4i_i2s *i2s = dev_get_drvdata(dev);
+ int ret;
+
+ ret = clk_prepare_enable(i2s->bus_clk);
+ if (ret) {
+ dev_err(dev, "Failed to enable bus clock\n");
+ return ret;
+ }
+
+ regcache_cache_only(i2s->regmap, false);
+ regcache_mark_dirty(i2s->regmap);
+
+ ret = regcache_sync(i2s->regmap);
+ if (ret) {
+ dev_err(dev, "Failed to sync regmap cache\n");
+ goto err_disable_clk;
+ }
+
+ /* Enable the whole hardware block */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+ SUN4I_I2S_CTRL_GL_EN, SUN4I_I2S_CTRL_GL_EN);
+
+ /* Enable the first output line */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+ SUN4I_I2S_CTRL_SDO_EN_MASK,
+ SUN4I_I2S_CTRL_SDO_EN(0));
+
+ ret = clk_prepare_enable(i2s->mod_clk);
+ if (ret) {
+ dev_err(dev, "Failed to enable module clock\n");
+ goto err_disable_clk;
+ }
+
+ return 0;
+
+err_disable_clk:
+ clk_disable_unprepare(i2s->bus_clk);
+ return ret;
+}
+
+static int sun4i_i2s_runtime_suspend(struct device *dev)
+{
+ struct sun4i_i2s *i2s = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(i2s->mod_clk);
+
+ /* Disable our output lines */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+ SUN4I_I2S_CTRL_SDO_EN_MASK, 0);
+
+ /* Disable the whole hardware block */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+ SUN4I_I2S_CTRL_GL_EN, 0);
+
+ regcache_cache_only(i2s->regmap, true);
+
+ clk_disable_unprepare(i2s->bus_clk);
+
+ return 0;
+}
+
+static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
+ .has_reset = false,
+ .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG,
+ .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
+ .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
+ .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
+ .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
+ .bclk_dividers = sun4i_i2s_bclk_div,
+ .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
+ .mclk_dividers = sun4i_i2s_mclk_div,
+ .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
+ .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
+ .get_sr = sun4i_i2s_get_sr,
+ .get_wss = sun4i_i2s_get_wss,
+ .set_chan_cfg = sun4i_i2s_set_chan_cfg,
+ .set_fmt = sun4i_i2s_set_soc_fmt,
+};
+
+static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
+ .has_reset = true,
+ .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG,
+ .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
+ .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
+ .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
+ .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
+ .bclk_dividers = sun4i_i2s_bclk_div,
+ .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
+ .mclk_dividers = sun4i_i2s_mclk_div,
+ .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
+ .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
+ .get_sr = sun4i_i2s_get_sr,
+ .get_wss = sun4i_i2s_get_wss,
+ .set_chan_cfg = sun4i_i2s_set_chan_cfg,
+ .set_fmt = sun4i_i2s_set_soc_fmt,
+};
+
+/*
+ * This doesn't describe the TDM controller documented in the A83t
+ * datasheet, but the three undocumented I2S controller that use the
+ * older design.
+ */
+static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
+ .has_reset = true,
+ .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
+ .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
+ .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
+ .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
+ .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
+ .bclk_dividers = sun4i_i2s_bclk_div,
+ .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
+ .mclk_dividers = sun4i_i2s_mclk_div,
+ .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
+ .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
+ .get_sr = sun4i_i2s_get_sr,
+ .get_wss = sun4i_i2s_get_wss,
+ .set_chan_cfg = sun4i_i2s_set_chan_cfg,
+ .set_fmt = sun4i_i2s_set_soc_fmt,
+};
+
+static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
+ .has_reset = true,
+ .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
+ .sun4i_i2s_regmap = &sun8i_i2s_regmap_config,
+ .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
+ .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
+ .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
+ .bclk_dividers = sun8i_i2s_clk_div,
+ .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
+ .mclk_dividers = sun8i_i2s_clk_div,
+ .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
+ .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate,
+ .get_sr = sun8i_i2s_get_sr_wss,
+ .get_wss = sun8i_i2s_get_sr_wss,
+ .set_chan_cfg = sun8i_i2s_set_chan_cfg,
+ .set_fmt = sun8i_i2s_set_soc_fmt,
+};
+
+static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
+ .has_reset = true,
+ .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
+ .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
+ .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
+ .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
+ .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
+ .bclk_dividers = sun4i_i2s_bclk_div,
+ .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
+ .mclk_dividers = sun4i_i2s_mclk_div,
+ .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
+ .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
+ .get_sr = sun4i_i2s_get_sr,
+ .get_wss = sun4i_i2s_get_wss,
+ .set_chan_cfg = sun4i_i2s_set_chan_cfg,
+ .set_fmt = sun4i_i2s_set_soc_fmt,
+};
+
+static const struct sun4i_i2s_quirks sun50i_h6_i2s_quirks = {
+ .has_reset = true,
+ .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
+ .sun4i_i2s_regmap = &sun50i_h6_i2s_regmap_config,
+ .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
+ .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
+ .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
+ .bclk_dividers = sun8i_i2s_clk_div,
+ .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
+ .mclk_dividers = sun8i_i2s_clk_div,
+ .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
+ .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate,
+ .get_sr = sun8i_i2s_get_sr_wss,
+ .get_wss = sun8i_i2s_get_sr_wss,
+ .set_chan_cfg = sun50i_h6_i2s_set_chan_cfg,
+ .set_fmt = sun50i_h6_i2s_set_soc_fmt,
+};
+
+static const struct sun4i_i2s_quirks sun50i_r329_i2s_quirks = {
+ .has_reset = true,
+ .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
+ .sun4i_i2s_regmap = &sun50i_h6_i2s_regmap_config,
+ .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
+ .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
+ .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
+ .num_din_pins = 4,
+ .num_dout_pins = 4,
+ .bclk_dividers = sun8i_i2s_clk_div,
+ .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
+ .mclk_dividers = sun8i_i2s_clk_div,
+ .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
+ .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate,
+ .get_sr = sun8i_i2s_get_sr_wss,
+ .get_wss = sun8i_i2s_get_sr_wss,
+ .set_chan_cfg = sun50i_h6_i2s_set_chan_cfg,
+ .set_fmt = sun50i_h6_i2s_set_soc_fmt,
+};
+
+static int sun4i_i2s_init_regmap_fields(struct device *dev,
+ struct sun4i_i2s *i2s)
+{
+ i2s->field_clkdiv_mclk_en =
+ devm_regmap_field_alloc(dev, i2s->regmap,
+ i2s->variant->field_clkdiv_mclk_en);
+ if (IS_ERR(i2s->field_clkdiv_mclk_en))
+ return PTR_ERR(i2s->field_clkdiv_mclk_en);
+
+ i2s->field_fmt_wss =
+ devm_regmap_field_alloc(dev, i2s->regmap,
+ i2s->variant->field_fmt_wss);
+ if (IS_ERR(i2s->field_fmt_wss))
+ return PTR_ERR(i2s->field_fmt_wss);
+
+ i2s->field_fmt_sr =
+ devm_regmap_field_alloc(dev, i2s->regmap,
+ i2s->variant->field_fmt_sr);
+ if (IS_ERR(i2s->field_fmt_sr))
+ return PTR_ERR(i2s->field_fmt_sr);
+
+ return 0;
+}
+
+static int sun4i_i2s_probe(struct platform_device *pdev)
+{
+ struct sun4i_i2s *i2s;
+ struct resource *res;
+ void __iomem *regs;
+ int irq, ret;
+
+ i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
+ if (!i2s)
+ return -ENOMEM;
+ platform_set_drvdata(pdev, i2s);
+
+ regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+
+ i2s->variant = of_device_get_match_data(&pdev->dev);
+ if (!i2s->variant) {
+ dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
+ return -ENODEV;
+ }
+
+ i2s->bus_clk = devm_clk_get(&pdev->dev, "apb");
+ if (IS_ERR(i2s->bus_clk)) {
+ dev_err(&pdev->dev, "Can't get our bus clock\n");
+ return PTR_ERR(i2s->bus_clk);
+ }
+
+ i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
+ i2s->variant->sun4i_i2s_regmap);
+ if (IS_ERR(i2s->regmap)) {
+ dev_err(&pdev->dev, "Regmap initialisation failed\n");
+ return PTR_ERR(i2s->regmap);
+ }
+
+ i2s->mod_clk = devm_clk_get(&pdev->dev, "mod");
+ if (IS_ERR(i2s->mod_clk)) {
+ dev_err(&pdev->dev, "Can't get our mod clock\n");
+ return PTR_ERR(i2s->mod_clk);
+ }
+
+ if (i2s->variant->has_reset) {
+ i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(i2s->rst)) {
+ dev_err(&pdev->dev, "Failed to get reset control\n");
+ return PTR_ERR(i2s->rst);
+ }
+ }
+
+ if (!IS_ERR(i2s->rst)) {
+ ret = reset_control_deassert(i2s->rst);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "Failed to deassert the reset control\n");
+ return -EINVAL;
+ }
+ }
+
+ i2s->playback_dma_data.addr = res->start +
+ i2s->variant->reg_offset_txdata;
+ i2s->playback_dma_data.maxburst = 8;
+
+ i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG;
+ i2s->capture_dma_data.maxburst = 8;
+
+ pm_runtime_enable(&pdev->dev);
+ if (!pm_runtime_enabled(&pdev->dev)) {
+ ret = sun4i_i2s_runtime_resume(&pdev->dev);
+ if (ret)
+ goto err_pm_disable;
+ }
+
+ ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s);
+ if (ret) {
+ dev_err(&pdev->dev, "Could not initialise regmap fields\n");
+ goto err_suspend;
+ }
+
+ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
+ if (ret) {
+ dev_err(&pdev->dev, "Could not register PCM\n");
+ goto err_suspend;
+ }
+
+ ret = devm_snd_soc_register_component(&pdev->dev,
+ &sun4i_i2s_component,
+ &sun4i_i2s_dai, 1);
+ if (ret) {
+ dev_err(&pdev->dev, "Could not register DAI\n");
+ goto err_suspend;
+ }
+
+ return 0;
+
+err_suspend:
+ if (!pm_runtime_status_suspended(&pdev->dev))
+ sun4i_i2s_runtime_suspend(&pdev->dev);
+err_pm_disable:
+ pm_runtime_disable(&pdev->dev);
+ if (!IS_ERR(i2s->rst))
+ reset_control_assert(i2s->rst);
+
+ return ret;
+}
+
+static void sun4i_i2s_remove(struct platform_device *pdev)
+{
+ struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev);
+
+ pm_runtime_disable(&pdev->dev);
+ if (!pm_runtime_status_suspended(&pdev->dev))
+ sun4i_i2s_runtime_suspend(&pdev->dev);
+
+ if (!IS_ERR(i2s->rst))
+ reset_control_assert(i2s->rst);
+}
+
+static const struct of_device_id sun4i_i2s_match[] = {
+ {
+ .compatible = "allwinner,sun4i-a10-i2s",
+ .data = &sun4i_a10_i2s_quirks,
+ },
+ {
+ .compatible = "allwinner,sun6i-a31-i2s",
+ .data = &sun6i_a31_i2s_quirks,
+ },
+ {
+ .compatible = "allwinner,sun8i-a83t-i2s",
+ .data = &sun8i_a83t_i2s_quirks,
+ },
+ {
+ .compatible = "allwinner,sun8i-h3-i2s",
+ .data = &sun8i_h3_i2s_quirks,
+ },
+ {
+ .compatible = "allwinner,sun50i-a64-codec-i2s",
+ .data = &sun50i_a64_codec_i2s_quirks,
+ },
+ {
+ .compatible = "allwinner,sun50i-h6-i2s",
+ .data = &sun50i_h6_i2s_quirks,
+ },
+ {
+ .compatible = "allwinner,sun50i-r329-i2s",
+ .data = &sun50i_r329_i2s_quirks,
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, sun4i_i2s_match);
+
+static const struct dev_pm_ops sun4i_i2s_pm_ops = {
+ .runtime_resume = sun4i_i2s_runtime_resume,
+ .runtime_suspend = sun4i_i2s_runtime_suspend,
+};
+
+static struct platform_driver sun4i_i2s_driver = {
+ .probe = sun4i_i2s_probe,
+ .remove_new = sun4i_i2s_remove,
+ .driver = {
+ .name = "sun4i-i2s",
+ .of_match_table = sun4i_i2s_match,
+ .pm = &sun4i_i2s_pm_ops,
+ },
+};
+module_platform_driver(sun4i_i2s_driver);
+
+MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>");
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
+MODULE_DESCRIPTION("Allwinner A10 I2S driver");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/sunxi/sun4i-spdif.c b/sound/soc/sunxi/sun4i-spdif.c
new file mode 100644
index 000000000..b849bb7cf
--- /dev/null
+++ b/sound/soc/sunxi/sun4i-spdif.c
@@ -0,0 +1,734 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * ALSA SoC SPDIF Audio Layer
+ *
+ * Copyright 2015 Andrea Venturi <be17068@iperbole.bo.it>
+ * Copyright 2015 Marcus Cooper <codekipper@gmail.com>
+ *
+ * Based on the Allwinner SDK driver, released under the GPL.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/regmap.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/spinlock.h>
+#include <sound/asoundef.h>
+#include <sound/dmaengine_pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#define SUN4I_SPDIF_CTL (0x00)
+ #define SUN4I_SPDIF_CTL_MCLKDIV(v) ((v) << 4) /* v even */
+ #define SUN4I_SPDIF_CTL_MCLKOUTEN BIT(2)
+ #define SUN4I_SPDIF_CTL_GEN BIT(1)
+ #define SUN4I_SPDIF_CTL_RESET BIT(0)
+
+#define SUN4I_SPDIF_TXCFG (0x04)
+ #define SUN4I_SPDIF_TXCFG_SINGLEMOD BIT(31)
+ #define SUN4I_SPDIF_TXCFG_ASS BIT(17)
+ #define SUN4I_SPDIF_TXCFG_NONAUDIO BIT(16)
+ #define SUN4I_SPDIF_TXCFG_TXRATIO(v) ((v) << 4)
+ #define SUN4I_SPDIF_TXCFG_TXRATIO_MASK GENMASK(8, 4)
+ #define SUN4I_SPDIF_TXCFG_FMTRVD GENMASK(3, 2)
+ #define SUN4I_SPDIF_TXCFG_FMT16BIT (0 << 2)
+ #define SUN4I_SPDIF_TXCFG_FMT20BIT (1 << 2)
+ #define SUN4I_SPDIF_TXCFG_FMT24BIT (2 << 2)
+ #define SUN4I_SPDIF_TXCFG_CHSTMODE BIT(1)
+ #define SUN4I_SPDIF_TXCFG_TXEN BIT(0)
+
+#define SUN4I_SPDIF_RXCFG (0x08)
+ #define SUN4I_SPDIF_RXCFG_LOCKFLAG BIT(4)
+ #define SUN4I_SPDIF_RXCFG_CHSTSRC BIT(3)
+ #define SUN4I_SPDIF_RXCFG_CHSTCP BIT(1)
+ #define SUN4I_SPDIF_RXCFG_RXEN BIT(0)
+
+#define SUN4I_SPDIF_TXFIFO (0x0C)
+
+#define SUN4I_SPDIF_RXFIFO (0x10)
+
+#define SUN4I_SPDIF_FCTL (0x14)
+ #define SUN4I_SPDIF_FCTL_FIFOSRC BIT(31)
+ #define SUN4I_SPDIF_FCTL_FTX BIT(17)
+ #define SUN4I_SPDIF_FCTL_FRX BIT(16)
+ #define SUN4I_SPDIF_FCTL_TXTL(v) ((v) << 8)
+ #define SUN4I_SPDIF_FCTL_TXTL_MASK GENMASK(12, 8)
+ #define SUN4I_SPDIF_FCTL_RXTL(v) ((v) << 3)
+ #define SUN4I_SPDIF_FCTL_RXTL_MASK GENMASK(7, 3)
+ #define SUN4I_SPDIF_FCTL_TXIM BIT(2)
+ #define SUN4I_SPDIF_FCTL_RXOM(v) ((v) << 0)
+ #define SUN4I_SPDIF_FCTL_RXOM_MASK GENMASK(1, 0)
+
+#define SUN50I_H6_SPDIF_FCTL (0x14)
+ #define SUN50I_H6_SPDIF_FCTL_HUB_EN BIT(31)
+ #define SUN50I_H6_SPDIF_FCTL_FTX BIT(30)
+ #define SUN50I_H6_SPDIF_FCTL_FRX BIT(29)
+ #define SUN50I_H6_SPDIF_FCTL_TXTL(v) ((v) << 12)
+ #define SUN50I_H6_SPDIF_FCTL_TXTL_MASK GENMASK(19, 12)
+ #define SUN50I_H6_SPDIF_FCTL_RXTL(v) ((v) << 4)
+ #define SUN50I_H6_SPDIF_FCTL_RXTL_MASK GENMASK(10, 4)
+ #define SUN50I_H6_SPDIF_FCTL_TXIM BIT(2)
+ #define SUN50I_H6_SPDIF_FCTL_RXOM(v) ((v) << 0)
+ #define SUN50I_H6_SPDIF_FCTL_RXOM_MASK GENMASK(1, 0)
+
+#define SUN4I_SPDIF_FSTA (0x18)
+ #define SUN4I_SPDIF_FSTA_TXE BIT(14)
+ #define SUN4I_SPDIF_FSTA_TXECNTSHT (8)
+ #define SUN4I_SPDIF_FSTA_RXA BIT(6)
+ #define SUN4I_SPDIF_FSTA_RXACNTSHT (0)
+
+#define SUN4I_SPDIF_INT (0x1C)
+ #define SUN4I_SPDIF_INT_RXLOCKEN BIT(18)
+ #define SUN4I_SPDIF_INT_RXUNLOCKEN BIT(17)
+ #define SUN4I_SPDIF_INT_RXPARERREN BIT(16)
+ #define SUN4I_SPDIF_INT_TXDRQEN BIT(7)
+ #define SUN4I_SPDIF_INT_TXUIEN BIT(6)
+ #define SUN4I_SPDIF_INT_TXOIEN BIT(5)
+ #define SUN4I_SPDIF_INT_TXEIEN BIT(4)
+ #define SUN4I_SPDIF_INT_RXDRQEN BIT(2)
+ #define SUN4I_SPDIF_INT_RXOIEN BIT(1)
+ #define SUN4I_SPDIF_INT_RXAIEN BIT(0)
+
+#define SUN4I_SPDIF_ISTA (0x20)
+ #define SUN4I_SPDIF_ISTA_RXLOCKSTA BIT(18)
+ #define SUN4I_SPDIF_ISTA_RXUNLOCKSTA BIT(17)
+ #define SUN4I_SPDIF_ISTA_RXPARERRSTA BIT(16)
+ #define SUN4I_SPDIF_ISTA_TXUSTA BIT(6)
+ #define SUN4I_SPDIF_ISTA_TXOSTA BIT(5)
+ #define SUN4I_SPDIF_ISTA_TXESTA BIT(4)
+ #define SUN4I_SPDIF_ISTA_RXOSTA BIT(1)
+ #define SUN4I_SPDIF_ISTA_RXASTA BIT(0)
+
+#define SUN8I_SPDIF_TXFIFO (0x20)
+
+#define SUN4I_SPDIF_TXCNT (0x24)
+
+#define SUN4I_SPDIF_RXCNT (0x28)
+
+#define SUN4I_SPDIF_TXCHSTA0 (0x2C)
+ #define SUN4I_SPDIF_TXCHSTA0_CLK(v) ((v) << 28)
+ #define SUN4I_SPDIF_TXCHSTA0_SAMFREQ(v) ((v) << 24)
+ #define SUN4I_SPDIF_TXCHSTA0_SAMFREQ_MASK GENMASK(27, 24)
+ #define SUN4I_SPDIF_TXCHSTA0_CHNUM(v) ((v) << 20)
+ #define SUN4I_SPDIF_TXCHSTA0_CHNUM_MASK GENMASK(23, 20)
+ #define SUN4I_SPDIF_TXCHSTA0_SRCNUM(v) ((v) << 16)
+ #define SUN4I_SPDIF_TXCHSTA0_CATACOD(v) ((v) << 8)
+ #define SUN4I_SPDIF_TXCHSTA0_MODE(v) ((v) << 6)
+ #define SUN4I_SPDIF_TXCHSTA0_EMPHASIS(v) ((v) << 3)
+ #define SUN4I_SPDIF_TXCHSTA0_CP BIT(2)
+ #define SUN4I_SPDIF_TXCHSTA0_AUDIO BIT(1)
+ #define SUN4I_SPDIF_TXCHSTA0_PRO BIT(0)
+
+#define SUN4I_SPDIF_TXCHSTA1 (0x30)
+ #define SUN4I_SPDIF_TXCHSTA1_CGMSA(v) ((v) << 8)
+ #define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ(v) ((v) << 4)
+ #define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ_MASK GENMASK(7, 4)
+ #define SUN4I_SPDIF_TXCHSTA1_SAMWORDLEN(v) ((v) << 1)
+ #define SUN4I_SPDIF_TXCHSTA1_MAXWORDLEN BIT(0)
+
+#define SUN4I_SPDIF_RXCHSTA0 (0x34)
+ #define SUN4I_SPDIF_RXCHSTA0_CLK(v) ((v) << 28)
+ #define SUN4I_SPDIF_RXCHSTA0_SAMFREQ(v) ((v) << 24)
+ #define SUN4I_SPDIF_RXCHSTA0_CHNUM(v) ((v) << 20)
+ #define SUN4I_SPDIF_RXCHSTA0_SRCNUM(v) ((v) << 16)
+ #define SUN4I_SPDIF_RXCHSTA0_CATACOD(v) ((v) << 8)
+ #define SUN4I_SPDIF_RXCHSTA0_MODE(v) ((v) << 6)
+ #define SUN4I_SPDIF_RXCHSTA0_EMPHASIS(v) ((v) << 3)
+ #define SUN4I_SPDIF_RXCHSTA0_CP BIT(2)
+ #define SUN4I_SPDIF_RXCHSTA0_AUDIO BIT(1)
+ #define SUN4I_SPDIF_RXCHSTA0_PRO BIT(0)
+
+#define SUN4I_SPDIF_RXCHSTA1 (0x38)
+ #define SUN4I_SPDIF_RXCHSTA1_CGMSA(v) ((v) << 8)
+ #define SUN4I_SPDIF_RXCHSTA1_ORISAMFREQ(v) ((v) << 4)
+ #define SUN4I_SPDIF_RXCHSTA1_SAMWORDLEN(v) ((v) << 1)
+ #define SUN4I_SPDIF_RXCHSTA1_MAXWORDLEN BIT(0)
+
+/* Defines for Sampling Frequency */
+#define SUN4I_SPDIF_SAMFREQ_44_1KHZ 0x0
+#define SUN4I_SPDIF_SAMFREQ_NOT_INDICATED 0x1
+#define SUN4I_SPDIF_SAMFREQ_48KHZ 0x2
+#define SUN4I_SPDIF_SAMFREQ_32KHZ 0x3
+#define SUN4I_SPDIF_SAMFREQ_22_05KHZ 0x4
+#define SUN4I_SPDIF_SAMFREQ_24KHZ 0x6
+#define SUN4I_SPDIF_SAMFREQ_88_2KHZ 0x8
+#define SUN4I_SPDIF_SAMFREQ_76_8KHZ 0x9
+#define SUN4I_SPDIF_SAMFREQ_96KHZ 0xa
+#define SUN4I_SPDIF_SAMFREQ_176_4KHZ 0xc
+#define SUN4I_SPDIF_SAMFREQ_192KHZ 0xe
+
+/**
+ * struct sun4i_spdif_quirks - Differences between SoC variants.
+ *
+ * @reg_dac_txdata: TX FIFO offset for DMA config.
+ * @has_reset: SoC needs reset deasserted.
+ * @val_fctl_ftx: TX FIFO flush bitmask.
+ */
+struct sun4i_spdif_quirks {
+ unsigned int reg_dac_txdata;
+ bool has_reset;
+ unsigned int val_fctl_ftx;
+};
+
+struct sun4i_spdif_dev {
+ struct platform_device *pdev;
+ struct clk *spdif_clk;
+ struct clk *apb_clk;
+ struct reset_control *rst;
+ struct snd_soc_dai_driver cpu_dai_drv;
+ struct regmap *regmap;
+ struct snd_dmaengine_dai_dma_data dma_params_tx;
+ const struct sun4i_spdif_quirks *quirks;
+ spinlock_t lock;
+};
+
+static void sun4i_spdif_configure(struct sun4i_spdif_dev *host)
+{
+ const struct sun4i_spdif_quirks *quirks = host->quirks;
+
+ /* soft reset SPDIF */
+ regmap_write(host->regmap, SUN4I_SPDIF_CTL, SUN4I_SPDIF_CTL_RESET);
+
+ /* flush TX FIFO */
+ regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,
+ quirks->val_fctl_ftx, quirks->val_fctl_ftx);
+
+ /* clear TX counter */
+ regmap_write(host->regmap, SUN4I_SPDIF_TXCNT, 0);
+}
+
+static void sun4i_snd_txctrl_on(struct snd_pcm_substream *substream,
+ struct sun4i_spdif_dev *host)
+{
+ if (substream->runtime->channels == 1)
+ regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
+ SUN4I_SPDIF_TXCFG_SINGLEMOD,
+ SUN4I_SPDIF_TXCFG_SINGLEMOD);
+
+ /* SPDIF TX ENABLE */
+ regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
+ SUN4I_SPDIF_TXCFG_TXEN, SUN4I_SPDIF_TXCFG_TXEN);
+
+ /* DRQ ENABLE */
+ regmap_update_bits(host->regmap, SUN4I_SPDIF_INT,
+ SUN4I_SPDIF_INT_TXDRQEN, SUN4I_SPDIF_INT_TXDRQEN);
+
+ /* Global enable */
+ regmap_update_bits(host->regmap, SUN4I_SPDIF_CTL,
+ SUN4I_SPDIF_CTL_GEN, SUN4I_SPDIF_CTL_GEN);
+}
+
+static void sun4i_snd_txctrl_off(struct snd_pcm_substream *substream,
+ struct sun4i_spdif_dev *host)
+{
+ /* SPDIF TX DISABLE */
+ regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
+ SUN4I_SPDIF_TXCFG_TXEN, 0);
+
+ /* DRQ DISABLE */
+ regmap_update_bits(host->regmap, SUN4I_SPDIF_INT,
+ SUN4I_SPDIF_INT_TXDRQEN, 0);
+
+ /* Global disable */
+ regmap_update_bits(host->regmap, SUN4I_SPDIF_CTL,
+ SUN4I_SPDIF_CTL_GEN, 0);
+}
+
+static int sun4i_spdif_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
+
+ if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
+ return -EINVAL;
+
+ sun4i_spdif_configure(host);
+
+ return 0;
+}
+
+static int sun4i_spdif_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *cpu_dai)
+{
+ int ret = 0;
+ int fmt;
+ unsigned long rate = params_rate(params);
+ u32 mclk_div = 0;
+ unsigned int mclk = 0;
+ u32 reg_val;
+ struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
+ struct platform_device *pdev = host->pdev;
+
+ /* Add the PCM and raw data select interface */
+ switch (params_channels(params)) {
+ case 1: /* PCM mode */
+ case 2:
+ fmt = 0;
+ break;
+ case 4: /* raw data mode */
+ fmt = SUN4I_SPDIF_TXCFG_NONAUDIO;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (params_format(params)) {
+ case SNDRV_PCM_FORMAT_S16_LE:
+ fmt |= SUN4I_SPDIF_TXCFG_FMT16BIT;
+ break;
+ case SNDRV_PCM_FORMAT_S20_3LE:
+ fmt |= SUN4I_SPDIF_TXCFG_FMT20BIT;
+ break;
+ case SNDRV_PCM_FORMAT_S24_LE:
+ fmt |= SUN4I_SPDIF_TXCFG_FMT24BIT;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (rate) {
+ case 22050:
+ case 44100:
+ case 88200:
+ case 176400:
+ mclk = 22579200;
+ break;
+ case 24000:
+ case 32000:
+ case 48000:
+ case 96000:
+ case 192000:
+ mclk = 24576000;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ ret = clk_set_rate(host->spdif_clk, mclk);
+ if (ret < 0) {
+ dev_err(&pdev->dev,
+ "Setting SPDIF clock rate for %d Hz failed!\n", mclk);
+ return ret;
+ }
+
+ regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,
+ SUN4I_SPDIF_FCTL_TXIM, SUN4I_SPDIF_FCTL_TXIM);
+
+ switch (rate) {
+ case 22050:
+ case 24000:
+ mclk_div = 8;
+ break;
+ case 32000:
+ mclk_div = 6;
+ break;
+ case 44100:
+ case 48000:
+ mclk_div = 4;
+ break;
+ case 88200:
+ case 96000:
+ mclk_div = 2;
+ break;
+ case 176400:
+ case 192000:
+ mclk_div = 1;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ reg_val = 0;
+ reg_val |= SUN4I_SPDIF_TXCFG_ASS;
+ reg_val |= fmt; /* set non audio and bit depth */
+ reg_val |= SUN4I_SPDIF_TXCFG_CHSTMODE;
+ reg_val |= SUN4I_SPDIF_TXCFG_TXRATIO(mclk_div - 1);
+ regmap_write(host->regmap, SUN4I_SPDIF_TXCFG, reg_val);
+
+ return 0;
+}
+
+static int sun4i_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
+ struct snd_soc_dai *dai)
+{
+ int ret = 0;
+ struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(dai);
+
+ if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
+ return -EINVAL;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ sun4i_snd_txctrl_on(substream, host);
+ break;
+
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ sun4i_snd_txctrl_off(substream, host);
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ return ret;
+}
+
+static int sun4i_spdif_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
+ uinfo->count = 1;
+
+ return 0;
+}
+
+static int sun4i_spdif_get_status_mask(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ u8 *status = ucontrol->value.iec958.status;
+
+ status[0] = 0xff;
+ status[1] = 0xff;
+ status[2] = 0xff;
+ status[3] = 0xff;
+ status[4] = 0xff;
+ status[5] = 0x03;
+
+ return 0;
+}
+
+static int sun4i_spdif_get_status(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
+ u8 *status = ucontrol->value.iec958.status;
+ unsigned long flags;
+ unsigned int reg;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ regmap_read(host->regmap, SUN4I_SPDIF_TXCHSTA0, &reg);
+
+ status[0] = reg & 0xff;
+ status[1] = (reg >> 8) & 0xff;
+ status[2] = (reg >> 16) & 0xff;
+ status[3] = (reg >> 24) & 0xff;
+
+ regmap_read(host->regmap, SUN4I_SPDIF_TXCHSTA1, &reg);
+
+ status[4] = reg & 0xff;
+ status[5] = (reg >> 8) & 0x3;
+
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ return 0;
+}
+
+static int sun4i_spdif_set_status(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
+ u8 *status = ucontrol->value.iec958.status;
+ unsigned long flags;
+ unsigned int reg;
+ bool chg0, chg1;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ reg = (u32)status[3] << 24;
+ reg |= (u32)status[2] << 16;
+ reg |= (u32)status[1] << 8;
+ reg |= (u32)status[0];
+
+ regmap_update_bits_check(host->regmap, SUN4I_SPDIF_TXCHSTA0,
+ GENMASK(31,0), reg, &chg0);
+
+ reg = (u32)status[5] << 8;
+ reg |= (u32)status[4];
+
+ regmap_update_bits_check(host->regmap, SUN4I_SPDIF_TXCHSTA1,
+ GENMASK(9,0), reg, &chg1);
+
+ reg = SUN4I_SPDIF_TXCFG_CHSTMODE;
+ if (status[0] & IEC958_AES0_NONAUDIO)
+ reg |= SUN4I_SPDIF_TXCFG_NONAUDIO;
+
+ regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
+ SUN4I_SPDIF_TXCFG_CHSTMODE |
+ SUN4I_SPDIF_TXCFG_NONAUDIO, reg);
+
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ return chg0 || chg1;
+}
+
+static struct snd_kcontrol_new sun4i_spdif_controls[] = {
+ {
+ .access = SNDRV_CTL_ELEM_ACCESS_READ,
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
+ .info = sun4i_spdif_info,
+ .get = sun4i_spdif_get_status_mask
+ },
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
+ .info = sun4i_spdif_info,
+ .get = sun4i_spdif_get_status,
+ .put = sun4i_spdif_set_status
+ }
+};
+
+static int sun4i_spdif_soc_dai_probe(struct snd_soc_dai *dai)
+{
+ struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(dai);
+
+ snd_soc_dai_init_dma_data(dai, &host->dma_params_tx, NULL);
+ snd_soc_add_dai_controls(dai, sun4i_spdif_controls,
+ ARRAY_SIZE(sun4i_spdif_controls));
+
+ return 0;
+}
+
+static const struct snd_soc_dai_ops sun4i_spdif_dai_ops = {
+ .probe = sun4i_spdif_soc_dai_probe,
+ .startup = sun4i_spdif_startup,
+ .trigger = sun4i_spdif_trigger,
+ .hw_params = sun4i_spdif_hw_params,
+};
+
+static const struct regmap_config sun4i_spdif_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = SUN4I_SPDIF_RXCHSTA1,
+};
+
+#define SUN4I_RATES SNDRV_PCM_RATE_8000_192000
+
+#define SUN4I_FORMATS (SNDRV_PCM_FORMAT_S16_LE | \
+ SNDRV_PCM_FORMAT_S20_3LE | \
+ SNDRV_PCM_FORMAT_S24_LE)
+
+static struct snd_soc_dai_driver sun4i_spdif_dai = {
+ .playback = {
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SUN4I_RATES,
+ .formats = SUN4I_FORMATS,
+ },
+ .ops = &sun4i_spdif_dai_ops,
+ .name = "spdif",
+};
+
+static const struct sun4i_spdif_quirks sun4i_a10_spdif_quirks = {
+ .reg_dac_txdata = SUN4I_SPDIF_TXFIFO,
+ .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
+};
+
+static const struct sun4i_spdif_quirks sun6i_a31_spdif_quirks = {
+ .reg_dac_txdata = SUN4I_SPDIF_TXFIFO,
+ .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
+ .has_reset = true,
+};
+
+static const struct sun4i_spdif_quirks sun8i_h3_spdif_quirks = {
+ .reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
+ .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
+ .has_reset = true,
+};
+
+static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
+ .reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
+ .val_fctl_ftx = SUN50I_H6_SPDIF_FCTL_FTX,
+ .has_reset = true,
+};
+
+static const struct of_device_id sun4i_spdif_of_match[] = {
+ {
+ .compatible = "allwinner,sun4i-a10-spdif",
+ .data = &sun4i_a10_spdif_quirks,
+ },
+ {
+ .compatible = "allwinner,sun6i-a31-spdif",
+ .data = &sun6i_a31_spdif_quirks,
+ },
+ {
+ .compatible = "allwinner,sun8i-h3-spdif",
+ .data = &sun8i_h3_spdif_quirks,
+ },
+ {
+ .compatible = "allwinner,sun50i-h6-spdif",
+ .data = &sun50i_h6_spdif_quirks,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sun4i_spdif_of_match);
+
+static const struct snd_soc_component_driver sun4i_spdif_component = {
+ .name = "sun4i-spdif",
+ .legacy_dai_naming = 1,
+};
+
+static int sun4i_spdif_runtime_suspend(struct device *dev)
+{
+ struct sun4i_spdif_dev *host = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(host->spdif_clk);
+ clk_disable_unprepare(host->apb_clk);
+
+ return 0;
+}
+
+static int sun4i_spdif_runtime_resume(struct device *dev)
+{
+ struct sun4i_spdif_dev *host = dev_get_drvdata(dev);
+ int ret;
+
+ ret = clk_prepare_enable(host->spdif_clk);
+ if (ret)
+ return ret;
+ ret = clk_prepare_enable(host->apb_clk);
+ if (ret)
+ clk_disable_unprepare(host->spdif_clk);
+
+ return ret;
+}
+
+static int sun4i_spdif_probe(struct platform_device *pdev)
+{
+ struct sun4i_spdif_dev *host;
+ struct resource *res;
+ const struct sun4i_spdif_quirks *quirks;
+ int ret;
+ void __iomem *base;
+
+ dev_dbg(&pdev->dev, "Entered %s\n", __func__);
+
+ host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
+ if (!host)
+ return -ENOMEM;
+
+ host->pdev = pdev;
+ spin_lock_init(&host->lock);
+
+ /* Initialize this copy of the CPU DAI driver structure */
+ memcpy(&host->cpu_dai_drv, &sun4i_spdif_dai, sizeof(sun4i_spdif_dai));
+ host->cpu_dai_drv.name = dev_name(&pdev->dev);
+
+ /* Get the addresses */
+ base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ quirks = of_device_get_match_data(&pdev->dev);
+ if (quirks == NULL) {
+ dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
+ return -ENODEV;
+ }
+ host->quirks = quirks;
+
+ host->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ &sun4i_spdif_regmap_config);
+
+ /* Clocks */
+ host->apb_clk = devm_clk_get(&pdev->dev, "apb");
+ if (IS_ERR(host->apb_clk)) {
+ dev_err(&pdev->dev, "failed to get a apb clock.\n");
+ return PTR_ERR(host->apb_clk);
+ }
+
+ host->spdif_clk = devm_clk_get(&pdev->dev, "spdif");
+ if (IS_ERR(host->spdif_clk)) {
+ dev_err(&pdev->dev, "failed to get a spdif clock.\n");
+ return PTR_ERR(host->spdif_clk);
+ }
+
+ host->dma_params_tx.addr = res->start + quirks->reg_dac_txdata;
+ host->dma_params_tx.maxburst = 8;
+ host->dma_params_tx.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+
+ platform_set_drvdata(pdev, host);
+
+ if (quirks->has_reset) {
+ host->rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
+ NULL);
+ if (PTR_ERR(host->rst) == -EPROBE_DEFER) {
+ ret = -EPROBE_DEFER;
+ dev_err(&pdev->dev, "Failed to get reset: %d\n", ret);
+ return ret;
+ }
+ if (!IS_ERR(host->rst))
+ reset_control_deassert(host->rst);
+ }
+
+ ret = devm_snd_soc_register_component(&pdev->dev,
+ &sun4i_spdif_component, &sun4i_spdif_dai, 1);
+ if (ret)
+ return ret;
+
+ pm_runtime_enable(&pdev->dev);
+ if (!pm_runtime_enabled(&pdev->dev)) {
+ ret = sun4i_spdif_runtime_resume(&pdev->dev);
+ if (ret)
+ goto err_unregister;
+ }
+
+ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
+ if (ret)
+ goto err_suspend;
+ return 0;
+err_suspend:
+ if (!pm_runtime_status_suspended(&pdev->dev))
+ sun4i_spdif_runtime_suspend(&pdev->dev);
+err_unregister:
+ pm_runtime_disable(&pdev->dev);
+ return ret;
+}
+
+static void sun4i_spdif_remove(struct platform_device *pdev)
+{
+ pm_runtime_disable(&pdev->dev);
+ if (!pm_runtime_status_suspended(&pdev->dev))
+ sun4i_spdif_runtime_suspend(&pdev->dev);
+}
+
+static const struct dev_pm_ops sun4i_spdif_pm = {
+ SET_RUNTIME_PM_OPS(sun4i_spdif_runtime_suspend,
+ sun4i_spdif_runtime_resume, NULL)
+};
+
+static struct platform_driver sun4i_spdif_driver = {
+ .driver = {
+ .name = "sun4i-spdif",
+ .of_match_table = sun4i_spdif_of_match,
+ .pm = &sun4i_spdif_pm,
+ },
+ .probe = sun4i_spdif_probe,
+ .remove_new = sun4i_spdif_remove,
+};
+
+module_platform_driver(sun4i_spdif_driver);
+
+MODULE_AUTHOR("Marcus Cooper <codekipper@gmail.com>");
+MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>");
+MODULE_DESCRIPTION("Allwinner sun4i SPDIF SoC Interface");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:sun4i-spdif");
diff --git a/sound/soc/sunxi/sun50i-codec-analog.c b/sound/soc/sunxi/sun50i-codec-analog.c
new file mode 100644
index 000000000..e1e5e8de0
--- /dev/null
+++ b/sound/soc/sunxi/sun50i-codec-analog.c
@@ -0,0 +1,548 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * This driver supports the analog controls for the internal codec
+ * found in Allwinner's A64 SoC.
+ *
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ * Copyright (C) 2017 Marcus Cooper <codekipper@gmail.com>
+ * Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com>
+ *
+ * Based on sun8i-codec-analog.c
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/tlv.h>
+
+#include "sun8i-adda-pr-regmap.h"
+
+/* Codec analog control register offsets and bit fields */
+#define SUN50I_ADDA_HP_CTRL 0x00
+#define SUN50I_ADDA_HP_CTRL_PA_CLK_GATE 7
+#define SUN50I_ADDA_HP_CTRL_HPPA_EN 6
+#define SUN50I_ADDA_HP_CTRL_HPVOL 0
+
+#define SUN50I_ADDA_OL_MIX_CTRL 0x01
+#define SUN50I_ADDA_OL_MIX_CTRL_MIC1 6
+#define SUN50I_ADDA_OL_MIX_CTRL_MIC2 5
+#define SUN50I_ADDA_OL_MIX_CTRL_PHONE 4
+#define SUN50I_ADDA_OL_MIX_CTRL_PHONEN 3
+#define SUN50I_ADDA_OL_MIX_CTRL_LINEINL 2
+#define SUN50I_ADDA_OL_MIX_CTRL_DACL 1
+#define SUN50I_ADDA_OL_MIX_CTRL_DACR 0
+
+#define SUN50I_ADDA_OR_MIX_CTRL 0x02
+#define SUN50I_ADDA_OR_MIX_CTRL_MIC1 6
+#define SUN50I_ADDA_OR_MIX_CTRL_MIC2 5
+#define SUN50I_ADDA_OR_MIX_CTRL_PHONE 4
+#define SUN50I_ADDA_OR_MIX_CTRL_PHONEP 3
+#define SUN50I_ADDA_OR_MIX_CTRL_LINEINR 2
+#define SUN50I_ADDA_OR_MIX_CTRL_DACR 1
+#define SUN50I_ADDA_OR_MIX_CTRL_DACL 0
+
+#define SUN50I_ADDA_EARPIECE_CTRL0 0x03
+#define SUN50I_ADDA_EARPIECE_CTRL0_EAR_RAMP_TIME 4
+#define SUN50I_ADDA_EARPIECE_CTRL0_ESPSR 0
+
+#define SUN50I_ADDA_EARPIECE_CTRL1 0x04
+#define SUN50I_ADDA_EARPIECE_CTRL1_ESPPA_EN 7
+#define SUN50I_ADDA_EARPIECE_CTRL1_ESPPA_MUTE 6
+#define SUN50I_ADDA_EARPIECE_CTRL1_ESP_VOL 0
+
+#define SUN50I_ADDA_LINEOUT_CTRL0 0x05
+#define SUN50I_ADDA_LINEOUT_CTRL0_LEN 7
+#define SUN50I_ADDA_LINEOUT_CTRL0_REN 6
+#define SUN50I_ADDA_LINEOUT_CTRL0_LSRC_SEL 5
+#define SUN50I_ADDA_LINEOUT_CTRL0_RSRC_SEL 4
+
+#define SUN50I_ADDA_LINEOUT_CTRL1 0x06
+#define SUN50I_ADDA_LINEOUT_CTRL1_VOL 0
+
+#define SUN50I_ADDA_MIC1_CTRL 0x07
+#define SUN50I_ADDA_MIC1_CTRL_MIC1G 4
+#define SUN50I_ADDA_MIC1_CTRL_MIC1AMPEN 3
+#define SUN50I_ADDA_MIC1_CTRL_MIC1BOOST 0
+
+#define SUN50I_ADDA_MIC2_CTRL 0x08
+#define SUN50I_ADDA_MIC2_CTRL_MIC2G 4
+#define SUN50I_ADDA_MIC2_CTRL_MIC2AMPEN 3
+#define SUN50I_ADDA_MIC2_CTRL_MIC2BOOST 0
+
+#define SUN50I_ADDA_LINEIN_CTRL 0x09
+#define SUN50I_ADDA_LINEIN_CTRL_LINEING 0
+
+#define SUN50I_ADDA_MIX_DAC_CTRL 0x0a
+#define SUN50I_ADDA_MIX_DAC_CTRL_DACAREN 7
+#define SUN50I_ADDA_MIX_DAC_CTRL_DACALEN 6
+#define SUN50I_ADDA_MIX_DAC_CTRL_RMIXEN 5
+#define SUN50I_ADDA_MIX_DAC_CTRL_LMIXEN 4
+#define SUN50I_ADDA_MIX_DAC_CTRL_RHPPAMUTE 3
+#define SUN50I_ADDA_MIX_DAC_CTRL_LHPPAMUTE 2
+#define SUN50I_ADDA_MIX_DAC_CTRL_RHPIS 1
+#define SUN50I_ADDA_MIX_DAC_CTRL_LHPIS 0
+
+#define SUN50I_ADDA_L_ADCMIX_SRC 0x0b
+#define SUN50I_ADDA_L_ADCMIX_SRC_MIC1 6
+#define SUN50I_ADDA_L_ADCMIX_SRC_MIC2 5
+#define SUN50I_ADDA_L_ADCMIX_SRC_PHONE 4
+#define SUN50I_ADDA_L_ADCMIX_SRC_PHONEN 3
+#define SUN50I_ADDA_L_ADCMIX_SRC_LINEINL 2
+#define SUN50I_ADDA_L_ADCMIX_SRC_OMIXRL 1
+#define SUN50I_ADDA_L_ADCMIX_SRC_OMIXRR 0
+
+#define SUN50I_ADDA_R_ADCMIX_SRC 0x0c
+#define SUN50I_ADDA_R_ADCMIX_SRC_MIC1 6
+#define SUN50I_ADDA_R_ADCMIX_SRC_MIC2 5
+#define SUN50I_ADDA_R_ADCMIX_SRC_PHONE 4
+#define SUN50I_ADDA_R_ADCMIX_SRC_PHONEP 3
+#define SUN50I_ADDA_R_ADCMIX_SRC_LINEINR 2
+#define SUN50I_ADDA_R_ADCMIX_SRC_OMIXR 1
+#define SUN50I_ADDA_R_ADCMIX_SRC_OMIXL 0
+
+#define SUN50I_ADDA_ADC_CTRL 0x0d
+#define SUN50I_ADDA_ADC_CTRL_ADCREN 7
+#define SUN50I_ADDA_ADC_CTRL_ADCLEN 6
+#define SUN50I_ADDA_ADC_CTRL_ADCG 0
+
+#define SUN50I_ADDA_HS_MBIAS_CTRL 0x0e
+#define SUN50I_ADDA_HS_MBIAS_CTRL_MMICBIASEN 7
+
+#define SUN50I_ADDA_JACK_MIC_CTRL 0x1d
+#define SUN50I_ADDA_JACK_MIC_CTRL_INNERRESEN 6
+#define SUN50I_ADDA_JACK_MIC_CTRL_HMICBIASEN 5
+
+/* mixer controls */
+static const struct snd_kcontrol_new sun50i_a64_codec_mixer_controls[] = {
+ SOC_DAPM_DOUBLE_R("Mic1 Playback Switch",
+ SUN50I_ADDA_OL_MIX_CTRL,
+ SUN50I_ADDA_OR_MIX_CTRL,
+ SUN50I_ADDA_OL_MIX_CTRL_MIC1, 1, 0),
+ SOC_DAPM_DOUBLE_R("Mic2 Playback Switch",
+ SUN50I_ADDA_OL_MIX_CTRL,
+ SUN50I_ADDA_OR_MIX_CTRL,
+ SUN50I_ADDA_OL_MIX_CTRL_MIC2, 1, 0),
+ SOC_DAPM_DOUBLE_R("Line In Playback Switch",
+ SUN50I_ADDA_OL_MIX_CTRL,
+ SUN50I_ADDA_OR_MIX_CTRL,
+ SUN50I_ADDA_OL_MIX_CTRL_LINEINL, 1, 0),
+ SOC_DAPM_DOUBLE_R("DAC Playback Switch",
+ SUN50I_ADDA_OL_MIX_CTRL,
+ SUN50I_ADDA_OR_MIX_CTRL,
+ SUN50I_ADDA_OL_MIX_CTRL_DACL, 1, 0),
+ SOC_DAPM_DOUBLE_R("DAC Reversed Playback Switch",
+ SUN50I_ADDA_OL_MIX_CTRL,
+ SUN50I_ADDA_OR_MIX_CTRL,
+ SUN50I_ADDA_OL_MIX_CTRL_DACR, 1, 0),
+};
+
+/* ADC mixer controls */
+static const struct snd_kcontrol_new sun50i_codec_adc_mixer_controls[] = {
+ SOC_DAPM_DOUBLE_R("Mic1 Capture Switch",
+ SUN50I_ADDA_L_ADCMIX_SRC,
+ SUN50I_ADDA_R_ADCMIX_SRC,
+ SUN50I_ADDA_L_ADCMIX_SRC_MIC1, 1, 0),
+ SOC_DAPM_DOUBLE_R("Mic2 Capture Switch",
+ SUN50I_ADDA_L_ADCMIX_SRC,
+ SUN50I_ADDA_R_ADCMIX_SRC,
+ SUN50I_ADDA_L_ADCMIX_SRC_MIC2, 1, 0),
+ SOC_DAPM_DOUBLE_R("Line In Capture Switch",
+ SUN50I_ADDA_L_ADCMIX_SRC,
+ SUN50I_ADDA_R_ADCMIX_SRC,
+ SUN50I_ADDA_L_ADCMIX_SRC_LINEINL, 1, 0),
+ SOC_DAPM_DOUBLE_R("Mixer Capture Switch",
+ SUN50I_ADDA_L_ADCMIX_SRC,
+ SUN50I_ADDA_R_ADCMIX_SRC,
+ SUN50I_ADDA_L_ADCMIX_SRC_OMIXRL, 1, 0),
+ SOC_DAPM_DOUBLE_R("Mixer Reversed Capture Switch",
+ SUN50I_ADDA_L_ADCMIX_SRC,
+ SUN50I_ADDA_R_ADCMIX_SRC,
+ SUN50I_ADDA_L_ADCMIX_SRC_OMIXRR, 1, 0),
+};
+
+static const DECLARE_TLV_DB_SCALE(sun50i_codec_out_mixer_pregain_scale,
+ -450, 150, 0);
+static const DECLARE_TLV_DB_RANGE(sun50i_codec_mic_gain_scale,
+ 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
+ 1, 7, TLV_DB_SCALE_ITEM(2400, 300, 0),
+);
+
+static const DECLARE_TLV_DB_SCALE(sun50i_codec_hp_vol_scale, -6300, 100, 1);
+
+static const DECLARE_TLV_DB_RANGE(sun50i_codec_lineout_vol_scale,
+ 0, 1, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
+ 2, 31, TLV_DB_SCALE_ITEM(-4350, 150, 0),
+);
+
+static const DECLARE_TLV_DB_RANGE(sun50i_codec_earpiece_vol_scale,
+ 0, 1, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
+ 2, 31, TLV_DB_SCALE_ITEM(-4350, 150, 0),
+);
+
+/* volume / mute controls */
+static const struct snd_kcontrol_new sun50i_a64_codec_controls[] = {
+ SOC_SINGLE_TLV("Headphone Playback Volume",
+ SUN50I_ADDA_HP_CTRL,
+ SUN50I_ADDA_HP_CTRL_HPVOL, 0x3f, 0,
+ sun50i_codec_hp_vol_scale),
+
+ /* Mixer pre-gain */
+ SOC_SINGLE_TLV("Mic1 Playback Volume", SUN50I_ADDA_MIC1_CTRL,
+ SUN50I_ADDA_MIC1_CTRL_MIC1G,
+ 0x7, 0, sun50i_codec_out_mixer_pregain_scale),
+
+ /* Microphone Amp boost gain */
+ SOC_SINGLE_TLV("Mic1 Boost Volume", SUN50I_ADDA_MIC1_CTRL,
+ SUN50I_ADDA_MIC1_CTRL_MIC1BOOST, 0x7, 0,
+ sun50i_codec_mic_gain_scale),
+
+ /* Mixer pre-gain */
+ SOC_SINGLE_TLV("Mic2 Playback Volume",
+ SUN50I_ADDA_MIC2_CTRL, SUN50I_ADDA_MIC2_CTRL_MIC2G,
+ 0x7, 0, sun50i_codec_out_mixer_pregain_scale),
+
+ /* Microphone Amp boost gain */
+ SOC_SINGLE_TLV("Mic2 Boost Volume", SUN50I_ADDA_MIC2_CTRL,
+ SUN50I_ADDA_MIC2_CTRL_MIC2BOOST, 0x7, 0,
+ sun50i_codec_mic_gain_scale),
+
+ /* ADC */
+ SOC_SINGLE_TLV("ADC Gain Capture Volume", SUN50I_ADDA_ADC_CTRL,
+ SUN50I_ADDA_ADC_CTRL_ADCG, 0x7, 0,
+ sun50i_codec_out_mixer_pregain_scale),
+
+ /* Mixer pre-gain */
+ SOC_SINGLE_TLV("Line In Playback Volume", SUN50I_ADDA_LINEIN_CTRL,
+ SUN50I_ADDA_LINEIN_CTRL_LINEING,
+ 0x7, 0, sun50i_codec_out_mixer_pregain_scale),
+
+ SOC_SINGLE_TLV("Line Out Playback Volume",
+ SUN50I_ADDA_LINEOUT_CTRL1,
+ SUN50I_ADDA_LINEOUT_CTRL1_VOL, 0x1f, 0,
+ sun50i_codec_lineout_vol_scale),
+
+ SOC_SINGLE_TLV("Earpiece Playback Volume",
+ SUN50I_ADDA_EARPIECE_CTRL1,
+ SUN50I_ADDA_EARPIECE_CTRL1_ESP_VOL, 0x1f, 0,
+ sun50i_codec_earpiece_vol_scale),
+};
+
+static const char * const sun50i_codec_hp_src_enum_text[] = {
+ "DAC", "Mixer",
+};
+
+static SOC_ENUM_DOUBLE_DECL(sun50i_codec_hp_src_enum,
+ SUN50I_ADDA_MIX_DAC_CTRL,
+ SUN50I_ADDA_MIX_DAC_CTRL_LHPIS,
+ SUN50I_ADDA_MIX_DAC_CTRL_RHPIS,
+ sun50i_codec_hp_src_enum_text);
+
+static const struct snd_kcontrol_new sun50i_codec_hp_src[] = {
+ SOC_DAPM_ENUM("Headphone Source Playback Route",
+ sun50i_codec_hp_src_enum),
+};
+
+static const struct snd_kcontrol_new sun50i_codec_hp_switch =
+ SOC_DAPM_DOUBLE("Headphone Playback Switch",
+ SUN50I_ADDA_MIX_DAC_CTRL,
+ SUN50I_ADDA_MIX_DAC_CTRL_LHPPAMUTE,
+ SUN50I_ADDA_MIX_DAC_CTRL_RHPPAMUTE, 1, 0);
+
+static const char * const sun50i_codec_lineout_src_enum_text[] = {
+ "Stereo", "Mono Differential",
+};
+
+static SOC_ENUM_DOUBLE_DECL(sun50i_codec_lineout_src_enum,
+ SUN50I_ADDA_LINEOUT_CTRL0,
+ SUN50I_ADDA_LINEOUT_CTRL0_LSRC_SEL,
+ SUN50I_ADDA_LINEOUT_CTRL0_RSRC_SEL,
+ sun50i_codec_lineout_src_enum_text);
+
+static const struct snd_kcontrol_new sun50i_codec_lineout_src[] = {
+ SOC_DAPM_ENUM("Line Out Source Playback Route",
+ sun50i_codec_lineout_src_enum),
+};
+
+static const struct snd_kcontrol_new sun50i_codec_lineout_switch =
+ SOC_DAPM_DOUBLE("Line Out Playback Switch",
+ SUN50I_ADDA_LINEOUT_CTRL0,
+ SUN50I_ADDA_LINEOUT_CTRL0_LEN,
+ SUN50I_ADDA_LINEOUT_CTRL0_REN, 1, 0);
+
+static const char * const sun50i_codec_earpiece_src_enum_text[] = {
+ "DACR", "DACL", "Right Mixer", "Left Mixer",
+};
+
+static SOC_ENUM_SINGLE_DECL(sun50i_codec_earpiece_src_enum,
+ SUN50I_ADDA_EARPIECE_CTRL0,
+ SUN50I_ADDA_EARPIECE_CTRL0_ESPSR,
+ sun50i_codec_earpiece_src_enum_text);
+
+static const struct snd_kcontrol_new sun50i_codec_earpiece_src[] = {
+ SOC_DAPM_ENUM("Earpiece Source Playback Route",
+ sun50i_codec_earpiece_src_enum),
+};
+
+static const struct snd_kcontrol_new sun50i_codec_earpiece_switch[] = {
+ SOC_DAPM_SINGLE("Earpiece Playback Switch",
+ SUN50I_ADDA_EARPIECE_CTRL1,
+ SUN50I_ADDA_EARPIECE_CTRL1_ESPPA_MUTE, 1, 0),
+};
+
+static const struct snd_soc_dapm_widget sun50i_a64_codec_widgets[] = {
+ /* DAC */
+ SND_SOC_DAPM_DAC("Left DAC", NULL, SUN50I_ADDA_MIX_DAC_CTRL,
+ SUN50I_ADDA_MIX_DAC_CTRL_DACALEN, 0),
+ SND_SOC_DAPM_DAC("Right DAC", NULL, SUN50I_ADDA_MIX_DAC_CTRL,
+ SUN50I_ADDA_MIX_DAC_CTRL_DACAREN, 0),
+ /* ADC */
+ SND_SOC_DAPM_ADC("Left ADC", NULL, SUN50I_ADDA_ADC_CTRL,
+ SUN50I_ADDA_ADC_CTRL_ADCLEN, 0),
+ SND_SOC_DAPM_ADC("Right ADC", NULL, SUN50I_ADDA_ADC_CTRL,
+ SUN50I_ADDA_ADC_CTRL_ADCREN, 0),
+ /*
+ * Due to this component and the codec belonging to separate DAPM
+ * contexts, we need to manually link the above widgets to their
+ * stream widgets at the card level.
+ */
+
+ SND_SOC_DAPM_REGULATOR_SUPPLY("cpvdd", 0, 0),
+ SND_SOC_DAPM_MUX("Left Headphone Source",
+ SND_SOC_NOPM, 0, 0, sun50i_codec_hp_src),
+ SND_SOC_DAPM_MUX("Right Headphone Source",
+ SND_SOC_NOPM, 0, 0, sun50i_codec_hp_src),
+ SND_SOC_DAPM_SWITCH("Left Headphone Switch",
+ SND_SOC_NOPM, 0, 0, &sun50i_codec_hp_switch),
+ SND_SOC_DAPM_SWITCH("Right Headphone Switch",
+ SND_SOC_NOPM, 0, 0, &sun50i_codec_hp_switch),
+ SND_SOC_DAPM_OUT_DRV("Left Headphone Amp",
+ SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_OUT_DRV("Right Headphone Amp",
+ SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("Headphone Amp", SUN50I_ADDA_HP_CTRL,
+ SUN50I_ADDA_HP_CTRL_HPPA_EN, 0, NULL, 0),
+ SND_SOC_DAPM_OUTPUT("HP"),
+
+ SND_SOC_DAPM_MUX("Left Line Out Source",
+ SND_SOC_NOPM, 0, 0, sun50i_codec_lineout_src),
+ SND_SOC_DAPM_MUX("Right Line Out Source",
+ SND_SOC_NOPM, 0, 0, sun50i_codec_lineout_src),
+ SND_SOC_DAPM_SWITCH("Left Line Out Switch",
+ SND_SOC_NOPM, 0, 0, &sun50i_codec_lineout_switch),
+ SND_SOC_DAPM_SWITCH("Right Line Out Switch",
+ SND_SOC_NOPM, 0, 0, &sun50i_codec_lineout_switch),
+ SND_SOC_DAPM_OUTPUT("LINEOUT"),
+
+ SND_SOC_DAPM_MUX("Earpiece Source Playback Route",
+ SND_SOC_NOPM, 0, 0, sun50i_codec_earpiece_src),
+ SOC_MIXER_NAMED_CTL_ARRAY("Earpiece Switch",
+ SND_SOC_NOPM, 0, 0,
+ sun50i_codec_earpiece_switch),
+ SND_SOC_DAPM_OUT_DRV("Earpiece Amp", SUN50I_ADDA_EARPIECE_CTRL1,
+ SUN50I_ADDA_EARPIECE_CTRL1_ESPPA_EN, 0, NULL, 0),
+ SND_SOC_DAPM_OUTPUT("EARPIECE"),
+
+ /* Microphone inputs */
+ SND_SOC_DAPM_INPUT("MIC1"),
+
+ /* Microphone Bias */
+ SND_SOC_DAPM_SUPPLY("MBIAS", SUN50I_ADDA_HS_MBIAS_CTRL,
+ SUN50I_ADDA_HS_MBIAS_CTRL_MMICBIASEN,
+ 0, NULL, 0),
+
+ /* Mic input path */
+ SND_SOC_DAPM_PGA("Mic1 Amplifier", SUN50I_ADDA_MIC1_CTRL,
+ SUN50I_ADDA_MIC1_CTRL_MIC1AMPEN, 0, NULL, 0),
+
+ /* Microphone input */
+ SND_SOC_DAPM_INPUT("MIC2"),
+
+ /* Microphone Bias */
+ SND_SOC_DAPM_SUPPLY("HBIAS", SUN50I_ADDA_JACK_MIC_CTRL,
+ SUN50I_ADDA_JACK_MIC_CTRL_HMICBIASEN,
+ 0, NULL, 0),
+
+ /* Mic input path */
+ SND_SOC_DAPM_PGA("Mic2 Amplifier", SUN50I_ADDA_MIC2_CTRL,
+ SUN50I_ADDA_MIC2_CTRL_MIC2AMPEN, 0, NULL, 0),
+
+ /* Line input */
+ SND_SOC_DAPM_INPUT("LINEIN"),
+
+ /* Mixers */
+ SND_SOC_DAPM_MIXER("Left Mixer", SUN50I_ADDA_MIX_DAC_CTRL,
+ SUN50I_ADDA_MIX_DAC_CTRL_LMIXEN, 0,
+ sun50i_a64_codec_mixer_controls,
+ ARRAY_SIZE(sun50i_a64_codec_mixer_controls)),
+ SND_SOC_DAPM_MIXER("Right Mixer", SUN50I_ADDA_MIX_DAC_CTRL,
+ SUN50I_ADDA_MIX_DAC_CTRL_RMIXEN, 0,
+ sun50i_a64_codec_mixer_controls,
+ ARRAY_SIZE(sun50i_a64_codec_mixer_controls)),
+ SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
+ sun50i_codec_adc_mixer_controls,
+ ARRAY_SIZE(sun50i_codec_adc_mixer_controls)),
+ SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
+ sun50i_codec_adc_mixer_controls,
+ ARRAY_SIZE(sun50i_codec_adc_mixer_controls)),
+};
+
+static const struct snd_soc_dapm_route sun50i_a64_codec_routes[] = {
+ /* Left Mixer Routes */
+ { "Left Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
+ { "Left Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
+ { "Left Mixer", "Line In Playback Switch", "LINEIN" },
+ { "Left Mixer", "DAC Playback Switch", "Left DAC" },
+ { "Left Mixer", "DAC Reversed Playback Switch", "Right DAC" },
+
+ /* Right Mixer Routes */
+ { "Right Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
+ { "Right Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
+ { "Right Mixer", "Line In Playback Switch", "LINEIN" },
+ { "Right Mixer", "DAC Playback Switch", "Right DAC" },
+ { "Right Mixer", "DAC Reversed Playback Switch", "Left DAC" },
+
+ /* Left ADC Mixer Routes */
+ { "Left ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
+ { "Left ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
+ { "Left ADC Mixer", "Line In Capture Switch", "LINEIN" },
+ { "Left ADC Mixer", "Mixer Capture Switch", "Left Mixer" },
+ { "Left ADC Mixer", "Mixer Reversed Capture Switch", "Right Mixer" },
+
+ /* Right ADC Mixer Routes */
+ { "Right ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
+ { "Right ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
+ { "Right ADC Mixer", "Line In Capture Switch", "LINEIN" },
+ { "Right ADC Mixer", "Mixer Capture Switch", "Right Mixer" },
+ { "Right ADC Mixer", "Mixer Reversed Capture Switch", "Left Mixer" },
+
+ /* ADC Routes */
+ { "Left ADC", NULL, "Left ADC Mixer" },
+ { "Right ADC", NULL, "Right ADC Mixer" },
+
+ /* Headphone Routes */
+ { "Left Headphone Source", "DAC", "Left DAC" },
+ { "Left Headphone Source", "Mixer", "Left Mixer" },
+ { "Left Headphone Switch", "Headphone Playback Switch", "Left Headphone Source" },
+ { "Left Headphone Amp", NULL, "Left Headphone Switch" },
+ { "Left Headphone Amp", NULL, "Headphone Amp" },
+ { "HP", NULL, "Left Headphone Amp" },
+
+ { "Right Headphone Source", "DAC", "Right DAC" },
+ { "Right Headphone Source", "Mixer", "Right Mixer" },
+ { "Right Headphone Switch", "Headphone Playback Switch", "Right Headphone Source" },
+ { "Right Headphone Amp", NULL, "Right Headphone Switch" },
+ { "Right Headphone Amp", NULL, "Headphone Amp" },
+ { "HP", NULL, "Right Headphone Amp" },
+
+ { "Headphone Amp", NULL, "cpvdd" },
+
+ /* Microphone Routes */
+ { "Mic1 Amplifier", NULL, "MIC1"},
+
+ /* Microphone Routes */
+ { "Mic2 Amplifier", NULL, "MIC2"},
+
+ /* Line-out Routes */
+ { "Left Line Out Source", "Stereo", "Left Mixer" },
+ { "Left Line Out Source", "Mono Differential", "Left Mixer" },
+ { "Left Line Out Source", "Mono Differential", "Right Mixer" },
+ { "Left Line Out Switch", "Line Out Playback Switch", "Left Line Out Source" },
+ { "LINEOUT", NULL, "Left Line Out Switch" },
+
+ { "Right Line Out Switch", "Line Out Playback Switch", "Right Mixer" },
+ { "Right Line Out Source", "Stereo", "Right Line Out Switch" },
+ { "Right Line Out Source", "Mono Differential", "Left Line Out Switch" },
+ { "LINEOUT", NULL, "Right Line Out Source" },
+
+ /* Earpiece Routes */
+ { "Earpiece Source Playback Route", "DACL", "Left DAC" },
+ { "Earpiece Source Playback Route", "DACR", "Right DAC" },
+ { "Earpiece Source Playback Route", "Left Mixer", "Left Mixer" },
+ { "Earpiece Source Playback Route", "Right Mixer", "Right Mixer" },
+ { "Earpiece Switch", "Earpiece Playback Switch", "Earpiece Source Playback Route" },
+ { "Earpiece Amp", NULL, "Earpiece Switch" },
+ { "EARPIECE", NULL, "Earpiece Amp" },
+};
+
+static int sun50i_a64_codec_suspend(struct snd_soc_component *component)
+{
+ return regmap_update_bits(component->regmap, SUN50I_ADDA_HP_CTRL,
+ BIT(SUN50I_ADDA_HP_CTRL_PA_CLK_GATE),
+ BIT(SUN50I_ADDA_HP_CTRL_PA_CLK_GATE));
+}
+
+static int sun50i_a64_codec_resume(struct snd_soc_component *component)
+{
+ return regmap_update_bits(component->regmap, SUN50I_ADDA_HP_CTRL,
+ BIT(SUN50I_ADDA_HP_CTRL_PA_CLK_GATE), 0);
+}
+
+static const struct snd_soc_component_driver sun50i_codec_analog_cmpnt_drv = {
+ .controls = sun50i_a64_codec_controls,
+ .num_controls = ARRAY_SIZE(sun50i_a64_codec_controls),
+ .dapm_widgets = sun50i_a64_codec_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(sun50i_a64_codec_widgets),
+ .dapm_routes = sun50i_a64_codec_routes,
+ .num_dapm_routes = ARRAY_SIZE(sun50i_a64_codec_routes),
+ .suspend = sun50i_a64_codec_suspend,
+ .resume = sun50i_a64_codec_resume,
+};
+
+static const struct of_device_id sun50i_codec_analog_of_match[] = {
+ {
+ .compatible = "allwinner,sun50i-a64-codec-analog",
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, sun50i_codec_analog_of_match);
+
+static int sun50i_codec_analog_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+ void __iomem *base;
+ bool enable;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base)) {
+ dev_err(&pdev->dev, "Failed to map the registers\n");
+ return PTR_ERR(base);
+ }
+
+ regmap = sun8i_adda_pr_regmap_init(&pdev->dev, base);
+ if (IS_ERR(regmap)) {
+ dev_err(&pdev->dev, "Failed to create regmap\n");
+ return PTR_ERR(regmap);
+ }
+
+ enable = device_property_read_bool(&pdev->dev,
+ "allwinner,internal-bias-resistor");
+ regmap_update_bits(regmap, SUN50I_ADDA_JACK_MIC_CTRL,
+ BIT(SUN50I_ADDA_JACK_MIC_CTRL_INNERRESEN),
+ enable << SUN50I_ADDA_JACK_MIC_CTRL_INNERRESEN);
+
+ return devm_snd_soc_register_component(&pdev->dev,
+ &sun50i_codec_analog_cmpnt_drv,
+ NULL, 0);
+}
+
+static struct platform_driver sun50i_codec_analog_driver = {
+ .driver = {
+ .name = "sun50i-codec-analog",
+ .of_match_table = sun50i_codec_analog_of_match,
+ },
+ .probe = sun50i_codec_analog_probe,
+};
+module_platform_driver(sun50i_codec_analog_driver);
+
+MODULE_DESCRIPTION("Allwinner internal codec analog controls driver for A64");
+MODULE_AUTHOR("Vasily Khoruzhick <anarsoul@gmail.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:sun50i-codec-analog");
diff --git a/sound/soc/sunxi/sun50i-dmic.c b/sound/soc/sunxi/sun50i-dmic.c
new file mode 100644
index 000000000..2599683a5
--- /dev/null
+++ b/sound/soc/sunxi/sun50i-dmic.c
@@ -0,0 +1,403 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+//
+// This driver supports the DMIC in Allwinner's H6 SoCs.
+//
+// Copyright 2021 Ban Tao <fengzheng923@gmail.com>
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/of_device.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <sound/dmaengine_pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#define SUN50I_DMIC_EN_CTL (0x00)
+ #define SUN50I_DMIC_EN_CTL_GLOBE BIT(8)
+ #define SUN50I_DMIC_EN_CTL_CHAN(v) ((v) << 0)
+ #define SUN50I_DMIC_EN_CTL_CHAN_MASK GENMASK(7, 0)
+#define SUN50I_DMIC_SR (0x04)
+ #define SUN50I_DMIC_SR_SAMPLE_RATE(v) ((v) << 0)
+ #define SUN50I_DMIC_SR_SAMPLE_RATE_MASK GENMASK(2, 0)
+#define SUN50I_DMIC_CTL (0x08)
+ #define SUN50I_DMIC_CTL_OVERSAMPLE_RATE BIT(0)
+#define SUN50I_DMIC_DATA (0x10)
+#define SUN50I_DMIC_INTC (0x14)
+ #define SUN50I_DMIC_FIFO_DRQ_EN BIT(2)
+#define SUN50I_DMIC_INT_STA (0x18)
+ #define SUN50I_DMIC_INT_STA_OVERRUN_IRQ_PENDING BIT(1)
+ #define SUN50I_DMIC_INT_STA_DATA_IRQ_PENDING BIT(0)
+#define SUN50I_DMIC_RXFIFO_CTL (0x1c)
+ #define SUN50I_DMIC_RXFIFO_CTL_FLUSH BIT(31)
+ #define SUN50I_DMIC_RXFIFO_CTL_MODE_MASK BIT(9)
+ #define SUN50I_DMIC_RXFIFO_CTL_MODE_LSB (0 << 9)
+ #define SUN50I_DMIC_RXFIFO_CTL_MODE_MSB (1 << 9)
+ #define SUN50I_DMIC_RXFIFO_CTL_SAMPLE_MASK BIT(8)
+ #define SUN50I_DMIC_RXFIFO_CTL_SAMPLE_16 (0 << 8)
+ #define SUN50I_DMIC_RXFIFO_CTL_SAMPLE_24 (1 << 8)
+#define SUN50I_DMIC_CH_NUM (0x24)
+ #define SUN50I_DMIC_CH_NUM_N(v) ((v) << 0)
+ #define SUN50I_DMIC_CH_NUM_N_MASK GENMASK(2, 0)
+#define SUN50I_DMIC_CNT (0x2c)
+ #define SUN50I_DMIC_CNT_N (1 << 0)
+#define SUN50I_DMIC_HPF_CTRL (0x38)
+#define SUN50I_DMIC_VERSION (0x50)
+
+struct sun50i_dmic_dev {
+ struct clk *dmic_clk;
+ struct clk *bus_clk;
+ struct reset_control *rst;
+ struct regmap *regmap;
+ struct snd_dmaengine_dai_dma_data dma_params_rx;
+};
+
+struct dmic_rate {
+ unsigned int samplerate;
+ unsigned int rate_bit;
+};
+
+static const struct dmic_rate dmic_rate_s[] = {
+ {48000, 0x0},
+ {44100, 0x0},
+ {32000, 0x1},
+ {24000, 0x2},
+ {22050, 0x2},
+ {16000, 0x3},
+ {12000, 0x4},
+ {11025, 0x4},
+ {8000, 0x5},
+};
+
+static int sun50i_dmic_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct sun50i_dmic_dev *host = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
+
+ /* only support capture */
+ if (substream->stream != SNDRV_PCM_STREAM_CAPTURE)
+ return -EINVAL;
+
+ regmap_update_bits(host->regmap, SUN50I_DMIC_RXFIFO_CTL,
+ SUN50I_DMIC_RXFIFO_CTL_FLUSH,
+ SUN50I_DMIC_RXFIFO_CTL_FLUSH);
+ regmap_write(host->regmap, SUN50I_DMIC_CNT, SUN50I_DMIC_CNT_N);
+
+ return 0;
+}
+
+static int sun50i_dmic_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *cpu_dai)
+{
+ int i = 0;
+ unsigned long rate = params_rate(params);
+ unsigned int mclk = 0;
+ unsigned int channels = params_channels(params);
+ unsigned int chan_en = (1 << channels) - 1;
+ struct sun50i_dmic_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
+
+ /* DMIC num is N+1 */
+ regmap_update_bits(host->regmap, SUN50I_DMIC_CH_NUM,
+ SUN50I_DMIC_CH_NUM_N_MASK,
+ SUN50I_DMIC_CH_NUM_N(channels - 1));
+ regmap_write(host->regmap, SUN50I_DMIC_HPF_CTRL, chan_en);
+ regmap_update_bits(host->regmap, SUN50I_DMIC_EN_CTL,
+ SUN50I_DMIC_EN_CTL_CHAN_MASK,
+ SUN50I_DMIC_EN_CTL_CHAN(chan_en));
+
+ switch (params_format(params)) {
+ case SNDRV_PCM_FORMAT_S16_LE:
+ regmap_update_bits(host->regmap, SUN50I_DMIC_RXFIFO_CTL,
+ SUN50I_DMIC_RXFIFO_CTL_SAMPLE_MASK,
+ SUN50I_DMIC_RXFIFO_CTL_SAMPLE_16);
+ break;
+ case SNDRV_PCM_FORMAT_S24_LE:
+ regmap_update_bits(host->regmap, SUN50I_DMIC_RXFIFO_CTL,
+ SUN50I_DMIC_RXFIFO_CTL_SAMPLE_MASK,
+ SUN50I_DMIC_RXFIFO_CTL_SAMPLE_24);
+ break;
+ default:
+ dev_err(cpu_dai->dev, "Invalid format!\n");
+ return -EINVAL;
+ }
+ /* The hardware supports FIFO mode 1 for 24-bit samples */
+ regmap_update_bits(host->regmap, SUN50I_DMIC_RXFIFO_CTL,
+ SUN50I_DMIC_RXFIFO_CTL_MODE_MASK,
+ SUN50I_DMIC_RXFIFO_CTL_MODE_MSB);
+
+ switch (rate) {
+ case 11025:
+ case 22050:
+ case 44100:
+ mclk = 22579200;
+ break;
+ case 8000:
+ case 12000:
+ case 16000:
+ case 24000:
+ case 32000:
+ case 48000:
+ mclk = 24576000;
+ break;
+ default:
+ dev_err(cpu_dai->dev, "Invalid rate!\n");
+ return -EINVAL;
+ }
+
+ if (clk_set_rate(host->dmic_clk, mclk)) {
+ dev_err(cpu_dai->dev, "mclk : %u not support\n", mclk);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(dmic_rate_s); i++) {
+ if (dmic_rate_s[i].samplerate == rate) {
+ regmap_update_bits(host->regmap, SUN50I_DMIC_SR,
+ SUN50I_DMIC_SR_SAMPLE_RATE_MASK,
+ SUN50I_DMIC_SR_SAMPLE_RATE(dmic_rate_s[i].rate_bit));
+ break;
+ }
+ }
+
+ switch (params_physical_width(params)) {
+ case 16:
+ host->dma_params_rx.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+ break;
+ case 32:
+ host->dma_params_rx.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ break;
+ default:
+ dev_err(cpu_dai->dev, "Unsupported physical sample width: %d\n",
+ params_physical_width(params));
+ return -EINVAL;
+ }
+
+ /* oversamplerate adjust */
+ if (params_rate(params) >= 24000)
+ regmap_update_bits(host->regmap, SUN50I_DMIC_CTL,
+ SUN50I_DMIC_CTL_OVERSAMPLE_RATE,
+ SUN50I_DMIC_CTL_OVERSAMPLE_RATE);
+ else
+ regmap_update_bits(host->regmap, SUN50I_DMIC_CTL,
+ SUN50I_DMIC_CTL_OVERSAMPLE_RATE, 0);
+
+ return 0;
+}
+
+static int sun50i_dmic_trigger(struct snd_pcm_substream *substream, int cmd,
+ struct snd_soc_dai *dai)
+{
+ int ret = 0;
+ struct sun50i_dmic_dev *host = snd_soc_dai_get_drvdata(dai);
+
+ if (substream->stream != SNDRV_PCM_STREAM_CAPTURE)
+ return -EINVAL;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ /* DRQ ENABLE */
+ regmap_update_bits(host->regmap, SUN50I_DMIC_INTC,
+ SUN50I_DMIC_FIFO_DRQ_EN,
+ SUN50I_DMIC_FIFO_DRQ_EN);
+ /* Global enable */
+ regmap_update_bits(host->regmap, SUN50I_DMIC_EN_CTL,
+ SUN50I_DMIC_EN_CTL_GLOBE,
+ SUN50I_DMIC_EN_CTL_GLOBE);
+ break;
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ /* DRQ DISABLE */
+ regmap_update_bits(host->regmap, SUN50I_DMIC_INTC,
+ SUN50I_DMIC_FIFO_DRQ_EN, 0);
+ /* Global disable */
+ regmap_update_bits(host->regmap, SUN50I_DMIC_EN_CTL,
+ SUN50I_DMIC_EN_CTL_GLOBE, 0);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ return ret;
+}
+
+static int sun50i_dmic_soc_dai_probe(struct snd_soc_dai *dai)
+{
+ struct sun50i_dmic_dev *host = snd_soc_dai_get_drvdata(dai);
+
+ snd_soc_dai_init_dma_data(dai, NULL, &host->dma_params_rx);
+
+ return 0;
+}
+
+static const struct snd_soc_dai_ops sun50i_dmic_dai_ops = {
+ .probe = sun50i_dmic_soc_dai_probe,
+ .startup = sun50i_dmic_startup,
+ .trigger = sun50i_dmic_trigger,
+ .hw_params = sun50i_dmic_hw_params,
+};
+
+static const struct regmap_config sun50i_dmic_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = SUN50I_DMIC_VERSION,
+ .cache_type = REGCACHE_NONE,
+};
+
+#define SUN50I_DMIC_RATES (SNDRV_PCM_RATE_8000_48000)
+#define SUN50I_DMIC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
+
+static struct snd_soc_dai_driver sun50i_dmic_dai = {
+ .capture = {
+ .channels_min = 1,
+ .channels_max = 8,
+ .rates = SUN50I_DMIC_RATES,
+ .formats = SUN50I_DMIC_FORMATS,
+ .sig_bits = 21,
+ },
+ .ops = &sun50i_dmic_dai_ops,
+ .name = "dmic",
+};
+
+static const struct of_device_id sun50i_dmic_of_match[] = {
+ {
+ .compatible = "allwinner,sun50i-h6-dmic",
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sun50i_dmic_of_match);
+
+static const struct snd_soc_component_driver sun50i_dmic_component = {
+ .name = "sun50i-dmic",
+};
+
+static int sun50i_dmic_runtime_suspend(struct device *dev)
+{
+ struct sun50i_dmic_dev *host = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(host->dmic_clk);
+ clk_disable_unprepare(host->bus_clk);
+
+ return 0;
+}
+
+static int sun50i_dmic_runtime_resume(struct device *dev)
+{
+ struct sun50i_dmic_dev *host = dev_get_drvdata(dev);
+ int ret;
+
+ ret = clk_prepare_enable(host->dmic_clk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(host->bus_clk);
+ if (ret) {
+ clk_disable_unprepare(host->dmic_clk);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int sun50i_dmic_probe(struct platform_device *pdev)
+{
+ struct sun50i_dmic_dev *host;
+ struct resource *res;
+ int ret;
+ void __iomem *base;
+
+ host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
+ if (!host)
+ return -ENOMEM;
+
+ /* Get the addresses */
+ base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(base))
+ return dev_err_probe(&pdev->dev, PTR_ERR(base),
+ "get resource failed.\n");
+
+ host->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ &sun50i_dmic_regmap_config);
+
+ /* Clocks */
+ host->bus_clk = devm_clk_get(&pdev->dev, "bus");
+ if (IS_ERR(host->bus_clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(host->bus_clk),
+ "failed to get bus clock.\n");
+
+ host->dmic_clk = devm_clk_get(&pdev->dev, "mod");
+ if (IS_ERR(host->dmic_clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(host->dmic_clk),
+ "failed to get dmic clock.\n");
+
+ host->dma_params_rx.addr = res->start + SUN50I_DMIC_DATA;
+ host->dma_params_rx.maxburst = 8;
+
+ platform_set_drvdata(pdev, host);
+
+ host->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(host->rst))
+ return dev_err_probe(&pdev->dev, PTR_ERR(host->rst),
+ "Failed to get reset.\n");
+ reset_control_deassert(host->rst);
+
+ ret = devm_snd_soc_register_component(&pdev->dev, &sun50i_dmic_component,
+ &sun50i_dmic_dai, 1);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to register component.\n");
+
+ pm_runtime_enable(&pdev->dev);
+ if (!pm_runtime_enabled(&pdev->dev)) {
+ ret = sun50i_dmic_runtime_resume(&pdev->dev);
+ if (ret)
+ goto err_disable_runtime_pm;
+ }
+
+ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
+ if (ret)
+ goto err_suspend;
+
+ return 0;
+err_suspend:
+ if (!pm_runtime_status_suspended(&pdev->dev))
+ sun50i_dmic_runtime_suspend(&pdev->dev);
+err_disable_runtime_pm:
+ pm_runtime_disable(&pdev->dev);
+ return ret;
+}
+
+static void sun50i_dmic_remove(struct platform_device *pdev)
+{
+ pm_runtime_disable(&pdev->dev);
+ if (!pm_runtime_status_suspended(&pdev->dev))
+ sun50i_dmic_runtime_suspend(&pdev->dev);
+}
+
+static const struct dev_pm_ops sun50i_dmic_pm = {
+ SET_RUNTIME_PM_OPS(sun50i_dmic_runtime_suspend,
+ sun50i_dmic_runtime_resume, NULL)
+};
+
+static struct platform_driver sun50i_dmic_driver = {
+ .driver = {
+ .name = "sun50i-dmic",
+ .of_match_table = sun50i_dmic_of_match,
+ .pm = &sun50i_dmic_pm,
+ },
+ .probe = sun50i_dmic_probe,
+ .remove_new = sun50i_dmic_remove,
+};
+
+module_platform_driver(sun50i_dmic_driver);
+
+MODULE_DESCRIPTION("Allwinner sun50i DMIC SoC Interface");
+MODULE_AUTHOR("Ban Tao <fengzheng923@gmail.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:sun50i-dmic");
diff --git a/sound/soc/sunxi/sun8i-adda-pr-regmap.c b/sound/soc/sunxi/sun8i-adda-pr-regmap.c
new file mode 100644
index 000000000..e68ce9d28
--- /dev/null
+++ b/sound/soc/sunxi/sun8i-adda-pr-regmap.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * This driver provides regmap to access to analog part of audio codec
+ * found on Allwinner A23, A31s, A33, H3 and A64 Socs
+ *
+ * Copyright 2016 Chen-Yu Tsai <wens@csie.org>
+ * Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com>
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+
+#include "sun8i-adda-pr-regmap.h"
+
+/* Analog control register access bits */
+#define ADDA_PR 0x0 /* PRCM base + 0x1c0 */
+#define ADDA_PR_RESET BIT(28)
+#define ADDA_PR_WRITE BIT(24)
+#define ADDA_PR_ADDR_SHIFT 16
+#define ADDA_PR_ADDR_MASK GENMASK(4, 0)
+#define ADDA_PR_DATA_IN_SHIFT 8
+#define ADDA_PR_DATA_IN_MASK GENMASK(7, 0)
+#define ADDA_PR_DATA_OUT_SHIFT 0
+#define ADDA_PR_DATA_OUT_MASK GENMASK(7, 0)
+
+/* regmap access bits */
+static int adda_reg_read(void *context, unsigned int reg, unsigned int *val)
+{
+ void __iomem *base = (void __iomem *)context;
+ u32 tmp;
+
+ /* De-assert reset */
+ writel(readl(base) | ADDA_PR_RESET, base);
+
+ /* Clear write bit */
+ writel(readl(base) & ~ADDA_PR_WRITE, base);
+
+ /* Set register address */
+ tmp = readl(base);
+ tmp &= ~(ADDA_PR_ADDR_MASK << ADDA_PR_ADDR_SHIFT);
+ tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT;
+ writel(tmp, base);
+
+ /* Read back value */
+ *val = readl(base) & ADDA_PR_DATA_OUT_MASK;
+
+ return 0;
+}
+
+static int adda_reg_write(void *context, unsigned int reg, unsigned int val)
+{
+ void __iomem *base = (void __iomem *)context;
+ u32 tmp;
+
+ /* De-assert reset */
+ writel(readl(base) | ADDA_PR_RESET, base);
+
+ /* Set register address */
+ tmp = readl(base);
+ tmp &= ~(ADDA_PR_ADDR_MASK << ADDA_PR_ADDR_SHIFT);
+ tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT;
+ writel(tmp, base);
+
+ /* Set data to write */
+ tmp = readl(base);
+ tmp &= ~(ADDA_PR_DATA_IN_MASK << ADDA_PR_DATA_IN_SHIFT);
+ tmp |= (val & ADDA_PR_DATA_IN_MASK) << ADDA_PR_DATA_IN_SHIFT;
+ writel(tmp, base);
+
+ /* Set write bit to signal a write */
+ writel(readl(base) | ADDA_PR_WRITE, base);
+
+ /* Clear write bit */
+ writel(readl(base) & ~ADDA_PR_WRITE, base);
+
+ return 0;
+}
+
+static const struct regmap_config adda_pr_regmap_cfg = {
+ .name = "adda-pr",
+ .reg_bits = 5,
+ .reg_stride = 1,
+ .val_bits = 8,
+ .reg_read = adda_reg_read,
+ .reg_write = adda_reg_write,
+ .fast_io = true,
+ .max_register = 31,
+};
+
+struct regmap *sun8i_adda_pr_regmap_init(struct device *dev,
+ void __iomem *base)
+{
+ return devm_regmap_init(dev, NULL, base, &adda_pr_regmap_cfg);
+}
+EXPORT_SYMBOL_GPL(sun8i_adda_pr_regmap_init);
+
+MODULE_DESCRIPTION("Allwinner analog audio codec regmap driver");
+MODULE_AUTHOR("Vasily Khoruzhick <anarsoul@gmail.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:sunxi-adda-pr");
diff --git a/sound/soc/sunxi/sun8i-adda-pr-regmap.h b/sound/soc/sunxi/sun8i-adda-pr-regmap.h
new file mode 100644
index 000000000..a5ae95dfe
--- /dev/null
+++ b/sound/soc/sunxi/sun8i-adda-pr-regmap.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com>
+ */
+
+struct regmap *sun8i_adda_pr_regmap_init(struct device *dev,
+ void __iomem *base);
diff --git a/sound/soc/sunxi/sun8i-codec-analog.c b/sound/soc/sunxi/sun8i-codec-analog.c
new file mode 100644
index 000000000..be872eefa
--- /dev/null
+++ b/sound/soc/sunxi/sun8i-codec-analog.c
@@ -0,0 +1,854 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * This driver supports the analog controls for the internal codec
+ * found in Allwinner's A31s, A23, A33 and H3 SoCs.
+ *
+ * Copyright 2016 Chen-Yu Tsai <wens@csie.org>
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/tlv.h>
+
+#include "sun8i-adda-pr-regmap.h"
+
+/* Codec analog control register offsets and bit fields */
+#define SUN8I_ADDA_HP_VOLC 0x00
+#define SUN8I_ADDA_HP_VOLC_PA_CLK_GATE 7
+#define SUN8I_ADDA_HP_VOLC_HP_VOL 0
+#define SUN8I_ADDA_LOMIXSC 0x01
+#define SUN8I_ADDA_LOMIXSC_MIC1 6
+#define SUN8I_ADDA_LOMIXSC_MIC2 5
+#define SUN8I_ADDA_LOMIXSC_PHONE 4
+#define SUN8I_ADDA_LOMIXSC_PHONEN 3
+#define SUN8I_ADDA_LOMIXSC_LINEINL 2
+#define SUN8I_ADDA_LOMIXSC_DACL 1
+#define SUN8I_ADDA_LOMIXSC_DACR 0
+#define SUN8I_ADDA_ROMIXSC 0x02
+#define SUN8I_ADDA_ROMIXSC_MIC1 6
+#define SUN8I_ADDA_ROMIXSC_MIC2 5
+#define SUN8I_ADDA_ROMIXSC_PHONE 4
+#define SUN8I_ADDA_ROMIXSC_PHONEP 3
+#define SUN8I_ADDA_ROMIXSC_LINEINR 2
+#define SUN8I_ADDA_ROMIXSC_DACR 1
+#define SUN8I_ADDA_ROMIXSC_DACL 0
+#define SUN8I_ADDA_DAC_PA_SRC 0x03
+#define SUN8I_ADDA_DAC_PA_SRC_DACAREN 7
+#define SUN8I_ADDA_DAC_PA_SRC_DACALEN 6
+#define SUN8I_ADDA_DAC_PA_SRC_RMIXEN 5
+#define SUN8I_ADDA_DAC_PA_SRC_LMIXEN 4
+#define SUN8I_ADDA_DAC_PA_SRC_RHPPAMUTE 3
+#define SUN8I_ADDA_DAC_PA_SRC_LHPPAMUTE 2
+#define SUN8I_ADDA_DAC_PA_SRC_RHPIS 1
+#define SUN8I_ADDA_DAC_PA_SRC_LHPIS 0
+#define SUN8I_ADDA_PHONEIN_GCTRL 0x04
+#define SUN8I_ADDA_PHONEIN_GCTRL_PHONEPG 4
+#define SUN8I_ADDA_PHONEIN_GCTRL_PHONENG 0
+#define SUN8I_ADDA_LINEIN_GCTRL 0x05
+#define SUN8I_ADDA_LINEIN_GCTRL_LINEING 4
+#define SUN8I_ADDA_LINEIN_GCTRL_PHONEG 0
+#define SUN8I_ADDA_MICIN_GCTRL 0x06
+#define SUN8I_ADDA_MICIN_GCTRL_MIC1G 4
+#define SUN8I_ADDA_MICIN_GCTRL_MIC2G 0
+#define SUN8I_ADDA_PAEN_HP_CTRL 0x07
+#define SUN8I_ADDA_PAEN_HP_CTRL_HPPAEN 7
+#define SUN8I_ADDA_PAEN_HP_CTRL_LINEOUTEN 7 /* H3 specific */
+#define SUN8I_ADDA_PAEN_HP_CTRL_HPCOM_FC 5
+#define SUN8I_ADDA_PAEN_HP_CTRL_COMPTEN 4
+#define SUN8I_ADDA_PAEN_HP_CTRL_PA_ANTI_POP_CTRL 2
+#define SUN8I_ADDA_PAEN_HP_CTRL_LTRNMUTE 1
+#define SUN8I_ADDA_PAEN_HP_CTRL_RTLNMUTE 0
+#define SUN8I_ADDA_PHONEOUT_CTRL 0x08
+#define SUN8I_ADDA_PHONEOUT_CTRL_PHONEOUTG 5
+#define SUN8I_ADDA_PHONEOUT_CTRL_PHONEOUTEN 4
+#define SUN8I_ADDA_PHONEOUT_CTRL_PHONEOUT_MIC1 3
+#define SUN8I_ADDA_PHONEOUT_CTRL_PHONEOUT_MIC2 2
+#define SUN8I_ADDA_PHONEOUT_CTRL_PHONEOUT_RMIX 1
+#define SUN8I_ADDA_PHONEOUT_CTRL_PHONEOUT_LMIX 0
+#define SUN8I_ADDA_PHONE_GAIN_CTRL 0x09
+#define SUN8I_ADDA_PHONE_GAIN_CTRL_LINEOUT_VOL 3
+#define SUN8I_ADDA_PHONE_GAIN_CTRL_PHONEPREG 0
+#define SUN8I_ADDA_MIC2G_CTRL 0x0a
+#define SUN8I_ADDA_MIC2G_CTRL_MIC2AMPEN 7
+#define SUN8I_ADDA_MIC2G_CTRL_MIC2BOOST 4
+#define SUN8I_ADDA_MIC2G_CTRL_LINEOUTLEN 3
+#define SUN8I_ADDA_MIC2G_CTRL_LINEOUTREN 2
+#define SUN8I_ADDA_MIC2G_CTRL_LINEOUTLSRC 1
+#define SUN8I_ADDA_MIC2G_CTRL_LINEOUTRSRC 0
+#define SUN8I_ADDA_MIC1G_MICBIAS_CTRL 0x0b
+#define SUN8I_ADDA_MIC1G_MICBIAS_CTRL_HMICBIASEN 7
+#define SUN8I_ADDA_MIC1G_MICBIAS_CTRL_MMICBIASEN 6
+#define SUN8I_ADDA_MIC1G_MICBIAS_CTRL_HMICBIAS_MODE 5
+#define SUN8I_ADDA_MIC1G_MICBIAS_CTRL_MIC1AMPEN 3
+#define SUN8I_ADDA_MIC1G_MICBIAS_CTRL_MIC1BOOST 0
+#define SUN8I_ADDA_LADCMIXSC 0x0c
+#define SUN8I_ADDA_LADCMIXSC_MIC1 6
+#define SUN8I_ADDA_LADCMIXSC_MIC2 5
+#define SUN8I_ADDA_LADCMIXSC_PHONE 4
+#define SUN8I_ADDA_LADCMIXSC_PHONEN 3
+#define SUN8I_ADDA_LADCMIXSC_LINEINL 2
+#define SUN8I_ADDA_LADCMIXSC_OMIXRL 1
+#define SUN8I_ADDA_LADCMIXSC_OMIXRR 0
+#define SUN8I_ADDA_RADCMIXSC 0x0d
+#define SUN8I_ADDA_RADCMIXSC_MIC1 6
+#define SUN8I_ADDA_RADCMIXSC_MIC2 5
+#define SUN8I_ADDA_RADCMIXSC_PHONE 4
+#define SUN8I_ADDA_RADCMIXSC_PHONEP 3
+#define SUN8I_ADDA_RADCMIXSC_LINEINR 2
+#define SUN8I_ADDA_RADCMIXSC_OMIXR 1
+#define SUN8I_ADDA_RADCMIXSC_OMIXL 0
+#define SUN8I_ADDA_RES 0x0e
+#define SUN8I_ADDA_RES_MMICBIAS_SEL 4
+#define SUN8I_ADDA_RES_PA_ANTI_POP_CTRL 0
+#define SUN8I_ADDA_ADC_AP_EN 0x0f
+#define SUN8I_ADDA_ADC_AP_EN_ADCREN 7
+#define SUN8I_ADDA_ADC_AP_EN_ADCLEN 6
+#define SUN8I_ADDA_ADC_AP_EN_ADCG 0
+
+/* mixer controls */
+static const struct snd_kcontrol_new sun8i_codec_mixer_controls[] = {
+ SOC_DAPM_DOUBLE_R("DAC Playback Switch",
+ SUN8I_ADDA_LOMIXSC,
+ SUN8I_ADDA_ROMIXSC,
+ SUN8I_ADDA_LOMIXSC_DACL, 1, 0),
+ SOC_DAPM_DOUBLE_R("DAC Reversed Playback Switch",
+ SUN8I_ADDA_LOMIXSC,
+ SUN8I_ADDA_ROMIXSC,
+ SUN8I_ADDA_LOMIXSC_DACR, 1, 0),
+ SOC_DAPM_DOUBLE_R("Line In Playback Switch",
+ SUN8I_ADDA_LOMIXSC,
+ SUN8I_ADDA_ROMIXSC,
+ SUN8I_ADDA_LOMIXSC_LINEINL, 1, 0),
+ SOC_DAPM_DOUBLE_R("Mic1 Playback Switch",
+ SUN8I_ADDA_LOMIXSC,
+ SUN8I_ADDA_ROMIXSC,
+ SUN8I_ADDA_LOMIXSC_MIC1, 1, 0),
+ SOC_DAPM_DOUBLE_R("Mic2 Playback Switch",
+ SUN8I_ADDA_LOMIXSC,
+ SUN8I_ADDA_ROMIXSC,
+ SUN8I_ADDA_LOMIXSC_MIC2, 1, 0),
+};
+
+/* mixer controls */
+static const struct snd_kcontrol_new sun8i_v3s_codec_mixer_controls[] = {
+ SOC_DAPM_DOUBLE_R("DAC Playback Switch",
+ SUN8I_ADDA_LOMIXSC,
+ SUN8I_ADDA_ROMIXSC,
+ SUN8I_ADDA_LOMIXSC_DACL, 1, 0),
+ SOC_DAPM_DOUBLE_R("DAC Reversed Playback Switch",
+ SUN8I_ADDA_LOMIXSC,
+ SUN8I_ADDA_ROMIXSC,
+ SUN8I_ADDA_LOMIXSC_DACR, 1, 0),
+ SOC_DAPM_DOUBLE_R("Mic1 Playback Switch",
+ SUN8I_ADDA_LOMIXSC,
+ SUN8I_ADDA_ROMIXSC,
+ SUN8I_ADDA_LOMIXSC_MIC1, 1, 0),
+};
+
+/* ADC mixer controls */
+static const struct snd_kcontrol_new sun8i_codec_adc_mixer_controls[] = {
+ SOC_DAPM_DOUBLE_R("Mixer Capture Switch",
+ SUN8I_ADDA_LADCMIXSC,
+ SUN8I_ADDA_RADCMIXSC,
+ SUN8I_ADDA_LADCMIXSC_OMIXRL, 1, 0),
+ SOC_DAPM_DOUBLE_R("Mixer Reversed Capture Switch",
+ SUN8I_ADDA_LADCMIXSC,
+ SUN8I_ADDA_RADCMIXSC,
+ SUN8I_ADDA_LADCMIXSC_OMIXRR, 1, 0),
+ SOC_DAPM_DOUBLE_R("Line In Capture Switch",
+ SUN8I_ADDA_LADCMIXSC,
+ SUN8I_ADDA_RADCMIXSC,
+ SUN8I_ADDA_LADCMIXSC_LINEINL, 1, 0),
+ SOC_DAPM_DOUBLE_R("Mic1 Capture Switch",
+ SUN8I_ADDA_LADCMIXSC,
+ SUN8I_ADDA_RADCMIXSC,
+ SUN8I_ADDA_LADCMIXSC_MIC1, 1, 0),
+ SOC_DAPM_DOUBLE_R("Mic2 Capture Switch",
+ SUN8I_ADDA_LADCMIXSC,
+ SUN8I_ADDA_RADCMIXSC,
+ SUN8I_ADDA_LADCMIXSC_MIC2, 1, 0),
+};
+
+/* ADC mixer controls */
+static const struct snd_kcontrol_new sun8i_v3s_codec_adc_mixer_controls[] = {
+ SOC_DAPM_DOUBLE_R("Mixer Capture Switch",
+ SUN8I_ADDA_LADCMIXSC,
+ SUN8I_ADDA_RADCMIXSC,
+ SUN8I_ADDA_LADCMIXSC_OMIXRL, 1, 0),
+ SOC_DAPM_DOUBLE_R("Mixer Reversed Capture Switch",
+ SUN8I_ADDA_LADCMIXSC,
+ SUN8I_ADDA_RADCMIXSC,
+ SUN8I_ADDA_LADCMIXSC_OMIXRR, 1, 0),
+ SOC_DAPM_DOUBLE_R("Mic1 Capture Switch",
+ SUN8I_ADDA_LADCMIXSC,
+ SUN8I_ADDA_RADCMIXSC,
+ SUN8I_ADDA_LADCMIXSC_MIC1, 1, 0),
+};
+
+/* volume / mute controls */
+static const DECLARE_TLV_DB_SCALE(sun8i_codec_out_mixer_pregain_scale,
+ -450, 150, 0);
+static const DECLARE_TLV_DB_RANGE(sun8i_codec_mic_gain_scale,
+ 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
+ 1, 7, TLV_DB_SCALE_ITEM(2400, 300, 0),
+);
+
+static const struct snd_kcontrol_new sun8i_codec_common_controls[] = {
+ /* Mixer pre-gain */
+ SOC_SINGLE_TLV("Mic1 Playback Volume", SUN8I_ADDA_MICIN_GCTRL,
+ SUN8I_ADDA_MICIN_GCTRL_MIC1G,
+ 0x7, 0, sun8i_codec_out_mixer_pregain_scale),
+
+ /* Microphone Amp boost gain */
+ SOC_SINGLE_TLV("Mic1 Boost Volume", SUN8I_ADDA_MIC1G_MICBIAS_CTRL,
+ SUN8I_ADDA_MIC1G_MICBIAS_CTRL_MIC1BOOST, 0x7, 0,
+ sun8i_codec_mic_gain_scale),
+
+ /* ADC */
+ SOC_SINGLE_TLV("ADC Gain Capture Volume", SUN8I_ADDA_ADC_AP_EN,
+ SUN8I_ADDA_ADC_AP_EN_ADCG, 0x7, 0,
+ sun8i_codec_out_mixer_pregain_scale),
+};
+
+static const struct snd_soc_dapm_widget sun8i_codec_common_widgets[] = {
+ /* ADC */
+ SND_SOC_DAPM_ADC("Left ADC", NULL, SUN8I_ADDA_ADC_AP_EN,
+ SUN8I_ADDA_ADC_AP_EN_ADCLEN, 0),
+ SND_SOC_DAPM_ADC("Right ADC", NULL, SUN8I_ADDA_ADC_AP_EN,
+ SUN8I_ADDA_ADC_AP_EN_ADCREN, 0),
+
+ /* DAC */
+ SND_SOC_DAPM_DAC("Left DAC", NULL, SUN8I_ADDA_DAC_PA_SRC,
+ SUN8I_ADDA_DAC_PA_SRC_DACALEN, 0),
+ SND_SOC_DAPM_DAC("Right DAC", NULL, SUN8I_ADDA_DAC_PA_SRC,
+ SUN8I_ADDA_DAC_PA_SRC_DACAREN, 0),
+ /*
+ * Due to this component and the codec belonging to separate DAPM
+ * contexts, we need to manually link the above widgets to their
+ * stream widgets at the card level.
+ */
+
+ /* Microphone input */
+ SND_SOC_DAPM_INPUT("MIC1"),
+
+ /* Mic input path */
+ SND_SOC_DAPM_PGA("Mic1 Amplifier", SUN8I_ADDA_MIC1G_MICBIAS_CTRL,
+ SUN8I_ADDA_MIC1G_MICBIAS_CTRL_MIC1AMPEN, 0, NULL, 0),
+};
+
+static const struct snd_soc_dapm_widget sun8i_codec_mixer_widgets[] = {
+ SND_SOC_DAPM_MIXER("Left Mixer", SUN8I_ADDA_DAC_PA_SRC,
+ SUN8I_ADDA_DAC_PA_SRC_LMIXEN, 0,
+ sun8i_codec_mixer_controls,
+ ARRAY_SIZE(sun8i_codec_mixer_controls)),
+ SND_SOC_DAPM_MIXER("Right Mixer", SUN8I_ADDA_DAC_PA_SRC,
+ SUN8I_ADDA_DAC_PA_SRC_RMIXEN, 0,
+ sun8i_codec_mixer_controls,
+ ARRAY_SIZE(sun8i_codec_mixer_controls)),
+ SND_SOC_DAPM_MIXER("Left ADC Mixer", SUN8I_ADDA_ADC_AP_EN,
+ SUN8I_ADDA_ADC_AP_EN_ADCLEN, 0,
+ sun8i_codec_adc_mixer_controls,
+ ARRAY_SIZE(sun8i_codec_adc_mixer_controls)),
+ SND_SOC_DAPM_MIXER("Right ADC Mixer", SUN8I_ADDA_ADC_AP_EN,
+ SUN8I_ADDA_ADC_AP_EN_ADCREN, 0,
+ sun8i_codec_adc_mixer_controls,
+ ARRAY_SIZE(sun8i_codec_adc_mixer_controls)),
+};
+
+static const struct snd_soc_dapm_widget sun8i_v3s_codec_mixer_widgets[] = {
+ SND_SOC_DAPM_MIXER("Left Mixer", SUN8I_ADDA_DAC_PA_SRC,
+ SUN8I_ADDA_DAC_PA_SRC_LMIXEN, 0,
+ sun8i_v3s_codec_mixer_controls,
+ ARRAY_SIZE(sun8i_v3s_codec_mixer_controls)),
+ SND_SOC_DAPM_MIXER("Right Mixer", SUN8I_ADDA_DAC_PA_SRC,
+ SUN8I_ADDA_DAC_PA_SRC_RMIXEN, 0,
+ sun8i_v3s_codec_mixer_controls,
+ ARRAY_SIZE(sun8i_v3s_codec_mixer_controls)),
+ SND_SOC_DAPM_MIXER("Left ADC Mixer", SUN8I_ADDA_ADC_AP_EN,
+ SUN8I_ADDA_ADC_AP_EN_ADCLEN, 0,
+ sun8i_v3s_codec_adc_mixer_controls,
+ ARRAY_SIZE(sun8i_v3s_codec_adc_mixer_controls)),
+ SND_SOC_DAPM_MIXER("Right ADC Mixer", SUN8I_ADDA_ADC_AP_EN,
+ SUN8I_ADDA_ADC_AP_EN_ADCREN, 0,
+ sun8i_v3s_codec_adc_mixer_controls,
+ ARRAY_SIZE(sun8i_v3s_codec_adc_mixer_controls)),
+};
+
+static const struct snd_soc_dapm_route sun8i_codec_common_routes[] = {
+ /* Microphone Routes */
+ { "Mic1 Amplifier", NULL, "MIC1"},
+};
+
+static const struct snd_soc_dapm_route sun8i_codec_mixer_routes[] = {
+ /* Left Mixer Routes */
+ { "Left Mixer", "DAC Playback Switch", "Left DAC" },
+ { "Left Mixer", "DAC Reversed Playback Switch", "Right DAC" },
+ { "Left Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
+
+ /* Right Mixer Routes */
+ { "Right Mixer", "DAC Playback Switch", "Right DAC" },
+ { "Right Mixer", "DAC Reversed Playback Switch", "Left DAC" },
+ { "Right Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
+
+ /* Left ADC Mixer Routes */
+ { "Left ADC Mixer", "Mixer Capture Switch", "Left Mixer" },
+ { "Left ADC Mixer", "Mixer Reversed Capture Switch", "Right Mixer" },
+ { "Left ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
+
+ /* Right ADC Mixer Routes */
+ { "Right ADC Mixer", "Mixer Capture Switch", "Right Mixer" },
+ { "Right ADC Mixer", "Mixer Reversed Capture Switch", "Left Mixer" },
+ { "Right ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
+
+ /* ADC Routes */
+ { "Left ADC", NULL, "Left ADC Mixer" },
+ { "Right ADC", NULL, "Right ADC Mixer" },
+};
+
+/* headphone specific controls, widgets, and routes */
+static const DECLARE_TLV_DB_SCALE(sun8i_codec_hp_vol_scale, -6300, 100, 1);
+static const struct snd_kcontrol_new sun8i_codec_headphone_controls[] = {
+ SOC_SINGLE_TLV("Headphone Playback Volume",
+ SUN8I_ADDA_HP_VOLC,
+ SUN8I_ADDA_HP_VOLC_HP_VOL, 0x3f, 0,
+ sun8i_codec_hp_vol_scale),
+ SOC_DOUBLE("Headphone Playback Switch",
+ SUN8I_ADDA_DAC_PA_SRC,
+ SUN8I_ADDA_DAC_PA_SRC_LHPPAMUTE,
+ SUN8I_ADDA_DAC_PA_SRC_RHPPAMUTE, 1, 0),
+};
+
+static const char * const sun8i_codec_hp_src_enum_text[] = {
+ "DAC", "Mixer",
+};
+
+static SOC_ENUM_DOUBLE_DECL(sun8i_codec_hp_src_enum,
+ SUN8I_ADDA_DAC_PA_SRC,
+ SUN8I_ADDA_DAC_PA_SRC_LHPIS,
+ SUN8I_ADDA_DAC_PA_SRC_RHPIS,
+ sun8i_codec_hp_src_enum_text);
+
+static const struct snd_kcontrol_new sun8i_codec_hp_src[] = {
+ SOC_DAPM_ENUM("Headphone Source Playback Route",
+ sun8i_codec_hp_src_enum),
+};
+
+static int sun8i_headphone_amp_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *k, int event)
+{
+ struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
+
+ if (SND_SOC_DAPM_EVENT_ON(event)) {
+ snd_soc_component_update_bits(component, SUN8I_ADDA_PAEN_HP_CTRL,
+ BIT(SUN8I_ADDA_PAEN_HP_CTRL_HPPAEN),
+ BIT(SUN8I_ADDA_PAEN_HP_CTRL_HPPAEN));
+ /*
+ * Need a delay to have the amplifier up. 700ms seems the best
+ * compromise between the time to let the amplifier up and the
+ * time not to feel this delay while playing a sound.
+ */
+ msleep(700);
+ } else if (SND_SOC_DAPM_EVENT_OFF(event)) {
+ snd_soc_component_update_bits(component, SUN8I_ADDA_PAEN_HP_CTRL,
+ BIT(SUN8I_ADDA_PAEN_HP_CTRL_HPPAEN),
+ 0x0);
+ }
+
+ return 0;
+}
+
+static const struct snd_soc_dapm_widget sun8i_codec_headphone_widgets[] = {
+ SND_SOC_DAPM_MUX("Headphone Source Playback Route",
+ SND_SOC_NOPM, 0, 0, sun8i_codec_hp_src),
+ SND_SOC_DAPM_OUT_DRV_E("Headphone Amp", SUN8I_ADDA_PAEN_HP_CTRL,
+ SUN8I_ADDA_PAEN_HP_CTRL_HPPAEN, 0, NULL, 0,
+ sun8i_headphone_amp_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
+ SND_SOC_DAPM_SUPPLY("HPCOM Protection", SUN8I_ADDA_PAEN_HP_CTRL,
+ SUN8I_ADDA_PAEN_HP_CTRL_COMPTEN, 0, NULL, 0),
+ SND_SOC_DAPM_REG(snd_soc_dapm_supply, "HPCOM", SUN8I_ADDA_PAEN_HP_CTRL,
+ SUN8I_ADDA_PAEN_HP_CTRL_HPCOM_FC, 0x3, 0x3, 0),
+ SND_SOC_DAPM_OUTPUT("HP"),
+};
+
+static const struct snd_soc_dapm_route sun8i_codec_headphone_routes[] = {
+ { "Headphone Source Playback Route", "DAC", "Left DAC" },
+ { "Headphone Source Playback Route", "DAC", "Right DAC" },
+ { "Headphone Source Playback Route", "Mixer", "Left Mixer" },
+ { "Headphone Source Playback Route", "Mixer", "Right Mixer" },
+ { "Headphone Amp", NULL, "Headphone Source Playback Route" },
+ { "HPCOM", NULL, "HPCOM Protection" },
+ { "HP", NULL, "Headphone Amp" },
+};
+
+static int sun8i_codec_add_headphone(struct snd_soc_component *cmpnt)
+{
+ struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(cmpnt);
+ struct device *dev = cmpnt->dev;
+ int ret;
+
+ ret = snd_soc_add_component_controls(cmpnt,
+ sun8i_codec_headphone_controls,
+ ARRAY_SIZE(sun8i_codec_headphone_controls));
+ if (ret) {
+ dev_err(dev, "Failed to add Headphone controls: %d\n", ret);
+ return ret;
+ }
+
+ ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_headphone_widgets,
+ ARRAY_SIZE(sun8i_codec_headphone_widgets));
+ if (ret) {
+ dev_err(dev, "Failed to add Headphone DAPM widgets: %d\n", ret);
+ return ret;
+ }
+
+ ret = snd_soc_dapm_add_routes(dapm, sun8i_codec_headphone_routes,
+ ARRAY_SIZE(sun8i_codec_headphone_routes));
+ if (ret) {
+ dev_err(dev, "Failed to add Headphone DAPM routes: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+/* mbias specific widget */
+static const struct snd_soc_dapm_widget sun8i_codec_mbias_widgets[] = {
+ SND_SOC_DAPM_SUPPLY("MBIAS", SUN8I_ADDA_MIC1G_MICBIAS_CTRL,
+ SUN8I_ADDA_MIC1G_MICBIAS_CTRL_MMICBIASEN,
+ 0, NULL, 0),
+};
+
+static int sun8i_codec_add_mbias(struct snd_soc_component *cmpnt)
+{
+ struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(cmpnt);
+ struct device *dev = cmpnt->dev;
+ int ret;
+
+ ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_mbias_widgets,
+ ARRAY_SIZE(sun8i_codec_mbias_widgets));
+ if (ret)
+ dev_err(dev, "Failed to add MBIAS DAPM widgets: %d\n", ret);
+
+ return ret;
+}
+
+/* hmic specific widget */
+static const struct snd_soc_dapm_widget sun8i_codec_hmic_widgets[] = {
+ SND_SOC_DAPM_SUPPLY("HBIAS", SUN8I_ADDA_MIC1G_MICBIAS_CTRL,
+ SUN8I_ADDA_MIC1G_MICBIAS_CTRL_HMICBIASEN,
+ 0, NULL, 0),
+};
+
+static int sun8i_codec_add_hmic(struct snd_soc_component *cmpnt)
+{
+ struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(cmpnt);
+ struct device *dev = cmpnt->dev;
+ int ret;
+
+ ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_hmic_widgets,
+ ARRAY_SIZE(sun8i_codec_hmic_widgets));
+ if (ret)
+ dev_err(dev, "Failed to add Mic3 DAPM widgets: %d\n", ret);
+
+ return ret;
+}
+
+/* line in specific controls, widgets and rines */
+static const struct snd_kcontrol_new sun8i_codec_linein_controls[] = {
+ /* Mixer pre-gain */
+ SOC_SINGLE_TLV("Line In Playback Volume", SUN8I_ADDA_LINEIN_GCTRL,
+ SUN8I_ADDA_LINEIN_GCTRL_LINEING,
+ 0x7, 0, sun8i_codec_out_mixer_pregain_scale),
+};
+
+static const struct snd_soc_dapm_widget sun8i_codec_linein_widgets[] = {
+ /* Line input */
+ SND_SOC_DAPM_INPUT("LINEIN"),
+};
+
+static const struct snd_soc_dapm_route sun8i_codec_linein_routes[] = {
+ { "Left Mixer", "Line In Playback Switch", "LINEIN" },
+
+ { "Right Mixer", "Line In Playback Switch", "LINEIN" },
+
+ { "Left ADC Mixer", "Line In Capture Switch", "LINEIN" },
+
+ { "Right ADC Mixer", "Line In Capture Switch", "LINEIN" },
+};
+
+static int sun8i_codec_add_linein(struct snd_soc_component *cmpnt)
+{
+ struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(cmpnt);
+ struct device *dev = cmpnt->dev;
+ int ret;
+
+ ret = snd_soc_add_component_controls(cmpnt,
+ sun8i_codec_linein_controls,
+ ARRAY_SIZE(sun8i_codec_linein_controls));
+ if (ret) {
+ dev_err(dev, "Failed to add Line In controls: %d\n", ret);
+ return ret;
+ }
+
+ ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_linein_widgets,
+ ARRAY_SIZE(sun8i_codec_linein_widgets));
+ if (ret) {
+ dev_err(dev, "Failed to add Line In DAPM widgets: %d\n", ret);
+ return ret;
+ }
+
+ ret = snd_soc_dapm_add_routes(dapm, sun8i_codec_linein_routes,
+ ARRAY_SIZE(sun8i_codec_linein_routes));
+ if (ret) {
+ dev_err(dev, "Failed to add Line In DAPM routes: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+
+/* line out specific controls, widgets and routes */
+static const DECLARE_TLV_DB_RANGE(sun8i_codec_lineout_vol_scale,
+ 0, 1, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
+ 2, 31, TLV_DB_SCALE_ITEM(-4350, 150, 0),
+);
+static const struct snd_kcontrol_new sun8i_codec_lineout_controls[] = {
+ SOC_SINGLE_TLV("Line Out Playback Volume",
+ SUN8I_ADDA_PHONE_GAIN_CTRL,
+ SUN8I_ADDA_PHONE_GAIN_CTRL_LINEOUT_VOL, 0x1f, 0,
+ sun8i_codec_lineout_vol_scale),
+ SOC_DOUBLE("Line Out Playback Switch",
+ SUN8I_ADDA_MIC2G_CTRL,
+ SUN8I_ADDA_MIC2G_CTRL_LINEOUTLEN,
+ SUN8I_ADDA_MIC2G_CTRL_LINEOUTREN, 1, 0),
+};
+
+static const char * const sun8i_codec_lineout_src_enum_text[] = {
+ "Stereo", "Mono Differential",
+};
+
+static SOC_ENUM_DOUBLE_DECL(sun8i_codec_lineout_src_enum,
+ SUN8I_ADDA_MIC2G_CTRL,
+ SUN8I_ADDA_MIC2G_CTRL_LINEOUTLSRC,
+ SUN8I_ADDA_MIC2G_CTRL_LINEOUTRSRC,
+ sun8i_codec_lineout_src_enum_text);
+
+static const struct snd_kcontrol_new sun8i_codec_lineout_src[] = {
+ SOC_DAPM_ENUM("Line Out Source Playback Route",
+ sun8i_codec_lineout_src_enum),
+};
+
+static const struct snd_soc_dapm_widget sun8i_codec_lineout_widgets[] = {
+ SND_SOC_DAPM_MUX("Line Out Source Playback Route",
+ SND_SOC_NOPM, 0, 0, sun8i_codec_lineout_src),
+ /* It is unclear if this is a buffer or gate, model it as a supply */
+ SND_SOC_DAPM_SUPPLY("Line Out Enable", SUN8I_ADDA_PAEN_HP_CTRL,
+ SUN8I_ADDA_PAEN_HP_CTRL_LINEOUTEN, 0, NULL, 0),
+ SND_SOC_DAPM_OUTPUT("LINEOUT"),
+};
+
+static const struct snd_soc_dapm_route sun8i_codec_lineout_routes[] = {
+ { "Line Out Source Playback Route", "Stereo", "Left Mixer" },
+ { "Line Out Source Playback Route", "Stereo", "Right Mixer" },
+ { "Line Out Source Playback Route", "Mono Differential", "Left Mixer" },
+ { "Line Out Source Playback Route", "Mono Differential", "Right Mixer" },
+ { "LINEOUT", NULL, "Line Out Source Playback Route" },
+ { "LINEOUT", NULL, "Line Out Enable", },
+};
+
+static int sun8i_codec_add_lineout(struct snd_soc_component *cmpnt)
+{
+ struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(cmpnt);
+ struct device *dev = cmpnt->dev;
+ int ret;
+
+ ret = snd_soc_add_component_controls(cmpnt,
+ sun8i_codec_lineout_controls,
+ ARRAY_SIZE(sun8i_codec_lineout_controls));
+ if (ret) {
+ dev_err(dev, "Failed to add Line Out controls: %d\n", ret);
+ return ret;
+ }
+
+ ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_lineout_widgets,
+ ARRAY_SIZE(sun8i_codec_lineout_widgets));
+ if (ret) {
+ dev_err(dev, "Failed to add Line Out DAPM widgets: %d\n", ret);
+ return ret;
+ }
+
+ ret = snd_soc_dapm_add_routes(dapm, sun8i_codec_lineout_routes,
+ ARRAY_SIZE(sun8i_codec_lineout_routes));
+ if (ret) {
+ dev_err(dev, "Failed to add Line Out DAPM routes: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+/* mic2 specific controls, widgets and routes */
+static const struct snd_kcontrol_new sun8i_codec_mic2_controls[] = {
+ /* Mixer pre-gain */
+ SOC_SINGLE_TLV("Mic2 Playback Volume",
+ SUN8I_ADDA_MICIN_GCTRL, SUN8I_ADDA_MICIN_GCTRL_MIC2G,
+ 0x7, 0, sun8i_codec_out_mixer_pregain_scale),
+
+ /* Microphone Amp boost gain */
+ SOC_SINGLE_TLV("Mic2 Boost Volume", SUN8I_ADDA_MIC2G_CTRL,
+ SUN8I_ADDA_MIC2G_CTRL_MIC2BOOST, 0x7, 0,
+ sun8i_codec_mic_gain_scale),
+};
+
+static const struct snd_soc_dapm_widget sun8i_codec_mic2_widgets[] = {
+ /* Microphone input */
+ SND_SOC_DAPM_INPUT("MIC2"),
+
+ /* Mic input path */
+ SND_SOC_DAPM_PGA("Mic2 Amplifier", SUN8I_ADDA_MIC2G_CTRL,
+ SUN8I_ADDA_MIC2G_CTRL_MIC2AMPEN, 0, NULL, 0),
+};
+
+static const struct snd_soc_dapm_route sun8i_codec_mic2_routes[] = {
+ { "Mic2 Amplifier", NULL, "MIC2"},
+
+ { "Left Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
+
+ { "Right Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
+
+ { "Left ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
+
+ { "Right ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
+};
+
+static int sun8i_codec_add_mic2(struct snd_soc_component *cmpnt)
+{
+ struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(cmpnt);
+ struct device *dev = cmpnt->dev;
+ int ret;
+
+ ret = snd_soc_add_component_controls(cmpnt,
+ sun8i_codec_mic2_controls,
+ ARRAY_SIZE(sun8i_codec_mic2_controls));
+ if (ret) {
+ dev_err(dev, "Failed to add MIC2 controls: %d\n", ret);
+ return ret;
+ }
+
+ ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_mic2_widgets,
+ ARRAY_SIZE(sun8i_codec_mic2_widgets));
+ if (ret) {
+ dev_err(dev, "Failed to add MIC2 DAPM widgets: %d\n", ret);
+ return ret;
+ }
+
+ ret = snd_soc_dapm_add_routes(dapm, sun8i_codec_mic2_routes,
+ ARRAY_SIZE(sun8i_codec_mic2_routes));
+ if (ret) {
+ dev_err(dev, "Failed to add MIC2 DAPM routes: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+struct sun8i_codec_analog_quirks {
+ bool has_headphone;
+ bool has_hmic;
+ bool has_linein;
+ bool has_lineout;
+ bool has_mbias;
+ bool has_mic2;
+};
+
+static const struct sun8i_codec_analog_quirks sun8i_a23_quirks = {
+ .has_headphone = true,
+ .has_hmic = true,
+ .has_linein = true,
+ .has_mbias = true,
+ .has_mic2 = true,
+};
+
+static const struct sun8i_codec_analog_quirks sun8i_h3_quirks = {
+ .has_linein = true,
+ .has_lineout = true,
+ .has_mbias = true,
+ .has_mic2 = true,
+};
+
+static int sun8i_codec_analog_add_mixer(struct snd_soc_component *cmpnt,
+ const struct sun8i_codec_analog_quirks *quirks)
+{
+ struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(cmpnt);
+ struct device *dev = cmpnt->dev;
+ int ret;
+
+ if (!quirks->has_mic2 && !quirks->has_linein) {
+ /*
+ * Apply the special widget set which has uses a control
+ * without MIC2 and Line In, for SoCs without these.
+ * TODO: not all special cases are supported now, this case
+ * is present because it's the case of V3s.
+ */
+ ret = snd_soc_dapm_new_controls(dapm,
+ sun8i_v3s_codec_mixer_widgets,
+ ARRAY_SIZE(sun8i_v3s_codec_mixer_widgets));
+ if (ret) {
+ dev_err(dev, "Failed to add V3s Mixer DAPM widgets: %d\n", ret);
+ return ret;
+ }
+ } else {
+ /* Apply the generic mixer widget set. */
+ ret = snd_soc_dapm_new_controls(dapm,
+ sun8i_codec_mixer_widgets,
+ ARRAY_SIZE(sun8i_codec_mixer_widgets));
+ if (ret) {
+ dev_err(dev, "Failed to add Mixer DAPM widgets: %d\n", ret);
+ return ret;
+ }
+ }
+
+ ret = snd_soc_dapm_add_routes(dapm, sun8i_codec_mixer_routes,
+ ARRAY_SIZE(sun8i_codec_mixer_routes));
+ if (ret) {
+ dev_err(dev, "Failed to add Mixer DAPM routes: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct sun8i_codec_analog_quirks sun8i_v3s_quirks = {
+ .has_headphone = true,
+ .has_hmic = true,
+};
+
+static int sun8i_codec_analog_cmpnt_probe(struct snd_soc_component *cmpnt)
+{
+ struct device *dev = cmpnt->dev;
+ const struct sun8i_codec_analog_quirks *quirks;
+ int ret;
+
+ /*
+ * This would never return NULL unless someone directly registers a
+ * platform device matching this driver's name, without specifying a
+ * device tree node.
+ */
+ quirks = of_device_get_match_data(dev);
+
+ /* Add controls, widgets, and routes for individual features */
+ ret = sun8i_codec_analog_add_mixer(cmpnt, quirks);
+ if (ret)
+ return ret;
+
+ if (quirks->has_headphone) {
+ ret = sun8i_codec_add_headphone(cmpnt);
+ if (ret)
+ return ret;
+ }
+
+ if (quirks->has_hmic) {
+ ret = sun8i_codec_add_hmic(cmpnt);
+ if (ret)
+ return ret;
+ }
+
+ if (quirks->has_linein) {
+ ret = sun8i_codec_add_linein(cmpnt);
+ if (ret)
+ return ret;
+ }
+
+ if (quirks->has_lineout) {
+ ret = sun8i_codec_add_lineout(cmpnt);
+ if (ret)
+ return ret;
+ }
+
+ if (quirks->has_mbias) {
+ ret = sun8i_codec_add_mbias(cmpnt);
+ if (ret)
+ return ret;
+ }
+
+ if (quirks->has_mic2) {
+ ret = sun8i_codec_add_mic2(cmpnt);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct snd_soc_component_driver sun8i_codec_analog_cmpnt_drv = {
+ .controls = sun8i_codec_common_controls,
+ .num_controls = ARRAY_SIZE(sun8i_codec_common_controls),
+ .dapm_widgets = sun8i_codec_common_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(sun8i_codec_common_widgets),
+ .dapm_routes = sun8i_codec_common_routes,
+ .num_dapm_routes = ARRAY_SIZE(sun8i_codec_common_routes),
+ .probe = sun8i_codec_analog_cmpnt_probe,
+};
+
+static const struct of_device_id sun8i_codec_analog_of_match[] = {
+ {
+ .compatible = "allwinner,sun8i-a23-codec-analog",
+ .data = &sun8i_a23_quirks,
+ },
+ {
+ .compatible = "allwinner,sun8i-h3-codec-analog",
+ .data = &sun8i_h3_quirks,
+ },
+ {
+ .compatible = "allwinner,sun8i-v3s-codec-analog",
+ .data = &sun8i_v3s_quirks,
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, sun8i_codec_analog_of_match);
+
+static int sun8i_codec_analog_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+ void __iomem *base;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base)) {
+ dev_err(&pdev->dev, "Failed to map the registers\n");
+ return PTR_ERR(base);
+ }
+
+ regmap = sun8i_adda_pr_regmap_init(&pdev->dev, base);
+ if (IS_ERR(regmap)) {
+ dev_err(&pdev->dev, "Failed to create regmap\n");
+ return PTR_ERR(regmap);
+ }
+
+ return devm_snd_soc_register_component(&pdev->dev,
+ &sun8i_codec_analog_cmpnt_drv,
+ NULL, 0);
+}
+
+static struct platform_driver sun8i_codec_analog_driver = {
+ .driver = {
+ .name = "sun8i-codec-analog",
+ .of_match_table = sun8i_codec_analog_of_match,
+ },
+ .probe = sun8i_codec_analog_probe,
+};
+module_platform_driver(sun8i_codec_analog_driver);
+
+MODULE_DESCRIPTION("Allwinner internal codec analog controls driver");
+MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:sun8i-codec-analog");
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
new file mode 100644
index 000000000..4c0d0d7d3
--- /dev/null
+++ b/sound/soc/sunxi/sun8i-codec.c
@@ -0,0 +1,1393 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * This driver supports the digital controls for the internal codec
+ * found in Allwinner's A33 SoCs.
+ *
+ * (C) Copyright 2010-2016
+ * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
+ * huangxin <huangxin@Reuuimllatech.com>
+ * Mylène Josserand <mylene.josserand@free-electrons.com>
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/log2.h>
+
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/tlv.h>
+
+#define SUN8I_SYSCLK_CTL 0x00c
+#define SUN8I_SYSCLK_CTL_AIF1CLK_ENA 11
+#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL (0x2 << 8)
+#define SUN8I_SYSCLK_CTL_AIF2CLK_ENA 7
+#define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_PLL (0x2 << 4)
+#define SUN8I_SYSCLK_CTL_SYSCLK_ENA 3
+#define SUN8I_SYSCLK_CTL_SYSCLK_SRC 0
+#define SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF1CLK (0x0 << 0)
+#define SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF2CLK (0x1 << 0)
+#define SUN8I_MOD_CLK_ENA 0x010
+#define SUN8I_MOD_CLK_ENA_AIF1 15
+#define SUN8I_MOD_CLK_ENA_AIF2 14
+#define SUN8I_MOD_CLK_ENA_AIF3 13
+#define SUN8I_MOD_CLK_ENA_ADC 3
+#define SUN8I_MOD_CLK_ENA_DAC 2
+#define SUN8I_MOD_RST_CTL 0x014
+#define SUN8I_MOD_RST_CTL_AIF1 15
+#define SUN8I_MOD_RST_CTL_AIF2 14
+#define SUN8I_MOD_RST_CTL_AIF3 13
+#define SUN8I_MOD_RST_CTL_ADC 3
+#define SUN8I_MOD_RST_CTL_DAC 2
+#define SUN8I_SYS_SR_CTRL 0x018
+#define SUN8I_SYS_SR_CTRL_AIF1_FS 12
+#define SUN8I_SYS_SR_CTRL_AIF2_FS 8
+#define SUN8I_AIF_CLK_CTRL(n) (0x040 * (1 + (n)))
+#define SUN8I_AIF_CLK_CTRL_MSTR_MOD 15
+#define SUN8I_AIF_CLK_CTRL_CLK_INV 13
+#define SUN8I_AIF_CLK_CTRL_BCLK_DIV 9
+#define SUN8I_AIF_CLK_CTRL_LRCK_DIV 6
+#define SUN8I_AIF_CLK_CTRL_WORD_SIZ 4
+#define SUN8I_AIF_CLK_CTRL_DATA_FMT 2
+#define SUN8I_AIF1_ADCDAT_CTRL 0x044
+#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15
+#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14
+#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC 10
+#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC 8
+#define SUN8I_AIF1_DACDAT_CTRL 0x048
+#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15
+#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14
+#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_SRC 10
+#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_SRC 8
+#define SUN8I_AIF1_MXR_SRC 0x04c
+#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L 15
+#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL 14
+#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL 13
+#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR 12
+#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R 11
+#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR 10
+#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR 9
+#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL 8
+#define SUN8I_AIF1_VOL_CTRL1 0x050
+#define SUN8I_AIF1_VOL_CTRL1_AD0L_VOL 8
+#define SUN8I_AIF1_VOL_CTRL1_AD0R_VOL 0
+#define SUN8I_AIF1_VOL_CTRL3 0x058
+#define SUN8I_AIF1_VOL_CTRL3_DA0L_VOL 8
+#define SUN8I_AIF1_VOL_CTRL3_DA0R_VOL 0
+#define SUN8I_AIF2_ADCDAT_CTRL 0x084
+#define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_ENA 15
+#define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_ENA 14
+#define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_SRC 10
+#define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_SRC 8
+#define SUN8I_AIF2_DACDAT_CTRL 0x088
+#define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_ENA 15
+#define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_ENA 14
+#define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_SRC 10
+#define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_SRC 8
+#define SUN8I_AIF2_MXR_SRC 0x08c
+#define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA0L 15
+#define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA1L 14
+#define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF2DACR 13
+#define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_ADCL 12
+#define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA0R 11
+#define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA1R 10
+#define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF2DACL 9
+#define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_ADCR 8
+#define SUN8I_AIF2_VOL_CTRL1 0x090
+#define SUN8I_AIF2_VOL_CTRL1_ADCL_VOL 8
+#define SUN8I_AIF2_VOL_CTRL1_ADCR_VOL 0
+#define SUN8I_AIF2_VOL_CTRL2 0x098
+#define SUN8I_AIF2_VOL_CTRL2_DACL_VOL 8
+#define SUN8I_AIF2_VOL_CTRL2_DACR_VOL 0
+#define SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_AIF1 (0x0 << 0)
+#define SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_AIF2 (0x1 << 0)
+#define SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_AIF1CLK (0x2 << 0)
+#define SUN8I_AIF3_PATH_CTRL 0x0cc
+#define SUN8I_AIF3_PATH_CTRL_AIF3_ADC_SRC 10
+#define SUN8I_AIF3_PATH_CTRL_AIF2_DAC_SRC 8
+#define SUN8I_AIF3_PATH_CTRL_AIF3_PINS_TRI 7
+#define SUN8I_ADC_DIG_CTRL 0x100
+#define SUN8I_ADC_DIG_CTRL_ENAD 15
+#define SUN8I_ADC_DIG_CTRL_ADOUT_DTS 2
+#define SUN8I_ADC_DIG_CTRL_ADOUT_DLY 1
+#define SUN8I_ADC_VOL_CTRL 0x104
+#define SUN8I_ADC_VOL_CTRL_ADCL_VOL 8
+#define SUN8I_ADC_VOL_CTRL_ADCR_VOL 0
+#define SUN8I_DAC_DIG_CTRL 0x120
+#define SUN8I_DAC_DIG_CTRL_ENDA 15
+#define SUN8I_DAC_VOL_CTRL 0x124
+#define SUN8I_DAC_VOL_CTRL_DACL_VOL 8
+#define SUN8I_DAC_VOL_CTRL_DACR_VOL 0
+#define SUN8I_DAC_MXR_SRC 0x130
+#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L 15
+#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L 14
+#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL 13
+#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL 12
+#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R 11
+#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R 10
+#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9
+#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8
+
+#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK GENMASK(9, 8)
+#define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK GENMASK(5, 4)
+#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12)
+#define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8)
+#define SUN8I_AIF_CLK_CTRL_CLK_INV_MASK GENMASK(14, 13)
+#define SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK GENMASK(12, 9)
+#define SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK GENMASK(8, 6)
+#define SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK GENMASK(5, 4)
+#define SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK GENMASK(3, 2)
+#define SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_MASK GENMASK(1, 0)
+
+#define SUN8I_CODEC_PASSTHROUGH_SAMPLE_RATE 48000
+
+#define SUN8I_CODEC_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 |\
+ SNDRV_PCM_FMTBIT_S16_LE |\
+ SNDRV_PCM_FMTBIT_S20_LE |\
+ SNDRV_PCM_FMTBIT_S24_LE |\
+ SNDRV_PCM_FMTBIT_S20_3LE|\
+ SNDRV_PCM_FMTBIT_S24_3LE)
+
+#define SUN8I_CODEC_PCM_RATES (SNDRV_PCM_RATE_8000_48000|\
+ SNDRV_PCM_RATE_88200 |\
+ SNDRV_PCM_RATE_96000 |\
+ SNDRV_PCM_RATE_176400 |\
+ SNDRV_PCM_RATE_192000 |\
+ SNDRV_PCM_RATE_KNOT)
+
+enum {
+ SUN8I_CODEC_AIF1,
+ SUN8I_CODEC_AIF2,
+ SUN8I_CODEC_AIF3,
+ SUN8I_CODEC_NAIFS
+};
+
+struct sun8i_codec_aif {
+ unsigned int lrck_div_order;
+ unsigned int sample_rate;
+ unsigned int slots;
+ unsigned int slot_width;
+ unsigned int active_streams : 2;
+ unsigned int open_streams : 2;
+};
+
+struct sun8i_codec_quirks {
+ bool legacy_widgets : 1;
+ bool lrck_inversion : 1;
+};
+
+struct sun8i_codec {
+ struct regmap *regmap;
+ struct clk *clk_module;
+ const struct sun8i_codec_quirks *quirks;
+ struct sun8i_codec_aif aifs[SUN8I_CODEC_NAIFS];
+ unsigned int sysclk_rate;
+ int sysclk_refcnt;
+};
+
+static struct snd_soc_dai_driver sun8i_codec_dais[];
+
+static int sun8i_codec_runtime_resume(struct device *dev)
+{
+ struct sun8i_codec *scodec = dev_get_drvdata(dev);
+ int ret;
+
+ regcache_cache_only(scodec->regmap, false);
+
+ ret = regcache_sync(scodec->regmap);
+ if (ret) {
+ dev_err(dev, "Failed to sync regmap cache\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int sun8i_codec_runtime_suspend(struct device *dev)
+{
+ struct sun8i_codec *scodec = dev_get_drvdata(dev);
+
+ regcache_cache_only(scodec->regmap, true);
+ regcache_mark_dirty(scodec->regmap);
+
+ return 0;
+}
+
+static int sun8i_codec_get_hw_rate(unsigned int sample_rate)
+{
+ switch (sample_rate) {
+ case 7350:
+ case 8000:
+ return 0x0;
+ case 11025:
+ return 0x1;
+ case 12000:
+ return 0x2;
+ case 14700:
+ case 16000:
+ return 0x3;
+ case 22050:
+ return 0x4;
+ case 24000:
+ return 0x5;
+ case 29400:
+ case 32000:
+ return 0x6;
+ case 44100:
+ return 0x7;
+ case 48000:
+ return 0x8;
+ case 88200:
+ case 96000:
+ return 0x9;
+ case 176400:
+ case 192000:
+ return 0xa;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int sun8i_codec_update_sample_rate(struct sun8i_codec *scodec)
+{
+ unsigned int max_rate = 0;
+ int hw_rate, i;
+
+ for (i = SUN8I_CODEC_AIF1; i < SUN8I_CODEC_NAIFS; ++i) {
+ struct sun8i_codec_aif *aif = &scodec->aifs[i];
+
+ if (aif->active_streams)
+ max_rate = max(max_rate, aif->sample_rate);
+ }
+
+ /* Set the sample rate for ADC->DAC passthrough when no AIF is active. */
+ if (!max_rate)
+ max_rate = SUN8I_CODEC_PASSTHROUGH_SAMPLE_RATE;
+
+ hw_rate = sun8i_codec_get_hw_rate(max_rate);
+ if (hw_rate < 0)
+ return hw_rate;
+
+ regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL,
+ SUN8I_SYS_SR_CTRL_AIF1_FS_MASK,
+ hw_rate << SUN8I_SYS_SR_CTRL_AIF1_FS);
+
+ return 0;
+}
+
+static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+ struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai);
+ u32 dsp_format, format, invert, value;
+
+ /* clock masters */
+ switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
+ case SND_SOC_DAIFMT_CBC_CFC: /* Codec slave, DAI master */
+ value = 0x1;
+ break;
+ case SND_SOC_DAIFMT_CBP_CFP: /* Codec Master, DAI slave */
+ value = 0x0;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (dai->id == SUN8I_CODEC_AIF3) {
+ /* AIF3 only supports master mode. */
+ if (value)
+ return -EINVAL;
+
+ /* Use the AIF2 BCLK and LRCK for AIF3. */
+ regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
+ SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_MASK,
+ SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_AIF2);
+ } else {
+ regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
+ BIT(SUN8I_AIF_CLK_CTRL_MSTR_MOD),
+ value << SUN8I_AIF_CLK_CTRL_MSTR_MOD);
+ }
+
+ /* DAI format */
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_I2S:
+ format = 0x0;
+ break;
+ case SND_SOC_DAIFMT_LEFT_J:
+ format = 0x1;
+ break;
+ case SND_SOC_DAIFMT_RIGHT_J:
+ format = 0x2;
+ break;
+ case SND_SOC_DAIFMT_DSP_A:
+ format = 0x3;
+ dsp_format = 0x0; /* Set LRCK_INV to 0 */
+ break;
+ case SND_SOC_DAIFMT_DSP_B:
+ format = 0x3;
+ dsp_format = 0x1; /* Set LRCK_INV to 1 */
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (dai->id == SUN8I_CODEC_AIF3) {
+ /* AIF3 only supports DSP mode. */
+ if (format != 3)
+ return -EINVAL;
+ } else {
+ regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
+ SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK,
+ format << SUN8I_AIF_CLK_CTRL_DATA_FMT);
+ }
+
+ /* clock inversion */
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_NB_NF: /* Normal */
+ invert = 0x0;
+ break;
+ case SND_SOC_DAIFMT_NB_IF: /* Inverted LRCK */
+ invert = 0x1;
+ break;
+ case SND_SOC_DAIFMT_IB_NF: /* Inverted BCLK */
+ invert = 0x2;
+ break;
+ case SND_SOC_DAIFMT_IB_IF: /* Both inverted */
+ invert = 0x3;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (format == 0x3) {
+ /* Inverted LRCK is not available in DSP mode. */
+ if (invert & BIT(0))
+ return -EINVAL;
+
+ /* Instead, the bit selects between DSP A/B formats. */
+ invert |= dsp_format;
+ } else {
+ /*
+ * It appears that the DAI and the codec in the A33 SoC don't
+ * share the same polarity for the LRCK signal when they mean
+ * 'normal' and 'inverted' in the datasheet.
+ *
+ * Since the DAI here is our regular i2s driver that have been
+ * tested with way more codecs than just this one, it means
+ * that the codec probably gets it backward, and we have to
+ * invert the value here.
+ */
+ invert ^= scodec->quirks->lrck_inversion;
+ }
+
+ regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
+ SUN8I_AIF_CLK_CTRL_CLK_INV_MASK,
+ invert << SUN8I_AIF_CLK_CTRL_CLK_INV);
+
+ return 0;
+}
+
+static int sun8i_codec_set_tdm_slot(struct snd_soc_dai *dai,
+ unsigned int tx_mask, unsigned int rx_mask,
+ int slots, int slot_width)
+{
+ struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai);
+ struct sun8i_codec_aif *aif = &scodec->aifs[dai->id];
+
+ if (slot_width && !is_power_of_2(slot_width))
+ return -EINVAL;
+
+ aif->slots = slots;
+ aif->slot_width = slot_width;
+
+ return 0;
+}
+
+static const unsigned int sun8i_codec_rates[] = {
+ 7350, 8000, 11025, 12000, 14700, 16000, 22050, 24000,
+ 29400, 32000, 44100, 48000, 88200, 96000, 176400, 192000,
+};
+
+static const struct snd_pcm_hw_constraint_list sun8i_codec_all_rates = {
+ .list = sun8i_codec_rates,
+ .count = ARRAY_SIZE(sun8i_codec_rates),
+};
+
+static const struct snd_pcm_hw_constraint_list sun8i_codec_22M_rates = {
+ .list = sun8i_codec_rates,
+ .count = ARRAY_SIZE(sun8i_codec_rates),
+ .mask = 0x5555,
+};
+
+static const struct snd_pcm_hw_constraint_list sun8i_codec_24M_rates = {
+ .list = sun8i_codec_rates,
+ .count = ARRAY_SIZE(sun8i_codec_rates),
+ .mask = 0xaaaa,
+};
+
+static int sun8i_codec_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai);
+ const struct snd_pcm_hw_constraint_list *list;
+
+ /* hw_constraints is not relevant for codec2codec DAIs. */
+ if (dai->id != SUN8I_CODEC_AIF1)
+ return 0;
+
+ if (!scodec->sysclk_refcnt)
+ list = &sun8i_codec_all_rates;
+ else if (scodec->sysclk_rate == 22579200)
+ list = &sun8i_codec_22M_rates;
+ else if (scodec->sysclk_rate == 24576000)
+ list = &sun8i_codec_24M_rates;
+ else
+ return -EINVAL;
+
+ return snd_pcm_hw_constraint_list(substream->runtime, 0,
+ SNDRV_PCM_HW_PARAM_RATE, list);
+}
+
+struct sun8i_codec_clk_div {
+ u8 div;
+ u8 val;
+};
+
+static const struct sun8i_codec_clk_div sun8i_codec_bclk_div[] = {
+ { .div = 1, .val = 0 },
+ { .div = 2, .val = 1 },
+ { .div = 4, .val = 2 },
+ { .div = 6, .val = 3 },
+ { .div = 8, .val = 4 },
+ { .div = 12, .val = 5 },
+ { .div = 16, .val = 6 },
+ { .div = 24, .val = 7 },
+ { .div = 32, .val = 8 },
+ { .div = 48, .val = 9 },
+ { .div = 64, .val = 10 },
+ { .div = 96, .val = 11 },
+ { .div = 128, .val = 12 },
+ { .div = 192, .val = 13 },
+};
+
+static int sun8i_codec_get_bclk_div(unsigned int sysclk_rate,
+ unsigned int lrck_div_order,
+ unsigned int sample_rate)
+{
+ unsigned int div = sysclk_rate / sample_rate >> lrck_div_order;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(sun8i_codec_bclk_div); i++) {
+ const struct sun8i_codec_clk_div *bdiv = &sun8i_codec_bclk_div[i];
+
+ if (bdiv->div == div)
+ return bdiv->val;
+ }
+
+ return -EINVAL;
+}
+
+static int sun8i_codec_get_lrck_div_order(unsigned int slots,
+ unsigned int slot_width)
+{
+ unsigned int div = slots * slot_width;
+
+ if (div < 16 || div > 256)
+ return -EINVAL;
+
+ return order_base_2(div);
+}
+
+static unsigned int sun8i_codec_get_sysclk_rate(unsigned int sample_rate)
+{
+ return (sample_rate % 4000) ? 22579200 : 24576000;
+}
+
+static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai);
+ struct sun8i_codec_aif *aif = &scodec->aifs[dai->id];
+ unsigned int sample_rate = params_rate(params);
+ unsigned int slots = aif->slots ?: params_channels(params);
+ unsigned int slot_width = aif->slot_width ?: params_width(params);
+ unsigned int sysclk_rate = sun8i_codec_get_sysclk_rate(sample_rate);
+ int bclk_div, lrck_div_order, ret, word_size;
+ u32 clk_reg;
+
+ /* word size */
+ switch (params_width(params)) {
+ case 8:
+ word_size = 0x0;
+ break;
+ case 16:
+ word_size = 0x1;
+ break;
+ case 20:
+ word_size = 0x2;
+ break;
+ case 24:
+ word_size = 0x3;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
+ SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK,
+ word_size << SUN8I_AIF_CLK_CTRL_WORD_SIZ);
+
+ /* LRCK divider (BCLK/LRCK ratio) */
+ lrck_div_order = sun8i_codec_get_lrck_div_order(slots, slot_width);
+ if (lrck_div_order < 0)
+ return lrck_div_order;
+
+ if (dai->id == SUN8I_CODEC_AIF2 || dai->id == SUN8I_CODEC_AIF3) {
+ /* AIF2 and AIF3 share AIF2's BCLK and LRCK generation circuitry. */
+ int partner = (SUN8I_CODEC_AIF2 + SUN8I_CODEC_AIF3) - dai->id;
+ const struct sun8i_codec_aif *partner_aif = &scodec->aifs[partner];
+ const char *partner_name = sun8i_codec_dais[partner].name;
+
+ if (partner_aif->open_streams &&
+ (lrck_div_order != partner_aif->lrck_div_order ||
+ sample_rate != partner_aif->sample_rate)) {
+ dev_err(dai->dev,
+ "%s sample and bit rates must match %s when both are used\n",
+ dai->name, partner_name);
+ return -EBUSY;
+ }
+
+ clk_reg = SUN8I_AIF_CLK_CTRL(SUN8I_CODEC_AIF2);
+ } else {
+ clk_reg = SUN8I_AIF_CLK_CTRL(dai->id);
+ }
+
+ regmap_update_bits(scodec->regmap, clk_reg,
+ SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK,
+ (lrck_div_order - 4) << SUN8I_AIF_CLK_CTRL_LRCK_DIV);
+
+ /* BCLK divider (SYSCLK/BCLK ratio) */
+ bclk_div = sun8i_codec_get_bclk_div(sysclk_rate, lrck_div_order, sample_rate);
+ if (bclk_div < 0)
+ return bclk_div;
+
+ regmap_update_bits(scodec->regmap, clk_reg,
+ SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK,
+ bclk_div << SUN8I_AIF_CLK_CTRL_BCLK_DIV);
+
+ /*
+ * SYSCLK rate
+ *
+ * Clock rate protection is reference counted; but hw_params may be
+ * called many times per substream, without matching calls to hw_free.
+ * Protect the clock rate once per AIF, on the first hw_params call
+ * for the first substream. clk_set_rate() will allow clock rate
+ * changes on subsequent calls if only one AIF has open streams.
+ */
+ ret = (aif->open_streams ? clk_set_rate : clk_set_rate_exclusive)(scodec->clk_module,
+ sysclk_rate);
+ if (ret == -EBUSY)
+ dev_err(dai->dev,
+ "%s sample rate (%u Hz) conflicts with other audio streams\n",
+ dai->name, sample_rate);
+ if (ret < 0)
+ return ret;
+
+ if (!aif->open_streams)
+ scodec->sysclk_refcnt++;
+ scodec->sysclk_rate = sysclk_rate;
+
+ aif->lrck_div_order = lrck_div_order;
+ aif->sample_rate = sample_rate;
+ aif->open_streams |= BIT(substream->stream);
+
+ return sun8i_codec_update_sample_rate(scodec);
+}
+
+static int sun8i_codec_hw_free(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai);
+ struct sun8i_codec_aif *aif = &scodec->aifs[dai->id];
+
+ /* Drop references when the last substream for the AIF is freed. */
+ if (aif->open_streams != BIT(substream->stream))
+ goto done;
+
+ clk_rate_exclusive_put(scodec->clk_module);
+ scodec->sysclk_refcnt--;
+ aif->lrck_div_order = 0;
+ aif->sample_rate = 0;
+
+done:
+ aif->open_streams &= ~BIT(substream->stream);
+ return 0;
+}
+
+static const struct snd_soc_dai_ops sun8i_codec_dai_ops = {
+ .set_fmt = sun8i_codec_set_fmt,
+ .set_tdm_slot = sun8i_codec_set_tdm_slot,
+ .startup = sun8i_codec_startup,
+ .hw_params = sun8i_codec_hw_params,
+ .hw_free = sun8i_codec_hw_free,
+};
+
+static struct snd_soc_dai_driver sun8i_codec_dais[] = {
+ {
+ .name = "sun8i-codec-aif1",
+ .id = SUN8I_CODEC_AIF1,
+ .ops = &sun8i_codec_dai_ops,
+ /* capture capabilities */
+ .capture = {
+ .stream_name = "AIF1 Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SUN8I_CODEC_PCM_RATES,
+ .formats = SUN8I_CODEC_PCM_FORMATS,
+ .sig_bits = 24,
+ },
+ /* playback capabilities */
+ .playback = {
+ .stream_name = "AIF1 Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SUN8I_CODEC_PCM_RATES,
+ .formats = SUN8I_CODEC_PCM_FORMATS,
+ },
+ .symmetric_rate = true,
+ .symmetric_channels = true,
+ .symmetric_sample_bits = true,
+ },
+ {
+ .name = "sun8i-codec-aif2",
+ .id = SUN8I_CODEC_AIF2,
+ .ops = &sun8i_codec_dai_ops,
+ /* capture capabilities */
+ .capture = {
+ .stream_name = "AIF2 Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SUN8I_CODEC_PCM_RATES,
+ .formats = SUN8I_CODEC_PCM_FORMATS,
+ .sig_bits = 24,
+ },
+ /* playback capabilities */
+ .playback = {
+ .stream_name = "AIF2 Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SUN8I_CODEC_PCM_RATES,
+ .formats = SUN8I_CODEC_PCM_FORMATS,
+ },
+ .symmetric_rate = true,
+ .symmetric_channels = true,
+ .symmetric_sample_bits = true,
+ },
+ {
+ .name = "sun8i-codec-aif3",
+ .id = SUN8I_CODEC_AIF3,
+ .ops = &sun8i_codec_dai_ops,
+ /* capture capabilities */
+ .capture = {
+ .stream_name = "AIF3 Capture",
+ .channels_min = 1,
+ .channels_max = 1,
+ .rates = SUN8I_CODEC_PCM_RATES,
+ .formats = SUN8I_CODEC_PCM_FORMATS,
+ .sig_bits = 24,
+ },
+ /* playback capabilities */
+ .playback = {
+ .stream_name = "AIF3 Playback",
+ .channels_min = 1,
+ .channels_max = 1,
+ .rates = SUN8I_CODEC_PCM_RATES,
+ .formats = SUN8I_CODEC_PCM_FORMATS,
+ },
+ .symmetric_rate = true,
+ .symmetric_channels = true,
+ .symmetric_sample_bits = true,
+ },
+};
+
+static const DECLARE_TLV_DB_SCALE(sun8i_codec_vol_scale, -12000, 75, 1);
+
+static const struct snd_kcontrol_new sun8i_codec_controls[] = {
+ SOC_DOUBLE_TLV("AIF1 AD0 Capture Volume",
+ SUN8I_AIF1_VOL_CTRL1,
+ SUN8I_AIF1_VOL_CTRL1_AD0L_VOL,
+ SUN8I_AIF1_VOL_CTRL1_AD0R_VOL,
+ 0xc0, 0, sun8i_codec_vol_scale),
+ SOC_DOUBLE_TLV("AIF1 DA0 Playback Volume",
+ SUN8I_AIF1_VOL_CTRL3,
+ SUN8I_AIF1_VOL_CTRL3_DA0L_VOL,
+ SUN8I_AIF1_VOL_CTRL3_DA0R_VOL,
+ 0xc0, 0, sun8i_codec_vol_scale),
+ SOC_DOUBLE_TLV("AIF2 ADC Capture Volume",
+ SUN8I_AIF2_VOL_CTRL1,
+ SUN8I_AIF2_VOL_CTRL1_ADCL_VOL,
+ SUN8I_AIF2_VOL_CTRL1_ADCR_VOL,
+ 0xc0, 0, sun8i_codec_vol_scale),
+ SOC_DOUBLE_TLV("AIF2 DAC Playback Volume",
+ SUN8I_AIF2_VOL_CTRL2,
+ SUN8I_AIF2_VOL_CTRL2_DACL_VOL,
+ SUN8I_AIF2_VOL_CTRL2_DACR_VOL,
+ 0xc0, 0, sun8i_codec_vol_scale),
+ SOC_DOUBLE_TLV("ADC Capture Volume",
+ SUN8I_ADC_VOL_CTRL,
+ SUN8I_ADC_VOL_CTRL_ADCL_VOL,
+ SUN8I_ADC_VOL_CTRL_ADCR_VOL,
+ 0xc0, 0, sun8i_codec_vol_scale),
+ SOC_DOUBLE_TLV("DAC Playback Volume",
+ SUN8I_DAC_VOL_CTRL,
+ SUN8I_DAC_VOL_CTRL_DACL_VOL,
+ SUN8I_DAC_VOL_CTRL_DACR_VOL,
+ 0xc0, 0, sun8i_codec_vol_scale),
+};
+
+static int sun8i_codec_aif_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
+ struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component);
+ struct sun8i_codec_aif *aif = &scodec->aifs[w->sname[3] - '1'];
+ int stream = w->id == snd_soc_dapm_aif_out;
+
+ if (SND_SOC_DAPM_EVENT_ON(event))
+ aif->active_streams |= BIT(stream);
+ else
+ aif->active_streams &= ~BIT(stream);
+
+ return sun8i_codec_update_sample_rate(scodec);
+}
+
+static const char *const sun8i_aif_stereo_mux_enum_values[] = {
+ "Stereo", "Reverse Stereo", "Sum Mono", "Mix Mono"
+};
+
+static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_ad0_stereo_mux_enum,
+ SUN8I_AIF1_ADCDAT_CTRL,
+ SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC,
+ SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC,
+ sun8i_aif_stereo_mux_enum_values);
+
+static const struct snd_kcontrol_new sun8i_aif1_ad0_stereo_mux_control =
+ SOC_DAPM_ENUM("AIF1 AD0 Stereo Capture Route",
+ sun8i_aif1_ad0_stereo_mux_enum);
+
+static SOC_ENUM_DOUBLE_DECL(sun8i_aif2_adc_stereo_mux_enum,
+ SUN8I_AIF2_ADCDAT_CTRL,
+ SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_SRC,
+ SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_SRC,
+ sun8i_aif_stereo_mux_enum_values);
+
+static const struct snd_kcontrol_new sun8i_aif2_adc_stereo_mux_control =
+ SOC_DAPM_ENUM("AIF2 ADC Stereo Capture Route",
+ sun8i_aif2_adc_stereo_mux_enum);
+
+static const char *const sun8i_aif3_adc_mux_enum_values[] = {
+ "None", "AIF2 ADCL", "AIF2 ADCR"
+};
+
+static SOC_ENUM_SINGLE_DECL(sun8i_aif3_adc_mux_enum,
+ SUN8I_AIF3_PATH_CTRL,
+ SUN8I_AIF3_PATH_CTRL_AIF3_ADC_SRC,
+ sun8i_aif3_adc_mux_enum_values);
+
+static const struct snd_kcontrol_new sun8i_aif3_adc_mux_control =
+ SOC_DAPM_ENUM("AIF3 ADC Source Capture Route",
+ sun8i_aif3_adc_mux_enum);
+
+static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = {
+ SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital ADC Capture Switch",
+ SUN8I_AIF1_MXR_SRC,
+ SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L,
+ SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R, 1, 0),
+ SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch",
+ SUN8I_AIF1_MXR_SRC,
+ SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL,
+ SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR, 1, 0),
+ SOC_DAPM_DOUBLE("AIF1 Data Digital ADC Capture Switch",
+ SUN8I_AIF1_MXR_SRC,
+ SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL,
+ SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR, 1, 0),
+ SOC_DAPM_DOUBLE("AIF2 Inv Digital ADC Capture Switch",
+ SUN8I_AIF1_MXR_SRC,
+ SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR,
+ SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0),
+};
+
+static const struct snd_kcontrol_new sun8i_aif2_adc_mixer_controls[] = {
+ SOC_DAPM_DOUBLE("AIF2 ADC Mixer AIF1 DA0 Capture Switch",
+ SUN8I_AIF2_MXR_SRC,
+ SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA0L,
+ SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA0R, 1, 0),
+ SOC_DAPM_DOUBLE("AIF2 ADC Mixer AIF1 DA1 Capture Switch",
+ SUN8I_AIF2_MXR_SRC,
+ SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA1L,
+ SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA1R, 1, 0),
+ SOC_DAPM_DOUBLE("AIF2 ADC Mixer AIF2 DAC Rev Capture Switch",
+ SUN8I_AIF2_MXR_SRC,
+ SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF2DACR,
+ SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF2DACL, 1, 0),
+ SOC_DAPM_DOUBLE("AIF2 ADC Mixer ADC Capture Switch",
+ SUN8I_AIF2_MXR_SRC,
+ SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_ADCL,
+ SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_ADCR, 1, 0),
+};
+
+static const char *const sun8i_aif2_dac_mux_enum_values[] = {
+ "AIF2", "AIF3+2", "AIF2+3"
+};
+
+static SOC_ENUM_SINGLE_DECL(sun8i_aif2_dac_mux_enum,
+ SUN8I_AIF3_PATH_CTRL,
+ SUN8I_AIF3_PATH_CTRL_AIF2_DAC_SRC,
+ sun8i_aif2_dac_mux_enum_values);
+
+static const struct snd_kcontrol_new sun8i_aif2_dac_mux_control =
+ SOC_DAPM_ENUM("AIF2 DAC Source Playback Route",
+ sun8i_aif2_dac_mux_enum);
+
+static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_da0_stereo_mux_enum,
+ SUN8I_AIF1_DACDAT_CTRL,
+ SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_SRC,
+ SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_SRC,
+ sun8i_aif_stereo_mux_enum_values);
+
+static const struct snd_kcontrol_new sun8i_aif1_da0_stereo_mux_control =
+ SOC_DAPM_ENUM("AIF1 DA0 Stereo Playback Route",
+ sun8i_aif1_da0_stereo_mux_enum);
+
+static SOC_ENUM_DOUBLE_DECL(sun8i_aif2_dac_stereo_mux_enum,
+ SUN8I_AIF2_DACDAT_CTRL,
+ SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_SRC,
+ SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_SRC,
+ sun8i_aif_stereo_mux_enum_values);
+
+static const struct snd_kcontrol_new sun8i_aif2_dac_stereo_mux_control =
+ SOC_DAPM_ENUM("AIF2 DAC Stereo Playback Route",
+ sun8i_aif2_dac_stereo_mux_enum);
+
+static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = {
+ SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch",
+ SUN8I_DAC_MXR_SRC,
+ SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L,
+ SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0),
+ SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch",
+ SUN8I_DAC_MXR_SRC,
+ SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L,
+ SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0),
+ SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
+ SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL,
+ SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0),
+ SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
+ SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL,
+ SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0),
+};
+
+static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
+ /* System Clocks */
+ SND_SOC_DAPM_CLOCK_SUPPLY("mod"),
+
+ SND_SOC_DAPM_SUPPLY("AIF1CLK",
+ SUN8I_SYSCLK_CTL,
+ SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("AIF2CLK",
+ SUN8I_SYSCLK_CTL,
+ SUN8I_SYSCLK_CTL_AIF2CLK_ENA, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("SYSCLK",
+ SUN8I_SYSCLK_CTL,
+ SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0),
+
+ /* Module Clocks */
+ SND_SOC_DAPM_SUPPLY("CLK AIF1",
+ SUN8I_MOD_CLK_ENA,
+ SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("CLK AIF2",
+ SUN8I_MOD_CLK_ENA,
+ SUN8I_MOD_CLK_ENA_AIF2, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("CLK AIF3",
+ SUN8I_MOD_CLK_ENA,
+ SUN8I_MOD_CLK_ENA_AIF3, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("CLK ADC",
+ SUN8I_MOD_CLK_ENA,
+ SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("CLK DAC",
+ SUN8I_MOD_CLK_ENA,
+ SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0),
+
+ /* Module Resets */
+ SND_SOC_DAPM_SUPPLY("RST AIF1",
+ SUN8I_MOD_RST_CTL,
+ SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("RST AIF2",
+ SUN8I_MOD_RST_CTL,
+ SUN8I_MOD_RST_CTL_AIF2, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("RST AIF3",
+ SUN8I_MOD_RST_CTL,
+ SUN8I_MOD_RST_CTL_AIF3, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("RST ADC",
+ SUN8I_MOD_RST_CTL,
+ SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("RST DAC",
+ SUN8I_MOD_RST_CTL,
+ SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0),
+
+ /* Module Supplies */
+ SND_SOC_DAPM_SUPPLY("ADC",
+ SUN8I_ADC_DIG_CTRL,
+ SUN8I_ADC_DIG_CTRL_ENAD, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("DAC",
+ SUN8I_DAC_DIG_CTRL,
+ SUN8I_DAC_DIG_CTRL_ENDA, 0, NULL, 0),
+
+ /* AIF "ADC" Outputs */
+ SND_SOC_DAPM_AIF_OUT_E("AIF1 AD0L", "AIF1 Capture", 0,
+ SUN8I_AIF1_ADCDAT_CTRL,
+ SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0,
+ sun8i_codec_aif_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_AIF_OUT("AIF1 AD0R", "AIF1 Capture", 1,
+ SUN8I_AIF1_ADCDAT_CTRL,
+ SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0),
+
+ SND_SOC_DAPM_AIF_OUT_E("AIF2 ADCL", "AIF2 Capture", 0,
+ SUN8I_AIF2_ADCDAT_CTRL,
+ SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_ENA, 0,
+ sun8i_codec_aif_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_AIF_OUT("AIF2 ADCR", "AIF2 Capture", 1,
+ SUN8I_AIF2_ADCDAT_CTRL,
+ SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_ENA, 0),
+
+ SND_SOC_DAPM_AIF_OUT_E("AIF3 ADC", "AIF3 Capture", 0,
+ SND_SOC_NOPM, 0, 0,
+ sun8i_codec_aif_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ /* AIF "ADC" Mono/Stereo Muxes */
+ SND_SOC_DAPM_MUX("AIF1 AD0L Stereo Mux", SND_SOC_NOPM, 0, 0,
+ &sun8i_aif1_ad0_stereo_mux_control),
+ SND_SOC_DAPM_MUX("AIF1 AD0R Stereo Mux", SND_SOC_NOPM, 0, 0,
+ &sun8i_aif1_ad0_stereo_mux_control),
+
+ SND_SOC_DAPM_MUX("AIF2 ADCL Stereo Mux", SND_SOC_NOPM, 0, 0,
+ &sun8i_aif2_adc_stereo_mux_control),
+ SND_SOC_DAPM_MUX("AIF2 ADCR Stereo Mux", SND_SOC_NOPM, 0, 0,
+ &sun8i_aif2_adc_stereo_mux_control),
+
+ /* AIF "ADC" Output Muxes */
+ SND_SOC_DAPM_MUX("AIF3 ADC Source Capture Route", SND_SOC_NOPM, 0, 0,
+ &sun8i_aif3_adc_mux_control),
+
+ /* AIF "ADC" Mixers */
+ SOC_MIXER_ARRAY("AIF1 AD0L Mixer", SND_SOC_NOPM, 0, 0,
+ sun8i_aif1_ad0_mixer_controls),
+ SOC_MIXER_ARRAY("AIF1 AD0R Mixer", SND_SOC_NOPM, 0, 0,
+ sun8i_aif1_ad0_mixer_controls),
+
+ SOC_MIXER_ARRAY("AIF2 ADCL Mixer", SND_SOC_NOPM, 0, 0,
+ sun8i_aif2_adc_mixer_controls),
+ SOC_MIXER_ARRAY("AIF2 ADCR Mixer", SND_SOC_NOPM, 0, 0,
+ sun8i_aif2_adc_mixer_controls),
+
+ /* AIF "DAC" Input Muxes */
+ SND_SOC_DAPM_MUX("AIF2 DACL Source", SND_SOC_NOPM, 0, 0,
+ &sun8i_aif2_dac_mux_control),
+ SND_SOC_DAPM_MUX("AIF2 DACR Source", SND_SOC_NOPM, 0, 0,
+ &sun8i_aif2_dac_mux_control),
+
+ /* AIF "DAC" Mono/Stereo Muxes */
+ SND_SOC_DAPM_MUX("AIF1 DA0L Stereo Mux", SND_SOC_NOPM, 0, 0,
+ &sun8i_aif1_da0_stereo_mux_control),
+ SND_SOC_DAPM_MUX("AIF1 DA0R Stereo Mux", SND_SOC_NOPM, 0, 0,
+ &sun8i_aif1_da0_stereo_mux_control),
+
+ SND_SOC_DAPM_MUX("AIF2 DACL Stereo Mux", SND_SOC_NOPM, 0, 0,
+ &sun8i_aif2_dac_stereo_mux_control),
+ SND_SOC_DAPM_MUX("AIF2 DACR Stereo Mux", SND_SOC_NOPM, 0, 0,
+ &sun8i_aif2_dac_stereo_mux_control),
+
+ /* AIF "DAC" Inputs */
+ SND_SOC_DAPM_AIF_IN_E("AIF1 DA0L", "AIF1 Playback", 0,
+ SUN8I_AIF1_DACDAT_CTRL,
+ SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0,
+ sun8i_codec_aif_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_AIF_IN("AIF1 DA0R", "AIF1 Playback", 1,
+ SUN8I_AIF1_DACDAT_CTRL,
+ SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),
+
+ SND_SOC_DAPM_AIF_IN_E("AIF2 DACL", "AIF2 Playback", 0,
+ SUN8I_AIF2_DACDAT_CTRL,
+ SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_ENA, 0,
+ sun8i_codec_aif_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_AIF_IN("AIF2 DACR", "AIF2 Playback", 1,
+ SUN8I_AIF2_DACDAT_CTRL,
+ SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_ENA, 0),
+
+ SND_SOC_DAPM_AIF_IN_E("AIF3 DAC", "AIF3 Playback", 0,
+ SND_SOC_NOPM, 0, 0,
+ sun8i_codec_aif_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ /* ADC Inputs (connected to analog codec DAPM context) */
+ SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
+
+ /* DAC Outputs (connected to analog codec DAPM context) */
+ SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
+
+ /* DAC Mixers */
+ SOC_MIXER_ARRAY("DACL Mixer", SND_SOC_NOPM, 0, 0,
+ sun8i_dac_mixer_controls),
+ SOC_MIXER_ARRAY("DACR Mixer", SND_SOC_NOPM, 0, 0,
+ sun8i_dac_mixer_controls),
+};
+
+static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
+ /* Clock Routes */
+ { "AIF1CLK", NULL, "mod" },
+
+ { "SYSCLK", NULL, "AIF1CLK" },
+
+ { "CLK AIF1", NULL, "AIF1CLK" },
+ { "CLK AIF1", NULL, "SYSCLK" },
+ { "RST AIF1", NULL, "CLK AIF1" },
+ { "AIF1 AD0L", NULL, "RST AIF1" },
+ { "AIF1 AD0R", NULL, "RST AIF1" },
+ { "AIF1 DA0L", NULL, "RST AIF1" },
+ { "AIF1 DA0R", NULL, "RST AIF1" },
+
+ { "CLK AIF2", NULL, "AIF2CLK" },
+ { "CLK AIF2", NULL, "SYSCLK" },
+ { "RST AIF2", NULL, "CLK AIF2" },
+ { "AIF2 ADCL", NULL, "RST AIF2" },
+ { "AIF2 ADCR", NULL, "RST AIF2" },
+ { "AIF2 DACL", NULL, "RST AIF2" },
+ { "AIF2 DACR", NULL, "RST AIF2" },
+
+ { "CLK AIF3", NULL, "AIF1CLK" },
+ { "CLK AIF3", NULL, "SYSCLK" },
+ { "RST AIF3", NULL, "CLK AIF3" },
+ { "AIF3 ADC", NULL, "RST AIF3" },
+ { "AIF3 DAC", NULL, "RST AIF3" },
+
+ { "CLK ADC", NULL, "SYSCLK" },
+ { "RST ADC", NULL, "CLK ADC" },
+ { "ADC", NULL, "RST ADC" },
+ { "ADCL", NULL, "ADC" },
+ { "ADCR", NULL, "ADC" },
+
+ { "CLK DAC", NULL, "SYSCLK" },
+ { "RST DAC", NULL, "CLK DAC" },
+ { "DAC", NULL, "RST DAC" },
+ { "DACL", NULL, "DAC" },
+ { "DACR", NULL, "DAC" },
+
+ /* AIF "ADC" Output Routes */
+ { "AIF1 AD0L", NULL, "AIF1 AD0L Stereo Mux" },
+ { "AIF1 AD0R", NULL, "AIF1 AD0R Stereo Mux" },
+
+ { "AIF2 ADCL", NULL, "AIF2 ADCL Stereo Mux" },
+ { "AIF2 ADCR", NULL, "AIF2 ADCR Stereo Mux" },
+
+ { "AIF3 ADC", NULL, "AIF3 ADC Source Capture Route" },
+
+ /* AIF "ADC" Mono/Stereo Mux Routes */
+ { "AIF1 AD0L Stereo Mux", "Stereo", "AIF1 AD0L Mixer" },
+ { "AIF1 AD0L Stereo Mux", "Reverse Stereo", "AIF1 AD0R Mixer" },
+ { "AIF1 AD0L Stereo Mux", "Sum Mono", "AIF1 AD0L Mixer" },
+ { "AIF1 AD0L Stereo Mux", "Sum Mono", "AIF1 AD0R Mixer" },
+ { "AIF1 AD0L Stereo Mux", "Mix Mono", "AIF1 AD0L Mixer" },
+ { "AIF1 AD0L Stereo Mux", "Mix Mono", "AIF1 AD0R Mixer" },
+
+ { "AIF1 AD0R Stereo Mux", "Stereo", "AIF1 AD0R Mixer" },
+ { "AIF1 AD0R Stereo Mux", "Reverse Stereo", "AIF1 AD0L Mixer" },
+ { "AIF1 AD0R Stereo Mux", "Sum Mono", "AIF1 AD0L Mixer" },
+ { "AIF1 AD0R Stereo Mux", "Sum Mono", "AIF1 AD0R Mixer" },
+ { "AIF1 AD0R Stereo Mux", "Mix Mono", "AIF1 AD0L Mixer" },
+ { "AIF1 AD0R Stereo Mux", "Mix Mono", "AIF1 AD0R Mixer" },
+
+ { "AIF2 ADCL Stereo Mux", "Stereo", "AIF2 ADCL Mixer" },
+ { "AIF2 ADCL Stereo Mux", "Reverse Stereo", "AIF2 ADCR Mixer" },
+ { "AIF2 ADCL Stereo Mux", "Sum Mono", "AIF2 ADCL Mixer" },
+ { "AIF2 ADCL Stereo Mux", "Sum Mono", "AIF2 ADCR Mixer" },
+ { "AIF2 ADCL Stereo Mux", "Mix Mono", "AIF2 ADCL Mixer" },
+ { "AIF2 ADCL Stereo Mux", "Mix Mono", "AIF2 ADCR Mixer" },
+
+ { "AIF2 ADCR Stereo Mux", "Stereo", "AIF2 ADCR Mixer" },
+ { "AIF2 ADCR Stereo Mux", "Reverse Stereo", "AIF2 ADCL Mixer" },
+ { "AIF2 ADCR Stereo Mux", "Sum Mono", "AIF2 ADCL Mixer" },
+ { "AIF2 ADCR Stereo Mux", "Sum Mono", "AIF2 ADCR Mixer" },
+ { "AIF2 ADCR Stereo Mux", "Mix Mono", "AIF2 ADCL Mixer" },
+ { "AIF2 ADCR Stereo Mux", "Mix Mono", "AIF2 ADCR Mixer" },
+
+ /* AIF "ADC" Output Mux Routes */
+ { "AIF3 ADC Source Capture Route", "AIF2 ADCL", "AIF2 ADCL Mixer" },
+ { "AIF3 ADC Source Capture Route", "AIF2 ADCR", "AIF2 ADCR Mixer" },
+
+ /* AIF "ADC" Mixer Routes */
+ { "AIF1 AD0L Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0L Stereo Mux" },
+ { "AIF1 AD0L Mixer", "AIF2 Digital ADC Capture Switch", "AIF2 DACL Source" },
+ { "AIF1 AD0L Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCL" },
+ { "AIF1 AD0L Mixer", "AIF2 Inv Digital ADC Capture Switch", "AIF2 DACR Source" },
+
+ { "AIF1 AD0R Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0R Stereo Mux" },
+ { "AIF1 AD0R Mixer", "AIF2 Digital ADC Capture Switch", "AIF2 DACR Source" },
+ { "AIF1 AD0R Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCR" },
+ { "AIF1 AD0R Mixer", "AIF2 Inv Digital ADC Capture Switch", "AIF2 DACL Source" },
+
+ { "AIF2 ADCL Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0L Stereo Mux" },
+ { "AIF2 ADCL Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DACR Source" },
+ { "AIF2 ADCL Mixer", "AIF2 ADC Mixer ADC Capture Switch", "ADCL" },
+
+ { "AIF2 ADCR Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0R Stereo Mux" },
+ { "AIF2 ADCR Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DACL Source" },
+ { "AIF2 ADCR Mixer", "AIF2 ADC Mixer ADC Capture Switch", "ADCR" },
+
+ /* AIF "DAC" Input Mux Routes */
+ { "AIF2 DACL Source", "AIF2", "AIF2 DACL Stereo Mux" },
+ { "AIF2 DACL Source", "AIF3+2", "AIF3 DAC" },
+ { "AIF2 DACL Source", "AIF2+3", "AIF2 DACL Stereo Mux" },
+
+ { "AIF2 DACR Source", "AIF2", "AIF2 DACR Stereo Mux" },
+ { "AIF2 DACR Source", "AIF3+2", "AIF2 DACR Stereo Mux" },
+ { "AIF2 DACR Source", "AIF2+3", "AIF3 DAC" },
+
+ /* AIF "DAC" Mono/Stereo Mux Routes */
+ { "AIF1 DA0L Stereo Mux", "Stereo", "AIF1 DA0L" },
+ { "AIF1 DA0L Stereo Mux", "Reverse Stereo", "AIF1 DA0R" },
+ { "AIF1 DA0L Stereo Mux", "Sum Mono", "AIF1 DA0L" },
+ { "AIF1 DA0L Stereo Mux", "Sum Mono", "AIF1 DA0R" },
+ { "AIF1 DA0L Stereo Mux", "Mix Mono", "AIF1 DA0L" },
+ { "AIF1 DA0L Stereo Mux", "Mix Mono", "AIF1 DA0R" },
+
+ { "AIF1 DA0R Stereo Mux", "Stereo", "AIF1 DA0R" },
+ { "AIF1 DA0R Stereo Mux", "Reverse Stereo", "AIF1 DA0L" },
+ { "AIF1 DA0R Stereo Mux", "Sum Mono", "AIF1 DA0L" },
+ { "AIF1 DA0R Stereo Mux", "Sum Mono", "AIF1 DA0R" },
+ { "AIF1 DA0R Stereo Mux", "Mix Mono", "AIF1 DA0L" },
+ { "AIF1 DA0R Stereo Mux", "Mix Mono", "AIF1 DA0R" },
+
+ { "AIF2 DACL Stereo Mux", "Stereo", "AIF2 DACL" },
+ { "AIF2 DACL Stereo Mux", "Reverse Stereo", "AIF2 DACR" },
+ { "AIF2 DACL Stereo Mux", "Sum Mono", "AIF2 DACL" },
+ { "AIF2 DACL Stereo Mux", "Sum Mono", "AIF2 DACR" },
+ { "AIF2 DACL Stereo Mux", "Mix Mono", "AIF2 DACL" },
+ { "AIF2 DACL Stereo Mux", "Mix Mono", "AIF2 DACR" },
+
+ { "AIF2 DACR Stereo Mux", "Stereo", "AIF2 DACR" },
+ { "AIF2 DACR Stereo Mux", "Reverse Stereo", "AIF2 DACL" },
+ { "AIF2 DACR Stereo Mux", "Sum Mono", "AIF2 DACL" },
+ { "AIF2 DACR Stereo Mux", "Sum Mono", "AIF2 DACR" },
+ { "AIF2 DACR Stereo Mux", "Mix Mono", "AIF2 DACL" },
+ { "AIF2 DACR Stereo Mux", "Mix Mono", "AIF2 DACR" },
+
+ /* DAC Output Routes */
+ { "DACL", NULL, "DACL Mixer" },
+ { "DACR", NULL, "DACR Mixer" },
+
+ /* DAC Mixer Routes */
+ { "DACL Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0L Stereo Mux" },
+ { "DACL Mixer", "AIF2 Digital DAC Playback Switch", "AIF2 DACL Source" },
+ { "DACL Mixer", "ADC Digital DAC Playback Switch", "ADCL" },
+
+ { "DACR Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0R Stereo Mux" },
+ { "DACR Mixer", "AIF2 Digital DAC Playback Switch", "AIF2 DACR Source" },
+ { "DACR Mixer", "ADC Digital DAC Playback Switch", "ADCR" },
+};
+
+static const struct snd_soc_dapm_widget sun8i_codec_legacy_widgets[] = {
+ /* Legacy ADC Inputs (connected to analog codec DAPM context) */
+ SND_SOC_DAPM_ADC("AIF1 Slot 0 Left ADC", NULL, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_ADC("AIF1 Slot 0 Right ADC", NULL, SND_SOC_NOPM, 0, 0),
+
+ /* Legacy DAC Outputs (connected to analog codec DAPM context) */
+ SND_SOC_DAPM_DAC("AIF1 Slot 0 Left", NULL, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_DAC("AIF1 Slot 0 Right", NULL, SND_SOC_NOPM, 0, 0),
+};
+
+static const struct snd_soc_dapm_route sun8i_codec_legacy_routes[] = {
+ /* Legacy ADC Routes */
+ { "ADCL", NULL, "AIF1 Slot 0 Left ADC" },
+ { "ADCR", NULL, "AIF1 Slot 0 Right ADC" },
+
+ /* Legacy DAC Routes */
+ { "AIF1 Slot 0 Left", NULL, "DACL" },
+ { "AIF1 Slot 0 Right", NULL, "DACR" },
+};
+
+static int sun8i_codec_component_probe(struct snd_soc_component *component)
+{
+ struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
+ struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component);
+ int ret;
+
+ /* Add widgets for backward compatibility with old device trees. */
+ if (scodec->quirks->legacy_widgets) {
+ ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_legacy_widgets,
+ ARRAY_SIZE(sun8i_codec_legacy_widgets));
+ if (ret)
+ return ret;
+
+ ret = snd_soc_dapm_add_routes(dapm, sun8i_codec_legacy_routes,
+ ARRAY_SIZE(sun8i_codec_legacy_routes));
+ if (ret)
+ return ret;
+ }
+
+ /*
+ * AIF1CLK and AIF2CLK share a pair of clock parents: PLL_AUDIO ("mod")
+ * and MCLK (from the CPU DAI connected to AIF1). MCLK's parent is also
+ * PLL_AUDIO, so using it adds no additional flexibility. Use PLL_AUDIO
+ * directly to simplify the clock tree.
+ */
+ regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL,
+ SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK |
+ SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK,
+ SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL |
+ SUN8I_SYSCLK_CTL_AIF2CLK_SRC_PLL);
+
+ /* Use AIF1CLK as the SYSCLK parent since AIF1 is used most often. */
+ regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL,
+ BIT(SUN8I_SYSCLK_CTL_SYSCLK_SRC),
+ SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF1CLK);
+
+ /* Program the default sample rate. */
+ sun8i_codec_update_sample_rate(scodec);
+
+ return 0;
+}
+
+static const struct snd_soc_component_driver sun8i_soc_component = {
+ .controls = sun8i_codec_controls,
+ .num_controls = ARRAY_SIZE(sun8i_codec_controls),
+ .dapm_widgets = sun8i_codec_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets),
+ .dapm_routes = sun8i_codec_dapm_routes,
+ .num_dapm_routes = ARRAY_SIZE(sun8i_codec_dapm_routes),
+ .probe = sun8i_codec_component_probe,
+ .idle_bias_on = 1,
+ .endianness = 1,
+};
+
+static const struct regmap_config sun8i_codec_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = SUN8I_DAC_MXR_SRC,
+
+ .cache_type = REGCACHE_FLAT,
+};
+
+static int sun8i_codec_probe(struct platform_device *pdev)
+{
+ struct sun8i_codec *scodec;
+ void __iomem *base;
+ int ret;
+
+ scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
+ if (!scodec)
+ return -ENOMEM;
+
+ scodec->clk_module = devm_clk_get(&pdev->dev, "mod");
+ if (IS_ERR(scodec->clk_module)) {
+ dev_err(&pdev->dev, "Failed to get the module clock\n");
+ return PTR_ERR(scodec->clk_module);
+ }
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base)) {
+ dev_err(&pdev->dev, "Failed to map the registers\n");
+ return PTR_ERR(base);
+ }
+
+ scodec->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "bus", base,
+ &sun8i_codec_regmap_config);
+ if (IS_ERR(scodec->regmap)) {
+ dev_err(&pdev->dev, "Failed to create our regmap\n");
+ return PTR_ERR(scodec->regmap);
+ }
+
+ scodec->quirks = of_device_get_match_data(&pdev->dev);
+
+ platform_set_drvdata(pdev, scodec);
+
+ pm_runtime_enable(&pdev->dev);
+ if (!pm_runtime_enabled(&pdev->dev)) {
+ ret = sun8i_codec_runtime_resume(&pdev->dev);
+ if (ret)
+ goto err_pm_disable;
+ }
+
+ ret = devm_snd_soc_register_component(&pdev->dev, &sun8i_soc_component,
+ sun8i_codec_dais,
+ ARRAY_SIZE(sun8i_codec_dais));
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to register codec\n");
+ goto err_suspend;
+ }
+
+ return ret;
+
+err_suspend:
+ if (!pm_runtime_status_suspended(&pdev->dev))
+ sun8i_codec_runtime_suspend(&pdev->dev);
+
+err_pm_disable:
+ pm_runtime_disable(&pdev->dev);
+
+ return ret;
+}
+
+static void sun8i_codec_remove(struct platform_device *pdev)
+{
+ pm_runtime_disable(&pdev->dev);
+ if (!pm_runtime_status_suspended(&pdev->dev))
+ sun8i_codec_runtime_suspend(&pdev->dev);
+}
+
+static const struct sun8i_codec_quirks sun8i_a33_quirks = {
+ .legacy_widgets = true,
+ .lrck_inversion = true,
+};
+
+static const struct sun8i_codec_quirks sun50i_a64_quirks = {
+};
+
+static const struct of_device_id sun8i_codec_of_match[] = {
+ { .compatible = "allwinner,sun8i-a33-codec", .data = &sun8i_a33_quirks },
+ { .compatible = "allwinner,sun50i-a64-codec", .data = &sun50i_a64_quirks },
+ {}
+};
+MODULE_DEVICE_TABLE(of, sun8i_codec_of_match);
+
+static const struct dev_pm_ops sun8i_codec_pm_ops = {
+ SET_RUNTIME_PM_OPS(sun8i_codec_runtime_suspend,
+ sun8i_codec_runtime_resume, NULL)
+};
+
+static struct platform_driver sun8i_codec_driver = {
+ .driver = {
+ .name = "sun8i-codec",
+ .of_match_table = sun8i_codec_of_match,
+ .pm = &sun8i_codec_pm_ops,
+ },
+ .probe = sun8i_codec_probe,
+ .remove_new = sun8i_codec_remove,
+};
+module_platform_driver(sun8i_codec_driver);
+
+MODULE_DESCRIPTION("Allwinner A33 (sun8i) codec driver");
+MODULE_AUTHOR("Mylène Josserand <mylene.josserand@free-electrons.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:sun8i-codec");
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-05 06:56:10 +0000