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-rw-r--r--tools/perf/tests/pmu-events.c22
1 files changed, 11 insertions, 11 deletions
diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c
index a56d329057..47a7c32775 100644
--- a/tools/perf/tests/pmu-events.c
+++ b/tools/perf/tests/pmu-events.c
@@ -70,7 +70,7 @@ static const struct perf_pmu_test_event segment_reg_loads_any = {
.event = {
.pmu = "default_core",
.name = "segment_reg_loads.any",
- .event = "event=0x6,period=200000,umask=0x80",
+ .event = "event=6,period=200000,umask=0x80",
.desc = "Number of segment register loads",
.topic = "other",
},
@@ -82,7 +82,7 @@ static const struct perf_pmu_test_event dispatch_blocked_any = {
.event = {
.pmu = "default_core",
.name = "dispatch_blocked.any",
- .event = "event=0x9,period=200000,umask=0x20",
+ .event = "event=9,period=200000,umask=0x20",
.desc = "Memory cluster signals to block micro-op dispatch for any reason",
.topic = "other",
},
@@ -94,11 +94,11 @@ static const struct perf_pmu_test_event eist_trans = {
.event = {
.pmu = "default_core",
.name = "eist_trans",
- .event = "event=0x3a,period=200000,umask=0x0",
+ .event = "event=0x3a,period=200000",
.desc = "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
.topic = "other",
},
- .alias_str = "event=0x3a,period=0x30d40,umask=0",
+ .alias_str = "event=0x3a,period=0x30d40",
.alias_long_desc = "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
};
@@ -128,7 +128,7 @@ static const struct perf_pmu_test_event *core_events[] = {
static const struct perf_pmu_test_event uncore_hisi_ddrc_flux_wcmd = {
.event = {
.name = "uncore_hisi_ddrc.flux_wcmd",
- .event = "event=0x2",
+ .event = "event=2",
.desc = "DDRC write commands",
.topic = "uncore",
.long_desc = "DDRC write commands",
@@ -156,13 +156,13 @@ static const struct perf_pmu_test_event unc_cbo_xsnp_response_miss_eviction = {
static const struct perf_pmu_test_event uncore_hyphen = {
.event = {
.name = "event-hyphen",
- .event = "event=0xe0,umask=0x00",
+ .event = "event=0xe0",
.desc = "UNC_CBO_HYPHEN",
.topic = "uncore",
.long_desc = "UNC_CBO_HYPHEN",
.pmu = "uncore_cbox",
},
- .alias_str = "event=0xe0,umask=0",
+ .alias_str = "event=0xe0",
.alias_long_desc = "UNC_CBO_HYPHEN",
.matching_pmu = "uncore_cbox_0",
};
@@ -170,13 +170,13 @@ static const struct perf_pmu_test_event uncore_hyphen = {
static const struct perf_pmu_test_event uncore_two_hyph = {
.event = {
.name = "event-two-hyph",
- .event = "event=0xc0,umask=0x00",
+ .event = "event=0xc0",
.desc = "UNC_CBO_TWO_HYPH",
.topic = "uncore",
.long_desc = "UNC_CBO_TWO_HYPH",
.pmu = "uncore_cbox",
},
- .alias_str = "event=0xc0,umask=0",
+ .alias_str = "event=0xc0",
.alias_long_desc = "UNC_CBO_TWO_HYPH",
.matching_pmu = "uncore_cbox_0",
};
@@ -184,7 +184,7 @@ static const struct perf_pmu_test_event uncore_two_hyph = {
static const struct perf_pmu_test_event uncore_hisi_l3c_rd_hit_cpipe = {
.event = {
.name = "uncore_hisi_l3c.rd_hit_cpipe",
- .event = "event=0x7",
+ .event = "event=7",
.desc = "Total read hits",
.topic = "uncore",
.long_desc = "Total read hits",
@@ -265,7 +265,7 @@ static const struct perf_pmu_test_event sys_ccn_pmu_read_cycles = {
static const struct perf_pmu_test_event sys_cmn_pmu_hnf_cache_miss = {
.event = {
.name = "sys_cmn_pmu.hnf_cache_miss",
- .event = "eventid=0x1,type=0x5",
+ .event = "eventid=1,type=5",
.desc = "Counts total cache misses in first lookup result (high priority)",
.topic = "uncore",
.pmu = "uncore_sys_cmn_pmu",