From e54def4ad8144ab15f826416e2e0f290ef1901b4 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Wed, 19 Jun 2024 23:00:30 +0200 Subject: Adding upstream version 6.9.2. Signed-off-by: Daniel Baumann --- .../bindings/clock/mediatek,mt2701-hifsys.yaml | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt2701-hifsys.yaml (limited to 'Documentation/devicetree/bindings/clock/mediatek,mt2701-hifsys.yaml') diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt2701-hifsys.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt2701-hifsys.yaml new file mode 100644 index 0000000000..9e7c725093 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt2701-hifsys.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt2701-hifsys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek HIFSYS clock and reset controller + +description: + The MediaTek HIFSYS controller provides various clocks and reset outputs to + the system. + +maintainers: + - Matthias Brugger + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt2701-hifsys + - mediatek,mt7622-hifsys + - items: + - enum: + - mediatek,mt7623-hifsys + - const: mediatek,mt2701-hifsys + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + description: The available clocks are defined in dt-bindings/clock/mt*-clk.h + + "#reset-cells": + const: 1 + +required: + - reg + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clock-controller@1a000000 { + compatible = "mediatek,mt2701-hifsys"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; -- cgit v1.2.3