From ace9429bb58fd418f0c81d4c2835699bddf6bde6 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Thu, 11 Apr 2024 10:27:49 +0200 Subject: Adding upstream version 6.6.15. Signed-off-by: Daniel Baumann --- .../devicetree/bindings/serial/samsung_uart.yaml | 145 +++++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/samsung_uart.yaml (limited to 'Documentation/devicetree/bindings/serial/samsung_uart.yaml') diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml new file mode 100644 index 0000000000..8bd88d5cbb --- /dev/null +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -0,0 +1,145 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/samsung_uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller + +maintainers: + - Krzysztof Kozlowski + - Greg Kroah-Hartman + +description: |+ + Each Samsung UART should have an alias correctly numbered in the "aliases" + node, according to serialN format, where N is the port number (non-negative + decimal integer) as specified by User's Manual of respective SoC. + +properties: + compatible: + oneOf: + - items: + - const: samsung,exynosautov9-uart + - const: samsung,exynos850-uart + - enum: + - apple,s5l-uart + - axis,artpec8-uart + - samsung,s3c2410-uart + - samsung,s3c2412-uart + - samsung,s3c2440-uart + - samsung,s3c6400-uart + - samsung,s5pv210-uart + - samsung,exynos4210-uart + - samsung,exynos5433-uart + - samsung,exynos850-uart + + reg: + maxItems: 1 + + reg-io-width: + description: | + The size (in bytes) of the IO accesses that should be performed + on the device. + enum: [ 1, 4 ] + + clocks: + minItems: 2 + maxItems: 5 + + clock-names: + description: N = 0 is allowed for SoCs without internal baud clock mux. + minItems: 2 + items: + - const: uart + - pattern: '^clk_uart_baud[0-3]$' + - pattern: '^clk_uart_baud[0-3]$' + - pattern: '^clk_uart_baud[0-3]$' + - pattern: '^clk_uart_baud[0-3]$' + + dmas: + items: + - description: DMA controller phandle and request line for RX + - description: DMA controller phandle and request line for TX + + dma-names: + items: + - const: rx + - const: tx + + interrupts: + description: RX interrupt and optionally TX interrupt. + minItems: 1 + maxItems: 2 + + power-domains: + maxItems: 1 + + samsung,uart-fifosize: + description: The fifo size supported by the UART channel. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [16, 64, 256] + +required: + - compatible + - clocks + - clock-names + - interrupts + - reg + +unevaluatedProperties: false + +allOf: + - $ref: serial.yaml# + + - if: + properties: + compatible: + contains: + enum: + - samsung,s3c2410-uart + - samsung,s5pv210-uart + then: + properties: + clocks: + minItems: 2 + maxItems: 3 + clock-names: + minItems: 2 + items: + - const: uart + - pattern: '^clk_uart_baud[0-1]$' + - pattern: '^clk_uart_baud[0-1]$' + + - if: + properties: + compatible: + contains: + enum: + - apple,s5l-uart + - axis,artpec8-uart + - samsung,exynos4210-uart + - samsung,exynos5433-uart + then: + properties: + clocks: + maxItems: 2 + clock-names: + items: + - const: uart + - const: clk_uart_baud0 + +examples: + - | + #include + + uart0: serial@7f005000 { + compatible = "samsung,s3c6400-uart"; + reg = <0x7f005000 0x100>; + interrupt-parent = <&vic1>; + interrupts = <5>; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, + <&clocks SCLK_UART>; + samsung,uart-fifosize = <16>; + }; -- cgit v1.2.3