From b20732900e4636a467c0183a47f7396700f5f743 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Wed, 7 Aug 2024 15:11:22 +0200 Subject: Adding upstream version 6.9.7. Signed-off-by: Daniel Baumann --- .../devicetree/bindings/soc/qcom/qcom,pbs.yaml | 46 ++++++++ .../bindings/soc/qcom/qcom,pmic-glink.yaml | 3 + .../bindings/soc/qcom/qcom,rpm-master-stats.yaml | 2 + .../devicetree/bindings/soc/qcom/qcom,saw2.yaml | 119 +++++++++++++++++++++ .../devicetree/bindings/soc/qcom/qcom,spm.yaml | 85 --------------- 5 files changed, 170 insertions(+), 85 deletions(-) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,pbs.yaml create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml delete mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml (limited to 'Documentation/devicetree/bindings/soc/qcom') diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pbs.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pbs.yaml new file mode 100644 index 0000000000..b502ca7226 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pbs.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,pbs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Programmable Boot Sequencer + +maintainers: + - Anjelique Melendez + +description: | + The Qualcomm Technologies, Inc. Programmable Boot Sequencer (PBS) + supports triggering power up and power down sequences for clients + upon request. + +properties: + compatible: + items: + - enum: + - qcom,pmi632-pbs + - const: qcom,pbs + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pmic@0 { + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pbs@7400 { + compatible = "qcom,pmi632-pbs", "qcom,pbs"; + reg = <0x7400>; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index 61df97ffe1..4310bae6c5 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -23,6 +23,7 @@ properties: oneOf: - items: - enum: + - qcom,qcm6490-pmic-glink - qcom,sc8180x-pmic-glink - qcom,sc8280xp-pmic-glink - qcom,sm8350-pmic-glink @@ -32,6 +33,7 @@ properties: - items: - enum: - qcom,sm8650-pmic-glink + - qcom,x1e80100-pmic-glink - const: qcom,sm8550-pmic-glink - const: qcom,pmic-glink @@ -65,6 +67,7 @@ allOf: enum: - qcom,sm8450-pmic-glink - qcom,sm8550-pmic-glink + - qcom,x1e80100-pmic-glink then: properties: orientation-gpios: false diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpm-master-stats.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpm-master-stats.yaml index 031800985b..9410404f87 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,rpm-master-stats.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpm-master-stats.yaml @@ -35,6 +35,8 @@ properties: description: Phandle to an RPM MSG RAM slice containing the master stats minItems: 1 maxItems: 5 + items: + maxItems: 1 qcom,master-names: $ref: /schemas/types.yaml#/definitions/string-array diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml new file mode 100644 index 0000000000..ca4bce8172 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,saw2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Subsystem Power Manager / SPM AVS Wrapper 2 (SAW2) + +maintainers: + - Andy Gross + - Bjorn Andersson + +description: | + The Qualcomm Subsystem Power Manager is used to control the peripheral logic + surrounding the application cores in Qualcomm platforms. + + The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the + Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable + power-controller that transitions a piece of hardware (like a processor or + subsystem) into and out of low power modes via a direct connection to + the PMIC. It can also be wired up to interact with other processors in the + system, notifying them when a low power state is entered or exited. + +properties: + compatible: + items: + - enum: + - qcom,ipq4019-saw2-cpu + - qcom,ipq4019-saw2-l2 + - qcom,ipq8064-saw2-cpu + - qcom,sdm660-gold-saw2-v4.1-l2 + - qcom,sdm660-silver-saw2-v4.1-l2 + - qcom,msm8998-gold-saw2-v4.1-l2 + - qcom,msm8998-silver-saw2-v4.1-l2 + - qcom,msm8909-saw2-v3.0-cpu + - qcom,msm8916-saw2-v3.0-cpu + - qcom,msm8939-saw2-v3.0-cpu + - qcom,msm8226-saw2-v2.1-cpu + - qcom,msm8226-saw2-v2.1-l2 + - qcom,msm8960-saw2-cpu + - qcom,msm8974-saw2-v2.1-cpu + - qcom,msm8974-saw2-v2.1-l2 + - qcom,msm8976-gold-saw2-v2.3-l2 + - qcom,msm8976-silver-saw2-v2.3-l2 + - qcom,apq8084-saw2-v2.1-cpu + - qcom,apq8084-saw2-v2.1-l2 + - qcom,apq8064-saw2-v1.1-cpu + - const: qcom,saw2 + + reg: + items: + - description: Base address and size of the SPM register region + - description: Base address and size of the alias register region + minItems: 1 + + regulator: + $ref: /schemas/regulator/regulator.yaml# + description: Indicates that this SPM device acts as a regulator device + device for the core (CPU or Cache) the SPM is attached to. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + + /* Example 1: SoC using SAW2 and kpss-acc-v2 CPUIdle */ + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "qcom,kryo"; + device_type = "cpu"; + enable-method = "qcom,kpss-acc-v2"; + qcom,saw = <&saw0>; + reg = <0x0>; + operating-points-v2 = <&cpu_opp_table>; + }; + }; + + saw0: power-manager@f9089000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9089000 0x1000>; + }; + + - | + + /* + * Example 2: New-gen multi cluster SoC using SAW only for L2; + * This does not require any cpuidle driver, nor any cpu phandle. + */ + power-manager@17812000 { + compatible = "qcom,msm8998-gold-saw2-v4.1-l2", "qcom,saw2"; + reg = <0x17812000 0x1000>; + }; + + power-manager@17912000 { + compatible = "qcom,msm8998-silver-saw2-v4.1-l2", "qcom,saw2"; + reg = <0x17912000 0x1000>; + }; + + - | + /* + * Example 3: SAW2 with the bundled regulator definition. + */ + power-manager@2089000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + + regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml deleted file mode 100644 index 20c8cd38ff..0000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml +++ /dev/null @@ -1,85 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm Subsystem Power Manager - -maintainers: - - Andy Gross - - Bjorn Andersson - -description: | - This binding describes the Qualcomm Subsystem Power Manager, used to control - the peripheral logic surrounding the application cores in Qualcomm platforms. - -properties: - compatible: - items: - - enum: - - qcom,sdm660-gold-saw2-v4.1-l2 - - qcom,sdm660-silver-saw2-v4.1-l2 - - qcom,msm8998-gold-saw2-v4.1-l2 - - qcom,msm8998-silver-saw2-v4.1-l2 - - qcom,msm8909-saw2-v3.0-cpu - - qcom,msm8916-saw2-v3.0-cpu - - qcom,msm8939-saw2-v3.0-cpu - - qcom,msm8226-saw2-v2.1-cpu - - qcom,msm8974-saw2-v2.1-cpu - - qcom,msm8976-gold-saw2-v2.3-l2 - - qcom,msm8976-silver-saw2-v2.3-l2 - - qcom,apq8084-saw2-v2.1-cpu - - qcom,apq8064-saw2-v1.1-cpu - - const: qcom,saw2 - - reg: - description: Base address and size of the SPM register region - maxItems: 1 - -required: - - compatible - - reg - -additionalProperties: false - -examples: - - | - - /* Example 1: SoC using SAW2 and kpss-acc-v2 CPUIdle */ - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "qcom,kryo"; - device_type = "cpu"; - enable-method = "qcom,kpss-acc-v2"; - qcom,saw = <&saw0>; - reg = <0x0>; - operating-points-v2 = <&cpu_opp_table>; - }; - }; - - saw0: power-manager@f9089000 { - compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9089000 0x1000>; - }; - - - | - - /* - * Example 2: New-gen multi cluster SoC using SAW only for L2; - * This does not require any cpuidle driver, nor any cpu phandle. - */ - power-manager@17812000 { - compatible = "qcom,msm8998-gold-saw2-v4.1-l2", "qcom,saw2"; - reg = <0x17812000 0x1000>; - }; - - power-manager@17912000 { - compatible = "qcom,msm8998-silver-saw2-v4.1-l2", "qcom,saw2"; - reg = <0x17912000 0x1000>; - }; - -... -- cgit v1.2.3