From ace9429bb58fd418f0c81d4c2835699bddf6bde6 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Thu, 11 Apr 2024 10:27:49 +0200 Subject: Adding upstream version 6.6.15. Signed-off-by: Daniel Baumann --- arch/arm/boot/dts/microchip/sama5d3_can.dtsi | 57 ++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 arch/arm/boot/dts/microchip/sama5d3_can.dtsi (limited to 'arch/arm/boot/dts/microchip/sama5d3_can.dtsi') diff --git a/arch/arm/boot/dts/microchip/sama5d3_can.dtsi b/arch/arm/boot/dts/microchip/sama5d3_can.dtsi new file mode 100644 index 0000000000..9ac29bf3f9 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama5d3_can.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with + * CAN support + * + * Copyright (C) 2013 Boris BREZILLON + */ + +#include +#include + +/ { + ahb { + apb { + pinctrl@fffff200 { + can0 { + pinctrl_can0_rx_tx: can0_rx_tx { + atmel,pins = + ; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ + }; + }; + + can1 { + pinctrl_can1_rx_tx: can1_rx_tx { + atmel,pins = + ; /* PB15 periph B TX, conflicts with GCOL */ + }; + }; + + }; + + can0: can@f000c000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf000c000 0x300>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_rx_tx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; + clock-names = "can_clk"; + status = "disabled"; + }; + + can1: can@f8010000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf8010000 0x300>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_rx_tx>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; + clock-names = "can_clk"; + status = "disabled"; + }; + }; + }; +}; -- cgit v1.2.3