From ace9429bb58fd418f0c81d4c2835699bddf6bde6 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Thu, 11 Apr 2024 10:27:49 +0200 Subject: Adding upstream version 6.6.15. Signed-off-by: Daniel Baumann --- arch/arm/mach-mediatek/Kconfig | 43 ++++++++++++ arch/arm/mach-mediatek/Makefile | 3 + arch/arm/mach-mediatek/mediatek.c | 53 ++++++++++++++ arch/arm/mach-mediatek/platsmp.c | 143 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 242 insertions(+) create mode 100644 arch/arm/mach-mediatek/Kconfig create mode 100644 arch/arm/mach-mediatek/Makefile create mode 100644 arch/arm/mach-mediatek/mediatek.c create mode 100644 arch/arm/mach-mediatek/platsmp.c (limited to 'arch/arm/mach-mediatek') diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig new file mode 100644 index 0000000000..35a3430c79 --- /dev/null +++ b/arch/arm/mach-mediatek/Kconfig @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0-only +menuconfig ARCH_MEDIATEK + bool "MediaTek SoC Support" + depends on ARCH_MULTI_V7 + select ARM_GIC + select PINCTRL + select MTK_TIMER + select MFD_SYSCON + help + Support for Mediatek MT65xx & MT81xx SoCs + +if ARCH_MEDIATEK + +config MACH_MT2701 + bool "MediaTek MT2701 SoCs support" + default ARCH_MEDIATEK + +config MACH_MT6589 + bool "MediaTek MT6589 SoCs support" + default ARCH_MEDIATEK + +config MACH_MT6592 + bool "MediaTek MT6592 SoCs support" + default ARCH_MEDIATEK + +config MACH_MT7623 + bool "MediaTek MT7623 SoCs support" + default ARCH_MEDIATEK + +config MACH_MT7629 + bool "MediaTek MT7629 SoCs support" + default ARCH_MEDIATEK + select HAVE_ARM_ARCH_TIMER + +config MACH_MT8127 + bool "MediaTek MT8127 SoCs support" + default ARCH_MEDIATEK + +config MACH_MT8135 + bool "MediaTek MT8135 SoCs support" + default ARCH_MEDIATEK + +endif diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile new file mode 100644 index 0000000000..90e08a4222 --- /dev/null +++ b/arch/arm/mach-mediatek/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_SMP) += platsmp.o +obj-y += mediatek.o diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c new file mode 100644 index 0000000000..e6e9f93a1f --- /dev/null +++ b/arch/arm/mach-mediatek/mediatek.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Device Tree support for Mediatek SoCs + * + * Copyright (c) 2014 MundoReader S.L. + * Author: Matthias Brugger + */ +#include +#include +#include +#include +#include +#include + + +#define GPT6_CON_MT65xx 0x10008060 +#define GPT_ENABLE 0x31 + +static void __init mediatek_timer_init(void) +{ + void __iomem *gpt_base; + + if (of_machine_is_compatible("mediatek,mt6589") || + of_machine_is_compatible("mediatek,mt7623") || + of_machine_is_compatible("mediatek,mt8135") || + of_machine_is_compatible("mediatek,mt8127")) { + /* turn on GPT6 which ungates arch timer clocks */ + gpt_base = ioremap(GPT6_CON_MT65xx, 0x04); + + /* enable clock and set to free-run */ + writel(GPT_ENABLE, gpt_base); + iounmap(gpt_base); + } + + of_clk_init(NULL); + timer_probe(); +}; + +static const char * const mediatek_board_dt_compat[] = { + "mediatek,mt2701", + "mediatek,mt6589", + "mediatek,mt6592", + "mediatek,mt7623", + "mediatek,mt7629", + "mediatek,mt8127", + "mediatek,mt8135", + NULL, +}; + +DT_MACHINE_START(MEDIATEK_DT, "Mediatek Cortex-A7 (Device Tree)") + .dt_compat = mediatek_board_dt_compat, + .init_time = mediatek_timer_init, +MACHINE_END diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c new file mode 100644 index 0000000000..16a4ee6c95 --- /dev/null +++ b/arch/arm/mach-mediatek/platsmp.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * arch/arm/mach-mediatek/platsmp.c + * + * Copyright (c) 2014 Mediatek Inc. + * Author: Shunli Wang + * Yingjoe Chen + */ +#include +#include +#include +#include +#include +#include + +#define MTK_MAX_CPU 8 +#define MTK_SMP_REG_SIZE 0x1000 + +struct mtk_smp_boot_info { + unsigned long smp_base; + unsigned int jump_reg; + unsigned int core_keys[MTK_MAX_CPU - 1]; + unsigned int core_regs[MTK_MAX_CPU - 1]; +}; + +static const struct mtk_smp_boot_info mtk_mt8135_tz_boot = { + 0x80002000, 0x3fc, + { 0x534c4131, 0x4c415332, 0x41534c33 }, + { 0x3f8, 0x3f8, 0x3f8 }, +}; + +static const struct mtk_smp_boot_info mtk_mt6589_boot = { + 0x10002000, 0x34, + { 0x534c4131, 0x4c415332, 0x41534c33 }, + { 0x38, 0x3c, 0x40 }, +}; + +static const struct mtk_smp_boot_info mtk_mt7623_boot = { + 0x10202000, 0x34, + { 0x534c4131, 0x4c415332, 0x41534c33 }, + { 0x38, 0x3c, 0x40 }, +}; + +static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = { + { .compatible = "mediatek,mt8135", .data = &mtk_mt8135_tz_boot }, + { .compatible = "mediatek,mt8127", .data = &mtk_mt8135_tz_boot }, + { .compatible = "mediatek,mt2701", .data = &mtk_mt8135_tz_boot }, + {}, +}; + +static const struct of_device_id mtk_smp_boot_infos[] __initconst = { + { .compatible = "mediatek,mt6589", .data = &mtk_mt6589_boot }, + { .compatible = "mediatek,mt7623", .data = &mtk_mt7623_boot }, + { .compatible = "mediatek,mt7629", .data = &mtk_mt7623_boot }, + {}, +}; + +static void __iomem *mtk_smp_base; +static const struct mtk_smp_boot_info *mtk_smp_info; + +static int mtk_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + if (!mtk_smp_base) + return -EINVAL; + + if (!mtk_smp_info->core_keys[cpu-1]) + return -EINVAL; + + writel_relaxed(mtk_smp_info->core_keys[cpu-1], + mtk_smp_base + mtk_smp_info->core_regs[cpu-1]); + + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + + return 0; +} + +static void __init __mtk_smp_prepare_cpus(unsigned int max_cpus, int trustzone) +{ + int i, num; + const struct of_device_id *infos; + + if (trustzone) { + num = ARRAY_SIZE(mtk_tz_smp_boot_infos); + infos = mtk_tz_smp_boot_infos; + } else { + num = ARRAY_SIZE(mtk_smp_boot_infos); + infos = mtk_smp_boot_infos; + } + + /* Find smp boot info for this SoC */ + for (i = 0; i < num; i++) { + if (of_machine_is_compatible(infos[i].compatible)) { + mtk_smp_info = infos[i].data; + break; + } + } + + if (!mtk_smp_info) { + pr_err("%s: Device is not supported\n", __func__); + return; + } + + if (trustzone) { + /* smp_base(trustzone-bootinfo) is reserved by device tree */ + mtk_smp_base = phys_to_virt(mtk_smp_info->smp_base); + } else { + mtk_smp_base = ioremap(mtk_smp_info->smp_base, MTK_SMP_REG_SIZE); + if (!mtk_smp_base) { + pr_err("%s: Can't remap %lx\n", __func__, + mtk_smp_info->smp_base); + return; + } + } + + /* + * write the address of slave startup address into the system-wide + * jump register + */ + writel_relaxed(__pa_symbol(secondary_startup_arm), + mtk_smp_base + mtk_smp_info->jump_reg); +} + +static void __init mtk_tz_smp_prepare_cpus(unsigned int max_cpus) +{ + __mtk_smp_prepare_cpus(max_cpus, 1); +} + +static void __init mtk_smp_prepare_cpus(unsigned int max_cpus) +{ + __mtk_smp_prepare_cpus(max_cpus, 0); +} + +static const struct smp_operations mt81xx_tz_smp_ops __initconst = { + .smp_prepare_cpus = mtk_tz_smp_prepare_cpus, + .smp_boot_secondary = mtk_boot_secondary, +}; +CPU_METHOD_OF_DECLARE(mt81xx_tz_smp, "mediatek,mt81xx-tz-smp", &mt81xx_tz_smp_ops); + +static const struct smp_operations mt6589_smp_ops __initconst = { + .smp_prepare_cpus = mtk_smp_prepare_cpus, + .smp_boot_secondary = mtk_boot_secondary, +}; +CPU_METHOD_OF_DECLARE(mt6589_smp, "mediatek,mt6589-smp", &mt6589_smp_ops); -- cgit v1.2.3