From ace9429bb58fd418f0c81d4c2835699bddf6bde6 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Thu, 11 Apr 2024 10:27:49 +0200 Subject: Adding upstream version 6.6.15. Signed-off-by: Daniel Baumann --- drivers/fpga/altera-pr-ip-core-plat.c | 46 +++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 drivers/fpga/altera-pr-ip-core-plat.c (limited to 'drivers/fpga/altera-pr-ip-core-plat.c') diff --git a/drivers/fpga/altera-pr-ip-core-plat.c b/drivers/fpga/altera-pr-ip-core-plat.c new file mode 100644 index 0000000000..9dc2639300 --- /dev/null +++ b/drivers/fpga/altera-pr-ip-core-plat.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for Altera Partial Reconfiguration IP Core + * + * Copyright (C) 2016-2017 Intel Corporation + * + * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation + * by Alan Tull + */ +#include +#include +#include +#include + +static int alt_pr_platform_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + void __iomem *reg_base; + + /* First mmio base is for register access */ + reg_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reg_base)) + return PTR_ERR(reg_base); + + return alt_pr_register(dev, reg_base); +} + +static const struct of_device_id alt_pr_of_match[] = { + { .compatible = "altr,a10-pr-ip", }, + {}, +}; + +MODULE_DEVICE_TABLE(of, alt_pr_of_match); + +static struct platform_driver alt_pr_platform_driver = { + .probe = alt_pr_platform_probe, + .driver = { + .name = "alt_a10_pr_ip", + .of_match_table = alt_pr_of_match, + }, +}; + +module_platform_driver(alt_pr_platform_driver); +MODULE_AUTHOR("Matthew Gerlach "); +MODULE_DESCRIPTION("Altera Partial Reconfiguration IP Platform Driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3