From 85c675d0d09a45a135bddd15d7b385f8758c32fb Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sat, 18 May 2024 19:35:05 +0200 Subject: Adding upstream version 6.7.7. Signed-off-by: Daniel Baumann --- drivers/iio/imu/adis16475.c | 238 ++++++++++++++++++++++++----- drivers/iio/imu/bno055/Kconfig | 1 + drivers/iio/imu/inv_mpu6050/inv_mpu_aux.c | 13 ++ drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | 3 + drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h | 2 +- 5 files changed, 218 insertions(+), 39 deletions(-) (limited to 'drivers/iio/imu') diff --git a/drivers/iio/imu/adis16475.c b/drivers/iio/imu/adis16475.c index 6c81dc5bf2..64be656f0b 100644 --- a/drivers/iio/imu/adis16475.c +++ b/drivers/iio/imu/adis16475.c @@ -31,6 +31,12 @@ #define ADIS16475_REG_Y_ACCEL_L 0x14 #define ADIS16475_REG_Z_ACCEL_L 0x18 #define ADIS16475_REG_TEMP_OUT 0x1c +#define ADIS16475_REG_X_DELTANG_L 0x24 +#define ADIS16475_REG_Y_DELTANG_L 0x28 +#define ADIS16475_REG_Z_DELTANG_L 0x2C +#define ADIS16475_REG_X_DELTVEL_L 0x30 +#define ADIS16475_REG_Y_DELTVEL_L 0x34 +#define ADIS16475_REG_Z_DELTVEL_L 0x38 #define ADIS16475_REG_X_GYRO_BIAS_L 0x40 #define ADIS16475_REG_Y_GYRO_BIAS_L 0x44 #define ADIS16475_REG_Z_GYRO_BIAS_L 0x48 @@ -55,6 +61,7 @@ #define ADIS16475_REG_PROD_ID 0x72 #define ADIS16475_REG_SERIAL_NUM 0x74 #define ADIS16475_REG_FLASH_CNT 0x7c +#define ADIS16500_BURST_DATA_SEL_MASK BIT(8) #define ADIS16500_BURST32_MASK BIT(9) #define ADIS16500_BURST32(x) FIELD_PREP(ADIS16500_BURST32_MASK, x) /* number of data elements in burst mode */ @@ -65,6 +72,8 @@ #define ADIS16475_BURST_MAX_SPEED 1000000 #define ADIS16475_LSB_DEC_MASK 0 #define ADIS16475_LSB_FIR_MASK 1 +#define ADIS16500_BURST_DATA_SEL_0_CHN_MASK GENMASK(5, 0) +#define ADIS16500_BURST_DATA_SEL_1_CHN_MASK GENMASK(12, 7) enum { ADIS16475_SYNC_DIRECT = 1, @@ -84,16 +93,20 @@ struct adis16475_chip_info { const struct adis16475_sync *sync; const struct adis_data adis_data; const char *name; +#define ADIS16475_HAS_BURST32 BIT(0) +#define ADIS16475_HAS_BURST_DELTA_DATA BIT(1) + const long flags; u32 num_channels; u32 gyro_max_val; u32 gyro_max_scale; u32 accel_max_val; u32 accel_max_scale; u32 temp_scale; + u32 deltang_max_val; + u32 deltvel_max_val; u32 int_clk; u16 max_dec; u8 num_sync; - bool has_burst32; }; struct adis16475 { @@ -115,6 +128,12 @@ enum { ADIS16475_SCAN_ACCEL_Y, ADIS16475_SCAN_ACCEL_Z, ADIS16475_SCAN_TEMP, + ADIS16475_SCAN_DELTANG_X, + ADIS16475_SCAN_DELTANG_Y, + ADIS16475_SCAN_DELTANG_Z, + ADIS16475_SCAN_DELTVEL_X, + ADIS16475_SCAN_DELTVEL_Y, + ADIS16475_SCAN_DELTVEL_Z, }; static bool low_rate_allow; @@ -451,6 +470,14 @@ static int adis16475_read_raw(struct iio_dev *indio_dev, case IIO_TEMP: *val = st->info->temp_scale; return IIO_VAL_INT; + case IIO_DELTA_ANGL: + *val = st->info->deltang_max_val; + *val2 = 31; + return IIO_VAL_FRACTIONAL_LOG2; + case IIO_DELTA_VELOCITY: + *val = st->info->deltvel_max_val; + *val2 = 31; + return IIO_VAL_FRACTIONAL_LOG2; default: return -EINVAL; } @@ -551,6 +578,57 @@ static int adis16475_write_raw(struct iio_dev *indio_dev, }, \ } +#define ADIS16475_MOD_CHAN_DELTA(_type, _mod, _address, _si, _r_bits, _s_bits) { \ + .type = (_type), \ + .modified = 1, \ + .channel2 = (_mod), \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ + .address = (_address), \ + .scan_index = _si, \ + .scan_type = { \ + .sign = 's', \ + .realbits = (_r_bits), \ + .storagebits = (_s_bits), \ + .endianness = IIO_BE, \ + }, \ + } + +#define ADIS16475_DELTANG_CHAN(_mod) \ + ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \ + ADIS16475_REG_ ## _mod ## _DELTANG_L, ADIS16475_SCAN_DELTANG_ ## _mod, 32, 32) + +#define ADIS16475_DELTVEL_CHAN(_mod) \ + ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \ + ADIS16475_REG_ ## _mod ## _DELTVEL_L, ADIS16475_SCAN_DELTVEL_ ## _mod, 32, 32) + +#define ADIS16475_DELTANG_CHAN_NO_SCAN(_mod) \ + ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \ + ADIS16475_REG_ ## _mod ## _DELTANG_L, -1, 32, 32) + +#define ADIS16475_DELTVEL_CHAN_NO_SCAN(_mod) \ + ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \ + ADIS16475_REG_ ## _mod ## _DELTVEL_L, -1, 32, 32) + +static const struct iio_chan_spec adis16477_channels[] = { + ADIS16475_GYRO_CHANNEL(X), + ADIS16475_GYRO_CHANNEL(Y), + ADIS16475_GYRO_CHANNEL(Z), + ADIS16475_ACCEL_CHANNEL(X), + ADIS16475_ACCEL_CHANNEL(Y), + ADIS16475_ACCEL_CHANNEL(Z), + ADIS16475_TEMP_CHANNEL(), + ADIS16475_DELTANG_CHAN(X), + ADIS16475_DELTANG_CHAN(Y), + ADIS16475_DELTANG_CHAN(Z), + ADIS16475_DELTVEL_CHAN(X), + ADIS16475_DELTVEL_CHAN(Y), + ADIS16475_DELTVEL_CHAN(Z), + IIO_CHAN_SOFT_TIMESTAMP(13) +}; + static const struct iio_chan_spec adis16475_channels[] = { ADIS16475_GYRO_CHANNEL(X), ADIS16475_GYRO_CHANNEL(Y), @@ -559,6 +637,12 @@ static const struct iio_chan_spec adis16475_channels[] = { ADIS16475_ACCEL_CHANNEL(Y), ADIS16475_ACCEL_CHANNEL(Z), ADIS16475_TEMP_CHANNEL(), + ADIS16475_DELTANG_CHAN_NO_SCAN(X), + ADIS16475_DELTANG_CHAN_NO_SCAN(Y), + ADIS16475_DELTANG_CHAN_NO_SCAN(Z), + ADIS16475_DELTVEL_CHAN_NO_SCAN(X), + ADIS16475_DELTVEL_CHAN_NO_SCAN(Y), + ADIS16475_DELTVEL_CHAN_NO_SCAN(Z), IIO_CHAN_SOFT_TIMESTAMP(7) }; @@ -662,6 +746,8 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .accel_max_val = 1, .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(2160), + .deltvel_max_val = 400, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, @@ -677,6 +763,8 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .accel_max_val = 1, .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(360), + .deltvel_max_val = 100, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, @@ -692,6 +780,8 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .accel_max_val = 1, .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(720), + .deltvel_max_val = 100, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, @@ -707,6 +797,8 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .accel_max_val = 1, .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(2160), + .deltvel_max_val = 100, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, @@ -715,50 +807,56 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { }, [ADIS16477_1] = { .name = "adis16477-1", - .num_channels = ARRAY_SIZE(adis16475_channels), - .channels = adis16475_channels, + .num_channels = ARRAY_SIZE(adis16477_channels), + .channels = adis16477_channels, .gyro_max_val = 1, .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), .accel_max_val = 1, .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(360), + .deltvel_max_val = 400, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, .num_sync = ARRAY_SIZE(adis16475_sync_mode), - .has_burst32 = true, + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), }, [ADIS16477_2] = { .name = "adis16477-2", - .num_channels = ARRAY_SIZE(adis16475_channels), - .channels = adis16475_channels, + .num_channels = ARRAY_SIZE(adis16477_channels), + .channels = adis16477_channels, .gyro_max_val = 1, .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), .accel_max_val = 1, .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(720), + .deltvel_max_val = 400, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, .num_sync = ARRAY_SIZE(adis16475_sync_mode), - .has_burst32 = true, + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), }, [ADIS16477_3] = { .name = "adis16477-3", - .num_channels = ARRAY_SIZE(adis16475_channels), - .channels = adis16475_channels, + .num_channels = ARRAY_SIZE(adis16477_channels), + .channels = adis16477_channels, .gyro_max_val = 1, .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), .accel_max_val = 1, .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(2160), + .deltvel_max_val = 400, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, .num_sync = ARRAY_SIZE(adis16475_sync_mode), - .has_burst32 = true, + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), }, [ADIS16465_1] = { @@ -770,6 +868,8 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .accel_max_val = 1, .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(360), + .deltvel_max_val = 100, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, @@ -785,6 +885,8 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .accel_max_val = 1, .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(720), + .deltvel_max_val = 100, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, @@ -800,6 +902,8 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .accel_max_val = 1, .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(2160), + .deltvel_max_val = 100, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, @@ -815,6 +919,8 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .accel_max_val = 1, .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(360), + .deltvel_max_val = 400, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, @@ -830,6 +936,8 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .accel_max_val = 1, .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(720), + .deltvel_max_val = 400, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, @@ -845,6 +953,8 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .accel_max_val = 1, .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(2160), + .deltvel_max_val = 400, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, @@ -853,129 +963,168 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { }, [ADIS16500] = { .name = "adis16500", - .num_channels = ARRAY_SIZE(adis16475_channels), - .channels = adis16475_channels, + .num_channels = ARRAY_SIZE(adis16477_channels), + .channels = adis16477_channels, .gyro_max_val = 1, .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), .accel_max_val = 392, .accel_max_scale = 32000 << 16, .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(2160), + .deltvel_max_val = 400, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, /* pulse sync not supported */ .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, - .has_burst32 = true, + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data = ADIS16475_DATA(16500, &adis1650x_timeouts), }, [ADIS16505_1] = { .name = "adis16505-1", - .num_channels = ARRAY_SIZE(adis16475_channels), - .channels = adis16475_channels, + .num_channels = ARRAY_SIZE(adis16477_channels), + .channels = adis16477_channels, .gyro_max_val = 1, .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), .accel_max_val = 78, .accel_max_scale = 32000 << 16, .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(360), + .deltvel_max_val = 100, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, /* pulse sync not supported */ .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, - .has_burst32 = true, + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), }, [ADIS16505_2] = { .name = "adis16505-2", - .num_channels = ARRAY_SIZE(adis16475_channels), - .channels = adis16475_channels, + .num_channels = ARRAY_SIZE(adis16477_channels), + .channels = adis16477_channels, .gyro_max_val = 1, .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), .accel_max_val = 78, .accel_max_scale = 32000 << 16, .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(720), + .deltvel_max_val = 100, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, /* pulse sync not supported */ .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, - .has_burst32 = true, + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), }, [ADIS16505_3] = { .name = "adis16505-3", - .num_channels = ARRAY_SIZE(adis16475_channels), - .channels = adis16475_channels, + .num_channels = ARRAY_SIZE(adis16477_channels), + .channels = adis16477_channels, .gyro_max_val = 1, .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), .accel_max_val = 78, .accel_max_scale = 32000 << 16, .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(2160), + .deltvel_max_val = 100, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, /* pulse sync not supported */ .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, - .has_burst32 = true, + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), }, [ADIS16507_1] = { .name = "adis16507-1", - .num_channels = ARRAY_SIZE(adis16475_channels), - .channels = adis16475_channels, + .num_channels = ARRAY_SIZE(adis16477_channels), + .channels = adis16477_channels, .gyro_max_val = 1, .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), .accel_max_val = 392, .accel_max_scale = 32000 << 16, .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(360), + .deltvel_max_val = 400, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, /* pulse sync not supported */ .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, - .has_burst32 = true, + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), }, [ADIS16507_2] = { .name = "adis16507-2", - .num_channels = ARRAY_SIZE(adis16475_channels), - .channels = adis16475_channels, + .num_channels = ARRAY_SIZE(adis16477_channels), + .channels = adis16477_channels, .gyro_max_val = 1, .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), .accel_max_val = 392, .accel_max_scale = 32000 << 16, .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(720), + .deltvel_max_val = 400, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, /* pulse sync not supported */ .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, - .has_burst32 = true, + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), }, [ADIS16507_3] = { .name = "adis16507-3", - .num_channels = ARRAY_SIZE(adis16475_channels), - .channels = adis16475_channels, + .num_channels = ARRAY_SIZE(adis16477_channels), + .channels = adis16477_channels, .gyro_max_val = 1, .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), .accel_max_val = 392, .accel_max_scale = 32000 << 16, .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(2160), + .deltvel_max_val = 400, .int_clk = 2000, .max_dec = 1999, .sync = adis16475_sync_mode, /* pulse sync not supported */ .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, - .has_burst32 = true, + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), }, }; +static int adis16475_update_scan_mode(struct iio_dev *indio_dev, + const unsigned long *scan_mask) +{ + u16 en; + int ret; + struct adis16475 *st = iio_priv(indio_dev); + + if (st->info->flags & ADIS16475_HAS_BURST_DELTA_DATA) { + if ((*scan_mask & ADIS16500_BURST_DATA_SEL_0_CHN_MASK) && + (*scan_mask & ADIS16500_BURST_DATA_SEL_1_CHN_MASK)) + return -EINVAL; + if (*scan_mask & ADIS16500_BURST_DATA_SEL_0_CHN_MASK) + en = FIELD_PREP(ADIS16500_BURST_DATA_SEL_MASK, 0); + else + en = FIELD_PREP(ADIS16500_BURST_DATA_SEL_MASK, 1); + + ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, + ADIS16500_BURST_DATA_SEL_MASK, en); + if (ret) + return ret; + } + + return adis_update_scan_mode(indio_dev, scan_mask); +} + static const struct iio_info adis16475_info = { .read_raw = &adis16475_read_raw, .write_raw = &adis16475_write_raw, - .update_scan_mode = adis_update_scan_mode, + .update_scan_mode = adis16475_update_scan_mode, .debugfs_reg_access = adis_debugfs_reg_access, }; @@ -998,7 +1147,7 @@ static void adis16475_burst32_check(struct adis16475 *st) int ret; struct adis *adis = &st->adis; - if (!st->info->has_burst32) + if (!(st->info->flags & ADIS16475_HAS_BURST32)) return; if (st->lsb_flag && !st->burst32) { @@ -1044,7 +1193,7 @@ static irqreturn_t adis16475_trigger_handler(int irq, void *p) struct iio_dev *indio_dev = pf->indio_dev; struct adis16475 *st = iio_priv(indio_dev); struct adis *adis = &st->adis; - int ret, bit, i = 0; + int ret, bit, buff_offset = 0, i = 0; __be16 *buffer; u16 crc; bool valid; @@ -1073,7 +1222,20 @@ static irqreturn_t adis16475_trigger_handler(int irq, void *p) switch (bit) { case ADIS16475_SCAN_TEMP: st->data[i++] = buffer[offset]; + /* + * The temperature channel has 16-bit storage size. + * We need to perform the padding to have the buffer + * elements naturally aligned in case there are any + * 32-bit storage size channels enabled which have a + * scan index higher than the temperature channel scan + * index. + */ + if (*indio_dev->active_scan_mask & GENMASK(ADIS16475_SCAN_DELTVEL_Z, ADIS16475_SCAN_DELTANG_X)) + st->data[i++] = 0; break; + case ADIS16475_SCAN_DELTANG_X ... ADIS16475_SCAN_DELTVEL_Z: + buff_offset = ADIS16475_SCAN_DELTANG_X; + fallthrough; case ADIS16475_SCAN_GYRO_X ... ADIS16475_SCAN_ACCEL_Z: /* * The first 2 bytes on the received data are the @@ -1081,18 +1243,18 @@ static irqreturn_t adis16475_trigger_handler(int irq, void *p) */ if (st->burst32) { /* upper 16 */ - st->data[i++] = buffer[bit * 2 + 2]; + st->data[i++] = buffer[(bit - buff_offset) * 2 + 2]; /* lower 16 */ - st->data[i++] = buffer[bit * 2 + 1]; + st->data[i++] = buffer[(bit - buff_offset) * 2 + 1]; } else { - st->data[i++] = buffer[bit + 1]; + st->data[i++] = buffer[(bit - buff_offset) + 1]; /* * Don't bother in doing the manual read if the * device supports burst32. burst32 will be * enabled in the next call to * adis16475_burst32_check()... */ - if (st->lsb_flag && !st->info->has_burst32) { + if (st->lsb_flag && !(st->info->flags & ADIS16475_HAS_BURST32)) { u16 val = 0; const u32 reg = ADIS16475_REG_X_GYRO_L + bit * 4; diff --git a/drivers/iio/imu/bno055/Kconfig b/drivers/iio/imu/bno055/Kconfig index 83e53acfbe..c7f5866a17 100644 --- a/drivers/iio/imu/bno055/Kconfig +++ b/drivers/iio/imu/bno055/Kconfig @@ -8,6 +8,7 @@ config BOSCH_BNO055 config BOSCH_BNO055_SERIAL tristate "Bosch BNO055 attached via UART" depends on SERIAL_DEV_BUS + select REGMAP select BOSCH_BNO055 help Enable this to support Bosch BNO055 IMUs attached via UART. diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_aux.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_aux.c index 7327e5723f..8a7f291190 100644 --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_aux.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_aux.c @@ -71,6 +71,19 @@ int inv_mpu_aux_init(const struct inv_mpu6050_state *st) unsigned int val; int ret; + /* + * Code based on the vendor Linux kernel v3.0, + * the exact meaning is unknown. + */ + if (st->chip_type == INV_MPU9150) { + unsigned int mask = BIT(7); + + val = st->level_shifter ? mask : 0; + ret = regmap_update_bits(st->map, 0x1, mask, val); + if (ret) + return ret; + } + /* configure i2c master */ val = INV_MPU6050_BITS_I2C_MST_CLK_400KHZ | INV_MPU6050_BIT_WAIT_FOR_ES; diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c index a9a5fb266e..6b034dccc3 100644 --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -1495,6 +1496,8 @@ int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name, st->irq = irq; st->map = regmap; + st->level_shifter = device_property_read_bool(dev, + "invensense,level-shifter"); pdata = dev_get_platdata(dev); if (!pdata) { result = iio_read_mount_matrix(dev, &st->orientation); diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h index ed5a96e78d..5950e2419e 100644 --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h @@ -203,6 +203,7 @@ struct inv_mpu6050_state { s32 magn_raw_to_gauss[3]; struct iio_mount_matrix magn_orient; unsigned int suspended_sensors; + bool level_shifter; u8 *data; }; @@ -464,7 +465,6 @@ int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type); int inv_mpu6050_prepare_fifo(struct inv_mpu6050_state *st, bool enable); int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, unsigned int mask); -int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val); int inv_mpu_acpi_create_mux_client(struct i2c_client *client); void inv_mpu_acpi_delete_mux_client(struct i2c_client *client); int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name, -- cgit v1.2.3