From ace9429bb58fd418f0c81d4c2835699bddf6bde6 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Thu, 11 Apr 2024 10:27:49 +0200 Subject: Adding upstream version 6.6.15. Signed-off-by: Daniel Baumann --- drivers/watchdog/of_xilinx_wdt.c | 297 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 297 insertions(+) create mode 100644 drivers/watchdog/of_xilinx_wdt.c (limited to 'drivers/watchdog/of_xilinx_wdt.c') diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c new file mode 100644 index 0000000000..05657dc1d3 --- /dev/null +++ b/drivers/watchdog/of_xilinx_wdt.c @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt + * + * (C) Copyright 2013 - 2014 Xilinx, Inc. + * (C) Copyright 2011 (Alejandro Cabrera ) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Register offsets for the Wdt device */ +#define XWT_TWCSR0_OFFSET 0x0 /* Control/Status Register0 */ +#define XWT_TWCSR1_OFFSET 0x4 /* Control/Status Register1 */ +#define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */ + +/* Control/Status Register Masks */ +#define XWT_CSR0_WRS_MASK BIT(3) /* Reset status */ +#define XWT_CSR0_WDS_MASK BIT(2) /* Timer state */ +#define XWT_CSR0_EWDT1_MASK BIT(1) /* Enable bit 1 */ + +/* Control/Status Register 0/1 bits */ +#define XWT_CSRX_EWDT2_MASK BIT(0) /* Enable bit 2 */ + +/* SelfTest constants */ +#define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000 +#define XWT_TIMER_FAILED 0xFFFFFFFF + +#define WATCHDOG_NAME "Xilinx Watchdog" + +struct xwdt_device { + void __iomem *base; + u32 wdt_interval; + spinlock_t spinlock; /* spinlock for register handling */ + struct watchdog_device xilinx_wdt_wdd; + struct clk *clk; +}; + +static int xilinx_wdt_start(struct watchdog_device *wdd) +{ + int ret; + u32 control_status_reg; + struct xwdt_device *xdev = watchdog_get_drvdata(wdd); + + ret = clk_enable(xdev->clk); + if (ret) { + dev_err(wdd->parent, "Failed to enable clock\n"); + return ret; + } + + spin_lock(&xdev->spinlock); + + /* Clean previous status and enable the watchdog timer */ + control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); + control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); + + iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK), + xdev->base + XWT_TWCSR0_OFFSET); + + iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET); + + spin_unlock(&xdev->spinlock); + + dev_dbg(wdd->parent, "Watchdog Started!\n"); + + return 0; +} + +static int xilinx_wdt_stop(struct watchdog_device *wdd) +{ + u32 control_status_reg; + struct xwdt_device *xdev = watchdog_get_drvdata(wdd); + + spin_lock(&xdev->spinlock); + + control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); + + iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK), + xdev->base + XWT_TWCSR0_OFFSET); + + iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET); + + spin_unlock(&xdev->spinlock); + + clk_disable(xdev->clk); + + dev_dbg(wdd->parent, "Watchdog Stopped!\n"); + + return 0; +} + +static int xilinx_wdt_keepalive(struct watchdog_device *wdd) +{ + u32 control_status_reg; + struct xwdt_device *xdev = watchdog_get_drvdata(wdd); + + spin_lock(&xdev->spinlock); + + control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); + control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); + iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET); + + spin_unlock(&xdev->spinlock); + + return 0; +} + +static const struct watchdog_info xilinx_wdt_ident = { + .options = WDIOF_MAGICCLOSE | + WDIOF_KEEPALIVEPING, + .firmware_version = 1, + .identity = WATCHDOG_NAME, +}; + +static const struct watchdog_ops xilinx_wdt_ops = { + .owner = THIS_MODULE, + .start = xilinx_wdt_start, + .stop = xilinx_wdt_stop, + .ping = xilinx_wdt_keepalive, +}; + +static u32 xwdt_selftest(struct xwdt_device *xdev) +{ + int i; + u32 timer_value1; + u32 timer_value2; + + spin_lock(&xdev->spinlock); + + timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET); + timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET); + + for (i = 0; + ((i <= XWT_MAX_SELFTEST_LOOP_COUNT) && + (timer_value2 == timer_value1)); i++) { + timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET); + } + + spin_unlock(&xdev->spinlock); + + if (timer_value2 != timer_value1) + return ~XWT_TIMER_FAILED; + else + return XWT_TIMER_FAILED; +} + +static int xwdt_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + int rc; + u32 pfreq = 0, enable_once = 0; + struct xwdt_device *xdev; + struct watchdog_device *xilinx_wdt_wdd; + + xdev = devm_kzalloc(dev, sizeof(*xdev), GFP_KERNEL); + if (!xdev) + return -ENOMEM; + + xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd; + xilinx_wdt_wdd->info = &xilinx_wdt_ident; + xilinx_wdt_wdd->ops = &xilinx_wdt_ops; + xilinx_wdt_wdd->parent = dev; + + xdev->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(xdev->base)) + return PTR_ERR(xdev->base); + + rc = of_property_read_u32(dev->of_node, "xlnx,wdt-interval", + &xdev->wdt_interval); + if (rc) + dev_warn(dev, "Parameter \"xlnx,wdt-interval\" not found\n"); + + rc = of_property_read_u32(dev->of_node, "xlnx,wdt-enable-once", + &enable_once); + if (rc) + dev_warn(dev, + "Parameter \"xlnx,wdt-enable-once\" not found\n"); + + watchdog_set_nowayout(xilinx_wdt_wdd, enable_once); + + xdev->clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(xdev->clk)) { + if (PTR_ERR(xdev->clk) != -ENOENT) + return PTR_ERR(xdev->clk); + + /* + * Clock framework support is optional, continue on + * anyways if we don't find a matching clock. + */ + xdev->clk = NULL; + + rc = of_property_read_u32(dev->of_node, "clock-frequency", + &pfreq); + if (rc) + dev_warn(dev, + "The watchdog clock freq cannot be obtained\n"); + } else { + pfreq = clk_get_rate(xdev->clk); + } + + /* + * Twice of the 2^wdt_interval / freq because the first wdt overflow is + * ignored (interrupt), reset is only generated at second wdt overflow + */ + if (pfreq && xdev->wdt_interval) + xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) / + pfreq); + + spin_lock_init(&xdev->spinlock); + watchdog_set_drvdata(xilinx_wdt_wdd, xdev); + + rc = xwdt_selftest(xdev); + if (rc == XWT_TIMER_FAILED) { + dev_err(dev, "SelfTest routine error\n"); + return rc; + } + + rc = devm_watchdog_register_device(dev, xilinx_wdt_wdd); + if (rc) + return rc; + + clk_disable(xdev->clk); + + dev_info(dev, "Xilinx Watchdog Timer with timeout %ds\n", + xilinx_wdt_wdd->timeout); + + platform_set_drvdata(pdev, xdev); + + return 0; +} + +/** + * xwdt_suspend - Suspend the device. + * + * @dev: handle to the device structure. + * Return: 0 always. + */ +static int __maybe_unused xwdt_suspend(struct device *dev) +{ + struct xwdt_device *xdev = dev_get_drvdata(dev); + + if (watchdog_active(&xdev->xilinx_wdt_wdd)) + xilinx_wdt_stop(&xdev->xilinx_wdt_wdd); + + return 0; +} + +/** + * xwdt_resume - Resume the device. + * + * @dev: handle to the device structure. + * Return: 0 on success, errno otherwise. + */ +static int __maybe_unused xwdt_resume(struct device *dev) +{ + struct xwdt_device *xdev = dev_get_drvdata(dev); + int ret = 0; + + if (watchdog_active(&xdev->xilinx_wdt_wdd)) + ret = xilinx_wdt_start(&xdev->xilinx_wdt_wdd); + + return ret; +} + +static SIMPLE_DEV_PM_OPS(xwdt_pm_ops, xwdt_suspend, xwdt_resume); + +/* Match table for of_platform binding */ +static const struct of_device_id xwdt_of_match[] = { + { .compatible = "xlnx,xps-timebase-wdt-1.00.a", }, + { .compatible = "xlnx,xps-timebase-wdt-1.01.a", }, + {}, +}; +MODULE_DEVICE_TABLE(of, xwdt_of_match); + +static struct platform_driver xwdt_driver = { + .probe = xwdt_probe, + .driver = { + .name = WATCHDOG_NAME, + .of_match_table = xwdt_of_match, + .pm = &xwdt_pm_ops, + }, +}; + +module_platform_driver(xwdt_driver); + +MODULE_AUTHOR("Alejandro Cabrera "); +MODULE_DESCRIPTION("Xilinx Watchdog driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3