/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef _athub_1_8_0_OFFSET_HEADER #define _athub_1_8_0_OFFSET_HEADER // addressBlock: aid_athub_atsdec // base address: 0x3080 #define regATC_ATS_CNTL 0x0000 #define regATC_ATS_CNTL_BASE_IDX 0 #define regATC_ATS_CNTL2 0x0001 #define regATC_ATS_CNTL2_BASE_IDX 0 #define regATC_ATS_CNTL3 0x0002 #define regATC_ATS_CNTL3_BASE_IDX 0 #define regATC_ATS_CNTL4 0x0003 #define regATC_ATS_CNTL4_BASE_IDX 0 #define regATC_ATS_MISC_CNTL 0x0005 #define regATC_ATS_MISC_CNTL_BASE_IDX 0 #define regATC_ATS_STATUS 0x0009 #define regATC_ATS_STATUS_BASE_IDX 0 #define regATC_PERFCOUNTER0_CFG 0x000a #define regATC_PERFCOUNTER0_CFG_BASE_IDX 0 #define regATC_PERFCOUNTER1_CFG 0x000b #define regATC_PERFCOUNTER1_CFG_BASE_IDX 0 #define regATC_PERFCOUNTER2_CFG 0x000c #define regATC_PERFCOUNTER2_CFG_BASE_IDX 0 #define regATC_PERFCOUNTER3_CFG 0x000d #define regATC_PERFCOUNTER3_CFG_BASE_IDX 0 #define regATC_PERFCOUNTER_RSLT_CNTL 0x000e #define regATC_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 #define regATC_PERFCOUNTER_LO 0x000f #define regATC_PERFCOUNTER_LO_BASE_IDX 0 #define regATC_PERFCOUNTER_HI 0x0010 #define regATC_PERFCOUNTER_HI_BASE_IDX 0 #define regATC_ATS_FAULT_CNTL 0x0012 #define regATC_ATS_FAULT_CNTL_BASE_IDX 0 #define regATC_ATS_FAULT_STATUS_INFO 0x0013 #define regATC_ATS_FAULT_STATUS_INFO_BASE_IDX 0 #define regATC_ATS_FAULT_STATUS_INFO2 0x0014 #define regATC_ATS_FAULT_STATUS_INFO2_BASE_IDX 0 #define regATC_ATS_FAULT_STATUS_INFO3 0x0015 #define regATC_ATS_FAULT_STATUS_INFO3_BASE_IDX 0 #define regATC_ATS_FAULT_STATUS_INFO4 0x0016 #define regATC_ATS_FAULT_STATUS_INFO4_BASE_IDX 0 #define regATC_ATS_FAULT_STATUS_ADDR 0x0017 #define regATC_ATS_FAULT_STATUS_ADDR_BASE_IDX 0 #define regATC_ATS_DEFAULT_PAGE_LOW 0x0018 #define regATC_ATS_DEFAULT_PAGE_LOW_BASE_IDX 0 #define regATHUB_PCIE_ATS_CNTL 0x001f #define regATHUB_PCIE_ATS_CNTL_BASE_IDX 0 #define regATHUB_PCIE_PASID_CNTL 0x0020 #define regATHUB_PCIE_PASID_CNTL_BASE_IDX 0 #define regATHUB_PCIE_PAGE_REQ_CNTL 0x0021 #define regATHUB_PCIE_PAGE_REQ_CNTL_BASE_IDX 0 #define regATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x0022 #define regATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 0 #define regATHUB_COMMAND 0x0023 #define regATHUB_COMMAND_BASE_IDX 0 #define regATHUB_PCIE_ATS_CNTL_VF_0 0x0024 #define regATHUB_PCIE_ATS_CNTL_VF_0_BASE_IDX 0 #define regATHUB_PCIE_ATS_CNTL_VF_1 0x0025 #define regATHUB_PCIE_ATS_CNTL_VF_1_BASE_IDX 0 #define regATHUB_PCIE_ATS_CNTL_VF_2 0x0026 #define regATHUB_PCIE_ATS_CNTL_VF_2_BASE_IDX 0 #define regATHUB_PCIE_ATS_CNTL_VF_3 0x0027 #define regATHUB_PCIE_ATS_CNTL_VF_3_BASE_IDX 0 #define regATHUB_PCIE_ATS_CNTL_VF_4 0x0028 #define regATHUB_PCIE_ATS_CNTL_VF_4_BASE_IDX 0 #define regATHUB_PCIE_ATS_CNTL_VF_5 0x0029 #define regATHUB_PCIE_ATS_CNTL_VF_5_BASE_IDX 0 #define regATHUB_PCIE_ATS_CNTL_VF_6 0x002a #define regATHUB_PCIE_ATS_CNTL_VF_6_BASE_IDX 0 #define regATHUB_PCIE_ATS_CNTL_VF_7 0x002b #define regATHUB_PCIE_ATS_CNTL_VF_7_BASE_IDX 0 #define regATHUB_PCIE_ATS_CNTL_VF_8 0x002c #define regATHUB_PCIE_ATS_CNTL_VF_8_BASE_IDX 0 #define regATHUB_PCIE_ATS_CNTL_VF_9 0x002d #define regATHUB_PCIE_ATS_CNTL_VF_9_BASE_IDX 0 #define regATHUB_PCIE_ATS_CNTL_VF_10 0x002e #define regATHUB_PCIE_ATS_CNTL_VF_10_BASE_IDX 0 #define regATHUB_PCIE_ATS_CNTL_VF_11 0x002f #define regATHUB_PCIE_ATS_CNTL_VF_11_BASE_IDX 0 #define regATHUB_PCIE_ATS_CNTL_VF_12 0x0030 #define regATHUB_PCIE_ATS_CNTL_VF_12_BASE_IDX 0 #define regATHUB_PCIE_ATS_CNTL_VF_13 0x0031 #define regATHUB_PCIE_ATS_CNTL_VF_13_BASE_IDX 0 #define regATHUB_PCIE_ATS_CNTL_VF_14 0x0032 #define regATHUB_PCIE_ATS_CNTL_VF_14_BASE_IDX 0 #define regATHUB_PCIE_ATS_CNTL_VF_15 0x0033 #define regATHUB_PCIE_ATS_CNTL_VF_15_BASE_IDX 0 #define regATHUB_SHARED_VIRT_RESET_REQ 0x0034 #define regATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX 0 #define regATHUB_SHARED_ACTIVE_FCN_ID 0x0036 #define regATHUB_SHARED_ACTIVE_FCN_ID_BASE_IDX 0 #define regATC_ATS_SDPPORT_CNTL 0x0038 #define regATC_ATS_SDPPORT_CNTL_BASE_IDX 0 #define regATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x003e #define regATC_VMID_PASID_MAPPING_UPDATE_STATUS_BASE_IDX 0 #define regATC_VMID0_PASID_MAPPING 0x003f #define regATC_VMID0_PASID_MAPPING_BASE_IDX 0 #define regATC_VMID1_PASID_MAPPING 0x0040 #define regATC_VMID1_PASID_MAPPING_BASE_IDX 0 #define regATC_VMID2_PASID_MAPPING 0x0041 #define regATC_VMID2_PASID_MAPPING_BASE_IDX 0 #define regATC_VMID3_PASID_MAPPING 0x0042 #define regATC_VMID3_PASID_MAPPING_BASE_IDX 0 #define regATC_VMID4_PASID_MAPPING 0x0043 #define regATC_VMID4_PASID_MAPPING_BASE_IDX 0 #define regATC_VMID5_PASID_MAPPING 0x0044 #define regATC_VMID5_PASID_MAPPING_BASE_IDX 0 #define regATC_VMID6_PASID_MAPPING 0x0045 #define regATC_VMID6_PASID_MAPPING_BASE_IDX 0 #define regATC_VMID7_PASID_MAPPING 0x0046 #define regATC_VMID7_PASID_MAPPING_BASE_IDX 0 #define regATC_VMID8_PASID_MAPPING 0x0047 #define regATC_VMID8_PASID_MAPPING_BASE_IDX 0 #define regATC_VMID9_PASID_MAPPING 0x0048 #define regATC_VMID9_PASID_MAPPING_BASE_IDX 0 #define regATC_VMID10_PASID_MAPPING 0x0049 #define regATC_VMID10_PASID_MAPPING_BASE_IDX 0 #define regATC_VMID11_PASID_MAPPING 0x004a #define regATC_VMID11_PASID_MAPPING_BASE_IDX 0 #define regATC_VMID12_PASID_MAPPING 0x004b #define regATC_VMID12_PASID_MAPPING_BASE_IDX 0 #define regATC_VMID13_PASID_MAPPING 0x004c #define regATC_VMID13_PASID_MAPPING_BASE_IDX 0 #define regATC_VMID14_PASID_MAPPING 0x004d #define regATC_VMID14_PASID_MAPPING_BASE_IDX 0 #define regATC_VMID15_PASID_MAPPING 0x004e #define regATC_VMID15_PASID_MAPPING_BASE_IDX 0 #define regATC_TRANS_FAULT_RSPCNTRL 0x0050 #define regATC_TRANS_FAULT_RSPCNTRL_BASE_IDX 0 #define regATC_ATS_VMID_STATUS 0x0051 #define regATC_ATS_VMID_STATUS_BASE_IDX 0 #define regATHUB_MISC_CNTL 0x0055 #define regATHUB_MISC_CNTL_BASE_IDX 0 #define regATHUB_MEM_POWER_LS 0x0056 #define regATHUB_MEM_POWER_LS_BASE_IDX 0 #define regATHUB_IH_CREDIT 0x0057 #define regATHUB_IH_CREDIT_BASE_IDX 0 // addressBlock: aid_athub_xpbdec // base address: 0x46000 #define regXPB_RTR_SRC_APRTR0 0x0000 #define regXPB_RTR_SRC_APRTR0_BASE_IDX 1 #define regXPB_RTR_SRC_APRTR1 0x0001 #define regXPB_RTR_SRC_APRTR1_BASE_IDX 1 #define regXPB_RTR_SRC_APRTR2 0x0002 #define regXPB_RTR_SRC_APRTR2_BASE_IDX 1 #define regXPB_RTR_SRC_APRTR3 0x0003 #define regXPB_RTR_SRC_APRTR3_BASE_IDX 1 #define regXPB_RTR_SRC_APRTR4 0x0004 #define regXPB_RTR_SRC_APRTR4_BASE_IDX 1 #define regXPB_RTR_SRC_APRTR5 0x0005 #define regXPB_RTR_SRC_APRTR5_BASE_IDX 1 #define regXPB_RTR_SRC_APRTR6 0x0006 #define regXPB_RTR_SRC_APRTR6_BASE_IDX 1 #define regXPB_RTR_SRC_APRTR7 0x0007 #define regXPB_RTR_SRC_APRTR7_BASE_IDX 1 #define regXPB_RTR_SRC_APRTR8 0x0008 #define regXPB_RTR_SRC_APRTR8_BASE_IDX 1 #define regXPB_RTR_SRC_APRTR9 0x0009 #define regXPB_RTR_SRC_APRTR9_BASE_IDX 1 #define regXPB_XDMA_RTR_SRC_APRTR0 0x000a #define regXPB_XDMA_RTR_SRC_APRTR0_BASE_IDX 1 #define regXPB_XDMA_RTR_SRC_APRTR1 0x000b #define regXPB_XDMA_RTR_SRC_APRTR1_BASE_IDX 1 #define regXPB_XDMA_RTR_SRC_APRTR2 0x000c #define regXPB_XDMA_RTR_SRC_APRTR2_BASE_IDX 1 #define regXPB_XDMA_RTR_SRC_APRTR3 0x000d #define regXPB_XDMA_RTR_SRC_APRTR3_BASE_IDX 1 #define regXPB_RTR_DEST_MAP0 0x000e #define regXPB_RTR_DEST_MAP0_BASE_IDX 1 #define regXPB_RTR_DEST_MAP1 0x000f #define regXPB_RTR_DEST_MAP1_BASE_IDX 1 #define regXPB_RTR_DEST_MAP2 0x0010 #define regXPB_RTR_DEST_MAP2_BASE_IDX 1 #define regXPB_RTR_DEST_MAP3 0x0011 #define regXPB_RTR_DEST_MAP3_BASE_IDX 1 #define regXPB_RTR_DEST_MAP4 0x0012 #define regXPB_RTR_DEST_MAP4_BASE_IDX 1 #define regXPB_RTR_DEST_MAP5 0x0013 #define regXPB_RTR_DEST_MAP5_BASE_IDX 1 #define regXPB_RTR_DEST_MAP6 0x0014 #define regXPB_RTR_DEST_MAP6_BASE_IDX 1 #define regXPB_RTR_DEST_MAP7 0x0015 #define regXPB_RTR_DEST_MAP7_BASE_IDX 1 #define regXPB_RTR_DEST_MAP8 0x0016 #define regXPB_RTR_DEST_MAP8_BASE_IDX 1 #define regXPB_RTR_DEST_MAP9 0x0017 #define regXPB_RTR_DEST_MAP9_BASE_IDX 1 #define regXPB_XDMA_RTR_DEST_MAP0 0x0018 #define regXPB_XDMA_RTR_DEST_MAP0_BASE_IDX 1 #define regXPB_XDMA_RTR_DEST_MAP1 0x0019 #define regXPB_XDMA_RTR_DEST_MAP1_BASE_IDX 1 #define regXPB_XDMA_RTR_DEST_MAP2 0x001a #define regXPB_XDMA_RTR_DEST_MAP2_BASE_IDX 1 #define regXPB_XDMA_RTR_DEST_MAP3 0x001b #define regXPB_XDMA_RTR_DEST_MAP3_BASE_IDX 1 #define regXPB_CLG_CFG0 0x001c #define regXPB_CLG_CFG0_BASE_IDX 1 #define regXPB_CLG_CFG1 0x001d #define regXPB_CLG_CFG1_BASE_IDX 1 #define regXPB_CLG_CFG2 0x001e #define regXPB_CLG_CFG2_BASE_IDX 1 #define regXPB_CLG_CFG3 0x001f #define regXPB_CLG_CFG3_BASE_IDX 1 #define regXPB_CLG_CFG4 0x0020 #define regXPB_CLG_CFG4_BASE_IDX 1 #define regXPB_CLG_CFG5 0x0021 #define regXPB_CLG_CFG5_BASE_IDX 1 #define regXPB_CLG_CFG6 0x0022 #define regXPB_CLG_CFG6_BASE_IDX 1 #define regXPB_CLG_CFG7 0x0023 #define regXPB_CLG_CFG7_BASE_IDX 1 #define regXPB_CLG_EXTRA0 0x0024 #define regXPB_CLG_EXTRA0_BASE_IDX 1 #define regXPB_CLG_EXTRA1 0x0025 #define regXPB_CLG_EXTRA1_BASE_IDX 1 #define regXPB_CLG_EXTRA_MSK 0x0026 #define regXPB_CLG_EXTRA_MSK_BASE_IDX 1 #define regXPB_LB_ADDR 0x0027 #define regXPB_LB_ADDR_BASE_IDX 1 #define regXPB_WCB_STS 0x0028 #define regXPB_WCB_STS_BASE_IDX 1 #define regXPB_HST_CFG 0x0029 #define regXPB_HST_CFG_BASE_IDX 1 #define regXPB_P2P_BAR_CFG 0x002a #define regXPB_P2P_BAR_CFG_BASE_IDX 1 #define regXPB_P2P_BAR0 0x002b #define regXPB_P2P_BAR0_BASE_IDX 1 #define regXPB_P2P_BAR1 0x002c #define regXPB_P2P_BAR1_BASE_IDX 1 #define regXPB_P2P_BAR2 0x002d #define regXPB_P2P_BAR2_BASE_IDX 1 #define regXPB_P2P_BAR3 0x002e #define regXPB_P2P_BAR3_BASE_IDX 1 #define regXPB_P2P_BAR4 0x002f #define regXPB_P2P_BAR4_BASE_IDX 1 #define regXPB_P2P_BAR5 0x0030 #define regXPB_P2P_BAR5_BASE_IDX 1 #define regXPB_P2P_BAR6 0x0031 #define regXPB_P2P_BAR6_BASE_IDX 1 #define regXPB_P2P_BAR7 0x0032 #define regXPB_P2P_BAR7_BASE_IDX 1 #define regXPB_P2P_BAR_SETUP 0x0033 #define regXPB_P2P_BAR_SETUP_BASE_IDX 1 #define regXPB_P2P_BAR_DELTA_ABOVE 0x0035 #define regXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 1 #define regXPB_P2P_BAR_DELTA_BELOW 0x0036 #define regXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 1 #define regXPB_PEER_SYS_BAR0 0x0037 #define regXPB_PEER_SYS_BAR0_BASE_IDX 1 #define regXPB_PEER_SYS_BAR1 0x0038 #define regXPB_PEER_SYS_BAR1_BASE_IDX 1 #define regXPB_PEER_SYS_BAR2 0x0039 #define regXPB_PEER_SYS_BAR2_BASE_IDX 1 #define regXPB_PEER_SYS_BAR3 0x003a #define regXPB_PEER_SYS_BAR3_BASE_IDX 1 #define regXPB_PEER_SYS_BAR4 0x003b #define regXPB_PEER_SYS_BAR4_BASE_IDX 1 #define regXPB_PEER_SYS_BAR5 0x003c #define regXPB_PEER_SYS_BAR5_BASE_IDX 1 #define regXPB_PEER_SYS_BAR6 0x003d #define regXPB_PEER_SYS_BAR6_BASE_IDX 1 #define regXPB_PEER_SYS_BAR7 0x003e #define regXPB_PEER_SYS_BAR7_BASE_IDX 1 #define regXPB_PEER_SYS_BAR8 0x003f #define regXPB_PEER_SYS_BAR8_BASE_IDX 1 #define regXPB_PEER_SYS_BAR9 0x0040 #define regXPB_PEER_SYS_BAR9_BASE_IDX 1 #define regXPB_XDMA_PEER_SYS_BAR0 0x0041 #define regXPB_XDMA_PEER_SYS_BAR0_BASE_IDX 1 #define regXPB_XDMA_PEER_SYS_BAR1 0x0042 #define regXPB_XDMA_PEER_SYS_BAR1_BASE_IDX 1 #define regXPB_XDMA_PEER_SYS_BAR2 0x0043 #define regXPB_XDMA_PEER_SYS_BAR2_BASE_IDX 1 #define regXPB_XDMA_PEER_SYS_BAR3 0x0044 #define regXPB_XDMA_PEER_SYS_BAR3_BASE_IDX 1 #define regXPB_CLK_GAT 0x0045 #define regXPB_CLK_GAT_BASE_IDX 1 #define regXPB_INTF_CFG 0x0046 #define regXPB_INTF_CFG_BASE_IDX 1 #define regXPB_INTF_STS 0x0047 #define regXPB_INTF_STS_BASE_IDX 1 #define regXPB_PIPE_STS 0x0048 #define regXPB_PIPE_STS_BASE_IDX 1 #define regXPB_SUB_CTRL 0x0049 #define regXPB_SUB_CTRL_BASE_IDX 1 #define regXPB_MAP_INVERT_FLUSH_NUM_LSB 0x004a #define regXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 1 #define regXPB_PERF_KNOBS 0x004b #define regXPB_PERF_KNOBS_BASE_IDX 1 #define regXPB_STICKY 0x004c #define regXPB_STICKY_BASE_IDX 1 #define regXPB_STICKY_W1C 0x004d #define regXPB_STICKY_W1C_BASE_IDX 1 #define regXPB_MISC_CFG 0x004e #define regXPB_MISC_CFG_BASE_IDX 1 #define regXPB_INTF_CFG2 0x004f #define regXPB_INTF_CFG2_BASE_IDX 1 #define regXPB_CLG_EXTRA_RD 0x0050 #define regXPB_CLG_EXTRA_RD_BASE_IDX 1 #define regXPB_CLG_EXTRA_MSK_RD 0x0051 #define regXPB_CLG_EXTRA_MSK_RD_BASE_IDX 1 #define regXPB_CLG_GFX_MATCH 0x0052 #define regXPB_CLG_GFX_MATCH_BASE_IDX 1 #define regXPB_CLG_GFX_MATCH_VLD 0x0053 #define regXPB_CLG_GFX_MATCH_VLD_BASE_IDX 1 #define regXPB_CLG_GFX_MATCH_MSK 0x0054 #define regXPB_CLG_GFX_MATCH_MSK_BASE_IDX 1 #define regXPB_CLG_MM_MATCH 0x0055 #define regXPB_CLG_MM_MATCH_BASE_IDX 1 #define regXPB_CLG_MM_MATCH_VLD 0x0056 #define regXPB_CLG_MM_MATCH_VLD_BASE_IDX 1 #define regXPB_CLG_MM_MATCH_MSK 0x0057 #define regXPB_CLG_MM_MATCH_MSK_BASE_IDX 1 #define regXPB_CLG_GFX_UNITID_MAPPING0 0x0058 #define regXPB_CLG_GFX_UNITID_MAPPING0_BASE_IDX 1 #define regXPB_CLG_GFX_UNITID_MAPPING1 0x0059 #define regXPB_CLG_GFX_UNITID_MAPPING1_BASE_IDX 1 #define regXPB_CLG_GFX_UNITID_MAPPING2 0x005a #define regXPB_CLG_GFX_UNITID_MAPPING2_BASE_IDX 1 #define regXPB_CLG_GFX_UNITID_MAPPING3 0x005b #define regXPB_CLG_GFX_UNITID_MAPPING3_BASE_IDX 1 #define regXPB_CLG_GFX_UNITID_MAPPING4 0x005c #define regXPB_CLG_GFX_UNITID_MAPPING4_BASE_IDX 1 #define regXPB_CLG_GFX_UNITID_MAPPING5 0x005d #define regXPB_CLG_GFX_UNITID_MAPPING5_BASE_IDX 1 #define regXPB_CLG_GFX_UNITID_MAPPING6 0x005e #define regXPB_CLG_GFX_UNITID_MAPPING6_BASE_IDX 1 #define regXPB_CLG_GFX_UNITID_MAPPING7 0x005f #define regXPB_CLG_GFX_UNITID_MAPPING7_BASE_IDX 1 #define regXPB_CLG_MM_UNITID_MAPPING0 0x0060 #define regXPB_CLG_MM_UNITID_MAPPING0_BASE_IDX 1 #define regXPB_CLG_MM_UNITID_MAPPING1 0x0061 #define regXPB_CLG_MM_UNITID_MAPPING1_BASE_IDX 1 #define regXPB_CLG_MM_UNITID_MAPPING2 0x0062 #define regXPB_CLG_MM_UNITID_MAPPING2_BASE_IDX 1 #define regXPB_CLG_MM_UNITID_MAPPING3 0x0063 #define regXPB_CLG_MM_UNITID_MAPPING3_BASE_IDX 1 // addressBlock: aid_athub_rpbdec // base address: 0x46200 #define regRPB_PASSPW_CONF 0x0080 #define regRPB_PASSPW_CONF_BASE_IDX 1 #define regRPB_BLOCKLEVEL_CONF 0x0081 #define regRPB_BLOCKLEVEL_CONF_BASE_IDX 1 #define regRPB_TAG_CONF 0x0082 #define regRPB_TAG_CONF_BASE_IDX 1 #define regRPB_TAG_CONF2 0x0083 #define regRPB_TAG_CONF2_BASE_IDX 1 #define regRPB_ARB_CNTL 0x0085 #define regRPB_ARB_CNTL_BASE_IDX 1 #define regRPB_ARB_CNTL2 0x0086 #define regRPB_ARB_CNTL2_BASE_IDX 1 #define regRPB_BIF_CNTL 0x0087 #define regRPB_BIF_CNTL_BASE_IDX 1 #define regRPB_BIF_CNTL2 0x0088 #define regRPB_BIF_CNTL2_BASE_IDX 1 #define regRPB_PERF_COUNTER_CNTL 0x008a #define regRPB_PERF_COUNTER_CNTL_BASE_IDX 1 #define regRPB_DEINTRLV_COMBINE_CNTL 0x008c #define regRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 1 #define regRPB_VC_SWITCH_RDWR 0x008d #define regRPB_VC_SWITCH_RDWR_BASE_IDX 1 #define regRPB_PERFCOUNTER_LO 0x008e #define regRPB_PERFCOUNTER_LO_BASE_IDX 1 #define regRPB_PERFCOUNTER_HI 0x008f #define regRPB_PERFCOUNTER_HI_BASE_IDX 1 #define regRPB_PERFCOUNTER0_CFG 0x0090 #define regRPB_PERFCOUNTER0_CFG_BASE_IDX 1 #define regRPB_PERFCOUNTER1_CFG 0x0091 #define regRPB_PERFCOUNTER1_CFG_BASE_IDX 1 #define regRPB_PERFCOUNTER2_CFG 0x0092 #define regRPB_PERFCOUNTER2_CFG_BASE_IDX 1 #define regRPB_PERFCOUNTER3_CFG 0x0093 #define regRPB_PERFCOUNTER3_CFG_BASE_IDX 1 #define regRPB_PERFCOUNTER_RSLT_CNTL 0x0094 #define regRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 #define regRPB_ATS_CNTL 0x0096 #define regRPB_ATS_CNTL_BASE_IDX 1 #define regRPB_ATS_CNTL2 0x0097 #define regRPB_ATS_CNTL2_BASE_IDX 1 #define regRPB_SDPPORT_CNTL 0x0098 #define regRPB_SDPPORT_CNTL_BASE_IDX 1 #endif