[ { "BriefDescription": "Cycles the divider is busy", "EventCode": "0x14", "EventName": "ARITH.CYCLES_DIV_BUSY", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Divide Operations executed", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x14", "EventName": "ARITH.DIV", "Invert": "1", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Multiply operations executed", "EventCode": "0x14", "EventName": "ARITH.MUL", "SampleAfterValue": "2000000", "UMask": "0x2" }, { "BriefDescription": "BACLEAR asserted with bad target address", "EventCode": "0xE6", "EventName": "BACLEAR.BAD_TARGET", "SampleAfterValue": "2000000", "UMask": "0x2" }, { "BriefDescription": "BACLEAR asserted, regardless of cause", "EventCode": "0xE6", "EventName": "BACLEAR.CLEAR", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Instruction queue forced BACLEAR", "EventCode": "0xA7", "EventName": "BACLEAR_FORCE_IQ", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Early Branch Prediction Unit clears", "EventCode": "0xE8", "EventName": "BPU_CLEARS.EARLY", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Late Branch Prediction Unit clears", "EventCode": "0xE8", "EventName": "BPU_CLEARS.LATE", "SampleAfterValue": "2000000", "UMask": "0x2" }, { "BriefDescription": "Branch prediction unit missed call or return", "EventCode": "0xE5", "EventName": "BPU_MISSED_CALL_RET", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Branch instructions decoded", "EventCode": "0xE0", "EventName": "BR_INST_DECODED", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Branch instructions executed", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ANY", "SampleAfterValue": "200000", "UMask": "0x7f" }, { "BriefDescription": "Conditional branch instructions executed", "EventCode": "0x88", "EventName": "BR_INST_EXEC.COND", "SampleAfterValue": "200000", "UMask": "0x1" }, { "BriefDescription": "Unconditional branches executed", "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT", "SampleAfterValue": "200000", "UMask": "0x2" }, { "BriefDescription": "Unconditional call branches executed", "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "20000", "UMask": "0x10" }, { "BriefDescription": "Indirect call branches executed", "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "20000", "UMask": "0x20" }, { "BriefDescription": "Indirect non call branches executed", "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "20000", "UMask": "0x4" }, { "BriefDescription": "Call branches executed", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NEAR_CALLS", "SampleAfterValue": "20000", "UMask": "0x30" }, { "BriefDescription": "All non call branches executed", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NON_CALLS", "SampleAfterValue": "200000", "UMask": "0x7" }, { "BriefDescription": "Indirect return branches executed", "EventCode": "0x88", "EventName": "BR_INST_EXEC.RETURN_NEAR", "SampleAfterValue": "20000", "UMask": "0x8" }, { "BriefDescription": "Taken branches executed", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN", "SampleAfterValue": "200000", "UMask": "0x40" }, { "BriefDescription": "Retired branch instructions (Precise Event)", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", "SampleAfterValue": "200000", "UMask": "0x4" }, { "BriefDescription": "Retired conditional branch instructions (Precise Event)", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", "SampleAfterValue": "200000", "UMask": "0x1" }, { "BriefDescription": "Retired near call instructions (Precise Event)", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", "SampleAfterValue": "20000", "UMask": "0x2" }, { "BriefDescription": "Mispredicted branches executed", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ANY", "SampleAfterValue": "20000", "UMask": "0x7f" }, { "BriefDescription": "Mispredicted conditional branches executed", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.COND", "SampleAfterValue": "20000", "UMask": "0x1" }, { "BriefDescription": "Mispredicted unconditional branches executed", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT", "SampleAfterValue": "20000", "UMask": "0x2" }, { "BriefDescription": "Mispredicted non call branches executed", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "2000", "UMask": "0x10" }, { "BriefDescription": "Mispredicted indirect call branches executed", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "2000", "UMask": "0x20" }, { "BriefDescription": "Mispredicted indirect non call branches executed", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "2000", "UMask": "0x4" }, { "BriefDescription": "Mispredicted call branches executed", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NEAR_CALLS", "SampleAfterValue": "2000", "UMask": "0x30" }, { "BriefDescription": "Mispredicted non call branches executed", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NON_CALLS", "SampleAfterValue": "20000", "UMask": "0x7" }, { "BriefDescription": "Mispredicted return branches executed", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.RETURN_NEAR", "SampleAfterValue": "2000", "UMask": "0x8" }, { "BriefDescription": "Mispredicted taken branches executed", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN", "SampleAfterValue": "20000", "UMask": "0x40" }, { "BriefDescription": "Mispredicted retired branch instructions (Precise Event)", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", "SampleAfterValue": "20000", "UMask": "0x4" }, { "BriefDescription": "Mispredicted conditional retired branches (Precise Event)", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", "SampleAfterValue": "20000", "UMask": "0x1" }, { "BriefDescription": "Mispredicted near retired calls (Precise Event)", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", "PEBS": "1", "SampleAfterValue": "2000", "UMask": "0x2" }, { "BriefDescription": "Reference cycles when thread is not halted (fixed counter)", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000000" }, { "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_P", "SampleAfterValue": "100000", "UMask": "0x1" }, { "BriefDescription": "Cycles when thread is not halted (fixed counter)", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000000" }, { "BriefDescription": "Cycles when thread is not halted (programmable counter)", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000000" }, { "BriefDescription": "Total CPU cycles", "CounterMask": "2", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", "Invert": "1", "SampleAfterValue": "2000000" }, { "BriefDescription": "Any Instruction Length Decoder stall cycles", "EventCode": "0x87", "EventName": "ILD_STALL.ANY", "SampleAfterValue": "2000000", "UMask": "0xf" }, { "BriefDescription": "Instruction Queue full stall cycles", "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "SampleAfterValue": "2000000", "UMask": "0x4" }, { "BriefDescription": "Length Change Prefix stall cycles", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Stall cycles due to BPU MRU bypass", "EventCode": "0x87", "EventName": "ILD_STALL.MRU", "SampleAfterValue": "2000000", "UMask": "0x2" }, { "BriefDescription": "Regen stall cycles", "EventCode": "0x87", "EventName": "ILD_STALL.REGEN", "SampleAfterValue": "2000000", "UMask": "0x8" }, { "BriefDescription": "Instructions that must be decoded by decoder 0", "EventCode": "0x18", "EventName": "INST_DECODED.DEC0", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Instructions written to instruction queue.", "EventCode": "0x17", "EventName": "INST_QUEUE_WRITES", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Cycles instructions are written to the instruction queue", "EventCode": "0x1E", "EventName": "INST_QUEUE_WRITE_CYCLES", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Instructions retired (fixed counter)", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000000" }, { "BriefDescription": "Instructions retired (Programmable counter and Precise Event)", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Retired MMX instructions (Precise Event)", "EventCode": "0xC0", "EventName": "INST_RETIRED.MMX", "PEBS": "1", "SampleAfterValue": "2000000", "UMask": "0x4" }, { "BriefDescription": "Total cycles (Precise Event)", "CounterMask": "16", "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES", "Invert": "1", "PEBS": "1", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Total cycles (Precise Event)", "CounterMask": "16", "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", "Invert": "1", "PEBS": "2", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Retired floating-point operations (Precise Event)", "EventCode": "0xC0", "EventName": "INST_RETIRED.X87", "PEBS": "1", "SampleAfterValue": "2000000", "UMask": "0x2" }, { "BriefDescription": "Load operations conflicting with software prefetches", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE", "SampleAfterValue": "200000", "UMask": "0x1" }, { "BriefDescription": "Cycles when uops were delivered by the LSD", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.ACTIVE", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Cycles no uops were delivered by the LSD", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.INACTIVE", "Invert": "1", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Loops that can't stream from the instruction queue", "EventCode": "0x20", "EventName": "LSD_OVERFLOW", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Cycles machine clear asserted", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "20000", "UMask": "0x1" }, { "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEM_ORDER", "SampleAfterValue": "20000", "UMask": "0x2" }, { "BriefDescription": "Self-Modifying Code detected", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20000", "UMask": "0x4" }, { "BriefDescription": "All RAT stall cycles", "EventCode": "0xD2", "EventName": "RAT_STALLS.ANY", "SampleAfterValue": "2000000", "UMask": "0xf" }, { "BriefDescription": "Flag stall cycles", "EventCode": "0xD2", "EventName": "RAT_STALLS.FLAGS", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Partial register stall cycles", "EventCode": "0xD2", "EventName": "RAT_STALLS.REGISTERS", "SampleAfterValue": "2000000", "UMask": "0x2" }, { "BriefDescription": "ROB read port stalls cycles", "EventCode": "0xD2", "EventName": "RAT_STALLS.ROB_READ_PORT", "SampleAfterValue": "2000000", "UMask": "0x4" }, { "BriefDescription": "Scoreboard stall cycles", "EventCode": "0xD2", "EventName": "RAT_STALLS.SCOREBOARD", "SampleAfterValue": "2000000", "UMask": "0x8" }, { "BriefDescription": "Resource related stall cycles", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "FPU control word write stall cycles", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.FPCW", "SampleAfterValue": "2000000", "UMask": "0x20" }, { "BriefDescription": "Load buffer stall cycles", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LOAD", "SampleAfterValue": "2000000", "UMask": "0x2" }, { "BriefDescription": "MXCSR rename stall cycles", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.MXCSR", "SampleAfterValue": "2000000", "UMask": "0x40" }, { "BriefDescription": "Other Resource related stall cycles", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.OTHER", "SampleAfterValue": "2000000", "UMask": "0x80" }, { "BriefDescription": "ROB full stall cycles", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB_FULL", "SampleAfterValue": "2000000", "UMask": "0x10" }, { "BriefDescription": "Reservation Station full stall cycles", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS_FULL", "SampleAfterValue": "2000000", "UMask": "0x4" }, { "BriefDescription": "Store buffer stall cycles", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.STORE", "SampleAfterValue": "2000000", "UMask": "0x8" }, { "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", "PEBS": "1", "SampleAfterValue": "200000", "UMask": "0x4" }, { "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", "PEBS": "1", "SampleAfterValue": "200000", "UMask": "0x1" }, { "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", "PEBS": "1", "SampleAfterValue": "200000", "UMask": "0x8" }, { "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", "PEBS": "1", "SampleAfterValue": "200000", "UMask": "0x2" }, { "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", "PEBS": "1", "SampleAfterValue": "200000", "UMask": "0x10" }, { "BriefDescription": "Stack pointer instructions decoded", "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_FOLDING", "SampleAfterValue": "2000000", "UMask": "0x4" }, { "BriefDescription": "Stack pointer sync operations", "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_SYNC", "SampleAfterValue": "2000000", "UMask": "0x8" }, { "BriefDescription": "Uops decoded by Microcode Sequencer", "CounterMask": "1", "EventCode": "0xD1", "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", "SampleAfterValue": "2000000", "UMask": "0x2" }, { "BriefDescription": "Cycles no Uops are decoded", "CounterMask": "1", "EventCode": "0xD1", "EventName": "UOPS_DECODED.STALL_CYCLES", "Invert": "1", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "AnyThread": "1", "BriefDescription": "Cycles Uops executed on any port (core count)", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", "SampleAfterValue": "2000000", "UMask": "0x3f" }, { "AnyThread": "1", "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", "SampleAfterValue": "2000000", "UMask": "0x1f" }, { "BriefDescription": "Uops executed on any port (core count)", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", "Invert": "1", "SampleAfterValue": "2000000", "UMask": "0x3f" }, { "BriefDescription": "Uops executed on ports 0-4 (core count)", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", "Invert": "1", "SampleAfterValue": "2000000", "UMask": "0x1f" }, { "AnyThread": "1", "BriefDescription": "Cycles no Uops issued on any port (core count)", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", "Invert": "1", "SampleAfterValue": "2000000", "UMask": "0x3f" }, { "AnyThread": "1", "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", "Invert": "1", "SampleAfterValue": "2000000", "UMask": "0x1f" }, { "BriefDescription": "Uops executed on port 0", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT0", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Uops issued on ports 0, 1 or 5", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015", "SampleAfterValue": "2000000", "UMask": "0x40" }, { "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", "Invert": "1", "SampleAfterValue": "2000000", "UMask": "0x40" }, { "BriefDescription": "Uops executed on port 1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT1", "SampleAfterValue": "2000000", "UMask": "0x2" }, { "AnyThread": "1", "BriefDescription": "Uops issued on ports 2, 3 or 4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT234_CORE", "SampleAfterValue": "2000000", "UMask": "0x80" }, { "AnyThread": "1", "BriefDescription": "Uops executed on port 2 (core count)", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT2_CORE", "SampleAfterValue": "2000000", "UMask": "0x4" }, { "AnyThread": "1", "BriefDescription": "Uops executed on port 3 (core count)", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT3_CORE", "SampleAfterValue": "2000000", "UMask": "0x8" }, { "AnyThread": "1", "BriefDescription": "Uops executed on port 4 (core count)", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT4_CORE", "SampleAfterValue": "2000000", "UMask": "0x10" }, { "BriefDescription": "Uops executed on port 5", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT5", "SampleAfterValue": "2000000", "UMask": "0x20" }, { "BriefDescription": "Uops issued", "EventCode": "0xE", "EventName": "UOPS_ISSUED.ANY", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "AnyThread": "1", "BriefDescription": "Cycles no Uops were issued on any thread", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", "Invert": "1", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "AnyThread": "1", "BriefDescription": "Cycles Uops were issued on either thread", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Fused Uops issued", "EventCode": "0xE", "EventName": "UOPS_ISSUED.FUSED", "SampleAfterValue": "2000000", "UMask": "0x2" }, { "BriefDescription": "Cycles no Uops were issued", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.STALL_CYCLES", "Invert": "1", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Cycles Uops are being retired", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", "PEBS": "1", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Uops retired (Precise Event)", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", "PEBS": "1", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Macro-fused Uops retired (Precise Event)", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MACRO_FUSED", "PEBS": "1", "SampleAfterValue": "2000000", "UMask": "0x4" }, { "BriefDescription": "Retirement slots used (Precise Event)", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", "SampleAfterValue": "2000000", "UMask": "0x2" }, { "BriefDescription": "Cycles Uops are not retiring (Precise Event)", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", "Invert": "1", "PEBS": "1", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Total cycles using precise uop retired event (Precise Event)", "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", "Invert": "1", "PEBS": "1", "SampleAfterValue": "2000000", "UMask": "0x1" }, { "BriefDescription": "Uop unfusions due to FP exceptions", "EventCode": "0xDB", "EventName": "UOP_UNFUSION", "SampleAfterValue": "2000000", "UMask": "0x1" } ]