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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2020 thingy.jp.
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/mstar/mstar,l3bridge.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MStar/SigmaStar Armv7 SoC l3bridge
maintainers:
- Daniel Palmer <daniel@thingy.jp>
description: |
MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface
between the CPU and memory. This means that before DMA capable
devices are allowed to run the pipeline must be flushed to ensure
everything is in memory.
The l3bridge region contains registers that allow such a flush
to be triggered.
This node is used by the platform code to find where the registers
are and install a barrier that triggers the required pipeline flush.
properties:
compatible:
items:
- const: mstar,l3bridge
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
l3bridge: l3bridge@1f204400 {
compatible = "mstar,l3bridge";
reg = <0x1f204400 0x200>;
};
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