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Binding for MediaTek's CPUFreq driver
=====================================
Required properties:
- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
- clock-names: Should contain the following:
"cpu" - The multiplexer for clock input of CPU cluster.
"intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
source (usually MAINPLL) when the original CPU PLL is under
transition and not stable yet.
Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
generic clock consumer properties.
- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
for detail.
- proc-supply: Regulator for Vproc of CPU cluster.
Optional properties:
- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
needs to do "voltage tracking" to step by step scale up/down Vproc and
Vsram to fit SoC specific needs. When absent, the voltage scaling
flow is handled by hardware, hence no software "voltage tracking" is
needed.
- mediatek,cci:
Used to confirm the link status between cpufreq and mediatek cci. Because
cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs.
To prevent the issue of high frequency and low voltage, we need to use this
property to make sure mediatek cci is ready.
For details of mediatek cci, please refer to
Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
- #cooling-cells:
For details, please refer to
Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
Example 1 (MT7623 SoC):
cpu_opp_table: opp_table {
compatible = "operating-points-v2";
opp-shared;
opp-598000000 {
opp-hz = /bits/ 64 <598000000>;
opp-microvolt = <1050000>;
};
opp-747500000 {
opp-hz = /bits/ 64 <747500000>;
opp-microvolt = <1050000>;
};
opp-1040000000 {
opp-hz = /bits/ 64 <1040000000>;
opp-microvolt = <1150000>;
};
opp-1196000000 {
opp-hz = /bits/ 64 <1196000000>;
opp-microvolt = <1200000>;
};
opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1300000>;
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
clocks = <&infracfg CLK_INFRA_CPUSEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
operating-points-v2 = <&cpu_opp_table>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
operating-points-v2 = <&cpu_opp_table>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x3>;
operating-points-v2 = <&cpu_opp_table>;
};
Example 2 (MT8173 SoC):
cpu_opp_table_a: opp_table_a {
compatible = "operating-points-v2";
opp-shared;
opp-507000000 {
opp-hz = /bits/ 64 <507000000>;
opp-microvolt = <859000>;
};
opp-702000000 {
opp-hz = /bits/ 64 <702000000>;
opp-microvolt = <908000>;
};
opp-1001000000 {
opp-hz = /bits/ 64 <1001000000>;
opp-microvolt = <983000>;
};
opp-1105000000 {
opp-hz = /bits/ 64 <1105000000>;
opp-microvolt = <1009000>;
};
opp-1183000000 {
opp-hz = /bits/ 64 <1183000000>;
opp-microvolt = <1028000>;
};
opp-1404000000 {
opp-hz = /bits/ 64 <1404000000>;
opp-microvolt = <1083000>;
};
opp-1508000000 {
opp-hz = /bits/ 64 <1508000000>;
opp-microvolt = <1109000>;
};
opp-1573000000 {
opp-hz = /bits/ 64 <1573000000>;
opp-microvolt = <1125000>;
};
};
cpu_opp_table_b: opp_table_b {
compatible = "operating-points-v2";
opp-shared;
opp-507000000 {
opp-hz = /bits/ 64 <507000000>;
opp-microvolt = <828000>;
};
opp-702000000 {
opp-hz = /bits/ 64 <702000000>;
opp-microvolt = <867000>;
};
opp-1001000000 {
opp-hz = /bits/ 64 <1001000000>;
opp-microvolt = <927000>;
};
opp-1209000000 {
opp-hz = /bits/ 64 <1209000000>;
opp-microvolt = <968000>;
};
opp-1404000000 {
opp-hz = /bits/ 64 <1007000000>;
opp-microvolt = <1028000>;
};
opp-1612000000 {
opp-hz = /bits/ 64 <1612000000>;
opp-microvolt = <1049000>;
};
opp-1807000000 {
opp-hz = /bits/ 64 <1807000000>;
opp-microvolt = <1089000>;
};
opp-1989000000 {
opp-hz = /bits/ 64 <1989000000>;
opp-microvolt = <1125000>;
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x000>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&infracfg CLK_INFRA_CA53SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table_a>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x001>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&infracfg CLK_INFRA_CA53SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table_a>;
};
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&infracfg CLK_INFRA_CA72SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table_b>;
};
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&infracfg CLK_INFRA_CA72SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table_b>;
};
&cpu0 {
proc-supply = <&mt6397_vpca15_reg>;
};
&cpu1 {
proc-supply = <&mt6397_vpca15_reg>;
};
&cpu2 {
proc-supply = <&da9211_vcpu_reg>;
sram-supply = <&mt6397_vsramca7_reg>;
};
&cpu3 {
proc-supply = <&da9211_vcpu_reg>;
sram-supply = <&mt6397_vsramca7_reg>;
};
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