summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
blob: 163fc83c1e80cf07383f9aef510f2f58a26e1ecc (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SM8350 Display MDSS

maintainers:
  - Robert Foss <robert.foss@linaro.org>

description:
  MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like
  DPU display controller, DSI and DP interfaces etc.

$ref: /schemas/display/msm/mdss-common.yaml#

properties:
  compatible:
    items:
      - const: qcom,sm8350-mdss

  clocks:
    items:
      - description: Display AHB clock from gcc
      - description: Display hf axi clock
      - description: Display sf axi clock
      - description: Display core clock

  clock-names:
    items:
      - const: iface
      - const: bus
      - const: nrt_bus
      - const: core

  iommus:
    maxItems: 1

  interconnects:
    maxItems: 2

  interconnect-names:
    items:
      - const: mdp0-mem
      - const: mdp1-mem

patternProperties:
  "^display-controller@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        const: qcom,sm8350-dpu

  "^displayport-controller@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        const: qcom,sm8350-dp

  "^dsi@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        items:
          - const: qcom,sm8350-dsi-ctrl
          - const: qcom,mdss-dsi-ctrl

  "^phy@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        const: qcom,sm8350-dsi-phy-5nm

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
    #include <dt-bindings/clock/qcom,gcc-sm8350.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interconnect/qcom,sm8350.h>
    #include <dt-bindings/power/qcom,rpmhpd.h>

    display-subsystem@ae00000 {
        compatible = "qcom,sm8350-mdss";
        reg = <0x0ae00000 0x1000>;
        reg-names = "mdss";

        interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
                        <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
        interconnect-names = "mdp0-mem", "mdp1-mem";

        power-domains = <&dispcc MDSS_GDSC>;
        resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;

        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                 <&gcc GCC_DISP_HF_AXI_CLK>,
                 <&gcc GCC_DISP_SF_AXI_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
        clock-names = "iface", "bus", "nrt_bus", "core";

        iommus = <&apps_smmu 0x820 0x402>;

        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <1>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        display-controller@ae01000 {
            compatible = "qcom,sm8350-dpu";
            reg = <0x0ae01000 0x8f000>,
                  <0x0aeb0000 0x2008>;
            reg-names = "mdp", "vbif";

            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
                     <&gcc GCC_DISP_SF_AXI_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
            clock-names = "bus",
                          "nrt_bus",
                          "iface",
                          "lut",
                          "core",
                          "vsync";

            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
            assigned-clock-rates = <19200000>;

            operating-points-v2 = <&mdp_opp_table>;
            power-domains = <&rpmhpd RPMHPD_MMCX>;

            interrupt-parent = <&mdss>;
            interrupts = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dpu_intf1_out: endpoint {
                        remote-endpoint = <&dsi0_in>;
                    };
                };
            };

            mdp_opp_table: opp-table {
                compatible = "operating-points-v2";

                opp-200000000 {
                    opp-hz = /bits/ 64 <200000000>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };

                opp-300000000 {
                    opp-hz = /bits/ 64 <300000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };

                opp-345000000 {
                    opp-hz = /bits/ 64 <345000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };

                opp-460000000 {
                    opp-hz = /bits/ 64 <460000000>;
                    required-opps = <&rpmhpd_opp_nom>;
                };
            };
        };

        dsi0: dsi@ae94000 {
            compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
            reg = <0x0ae94000 0x400>;
            reg-names = "dsi_ctrl";

            interrupt-parent = <&mdss>;
            interrupts = <4>;

            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&gcc GCC_DISP_HF_AXI_CLK>;
            clock-names = "byte",
                      "byte_intf",
                      "pixel",
                      "core",
                      "iface",
                      "bus";

            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
                          <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
            assigned-clock-parents = <&mdss_dsi0_phy 0>,
                                 <&mdss_dsi0_phy 1>;

            operating-points-v2 = <&dsi_opp_table>;
            power-domains = <&rpmhpd RPMHPD_MMCX>;

            phys = <&mdss_dsi0_phy>;

            ports {
             #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dsi0_in: endpoint {
                        remote-endpoint = <&dpu_intf1_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dsi0_out: endpoint {
                    };
                };
            };
        };
    };
...