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|
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip SoC Image Signal Processing unit v1
maintainers:
- Helen Koike <helen.koike@collabora.com>
description: |
Rockchip ISP1 is the Camera interface for the Rockchip series of SoCs
which contains image processing, scaling, and compression functions.
properties:
compatible:
enum:
- fsl,imx8mp-isp
- rockchip,px30-cif-isp
- rockchip,rk3399-cif-isp
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 3
interrupt-names:
items:
- const: isp
- const: mi
- const: mipi
clocks:
minItems: 3
items:
# isp0 and isp1
- description: ISP clock (for imx8mp, clk)
- description: ISP AXI clock (for imx8mp, m_hclk)
- description: ISP AHB clock (for imx8mp, hclk)
# only for isp1
- description: ISP Pixel clock
clock-names:
minItems: 3
items:
# isp0 and isp1
- const: isp
- const: aclk
- const: hclk
# only for isp1
- const: pclk
fsl,blk-ctrl:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
description:
A phandle to the media block control for the ISP, followed by a cell
containing the index of the gasket.
iommus:
maxItems: 1
phys:
maxItems: 1
description: phandle for the PHY port
phy-names:
const: dphy
power-domains:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: connection point for sensors at MIPI-DPHY RX0
properties:
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 4
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: connection point for input on the parallel interface
properties:
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
bus-type:
enum: [5, 6]
required:
- bus-type
anyOf:
- required:
- port@0
- required:
- port@1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- power-domains
- ports
allOf:
- if:
properties:
compatible:
contains:
const: rockchip,rk3399-cif-isp
then:
properties:
clocks:
minItems: 3
maxItems: 4
clock-names:
minItems: 3
maxItems: 4
- if:
properties:
compatible:
contains:
const: rockchip,px30-cif-isp
then:
required:
- interrupt-names
- if:
properties:
compatible:
contains:
const: fsl,imx8mp-isp
then:
properties:
iommus: false
phys: false
phy-names: false
required:
- fsl,blk-ctrl
else:
properties:
fsl,blk-ctrl: false
required:
- iommus
- phys
- phy-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/rk3399-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/rk3399-power.h>
parent0: parent {
#address-cells = <2>;
#size-cells = <2>;
isp0: isp0@ff910000 {
compatible = "rockchip,rk3399-cif-isp";
reg = <0x0 0xff910000 0x0 0x4000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_ISP0>,
<&cru ACLK_ISP0_WRAPPER>,
<&cru HCLK_ISP0_WRAPPER>;
clock-names = "isp", "aclk", "hclk";
iommus = <&isp0_mmu>;
phys = <&dphy>;
phy-names = "dphy";
power-domains = <&power RK3399_PD_ISP0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_wcam: endpoint@0 {
reg = <0>;
remote-endpoint = <&wcam_out>;
data-lanes = <1 2>;
};
mipi_in_ucam: endpoint@1 {
reg = <1>;
remote-endpoint = <&ucam_out>;
data-lanes = <1>;
};
};
};
};
i2c7: i2c {
#address-cells = <1>;
#size-cells = <0>;
wcam: camera@36 {
compatible = "ovti,ov5695";
reg = <0x36>;
clocks = <&cru SCLK_TESTCLKOUT1>;
port {
wcam_out: endpoint {
remote-endpoint = <&mipi_in_wcam>;
data-lanes = <1 2>;
};
};
};
ucam: camera@3c {
compatible = "ovti,ov2685";
reg = <0x3c>;
clocks = <&cru SCLK_TESTCLKOUT1>;
clock-names = "xvclk";
avdd-supply = <&pp2800_cam>;
dovdd-supply = <&pp1800>;
dvdd-supply = <&pp1800>;
port {
ucam_out: endpoint {
remote-endpoint = <&mipi_in_ucam>;
data-lanes = <1>;
};
};
};
};
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/px30-power.h>
parent1: parent {
#address-cells = <2>;
#size-cells = <2>;
isp: isp@ff4a0000 {
compatible = "rockchip,px30-cif-isp";
reg = <0x0 0xff4a0000 0x0 0x8000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "isp", "mi", "mipi";
clocks = <&cru SCLK_ISP0>,
<&cru ACLK_ISP0_WRAPPER>,
<&cru HCLK_ISP0_WRAPPER>,
<&cru PCLK_ISP1_WRAPPER>;
clock-names = "isp", "aclk", "hclk", "pclk";
iommus = <&isp_mmu>;
phys = <&csi_dphy>;
phy-names = "dphy";
power-domains = <&power PX30_PD_VI>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ucam1: endpoint@0 {
reg = <0>;
remote-endpoint = <&ucam1_out>;
data-lanes = <1 2>;
};
};
};
};
i2c2: i2c {
#address-cells = <1>;
#size-cells = <0>;
ov5695: camera@36 {
compatible = "ovti,ov5647";
reg = <0x36>;
clocks = <&cru SCLK_CIF_OUT>;
port {
ucam1_out: endpoint {
remote-endpoint = <&mipi_in_ucam1>;
data-lanes = <1 2>;
};
};
};
};
};
|
