1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SDHCI controller (sdhci-msm)
maintainers:
- Bhupesh Sharma <bhupesh.sharma@linaro.org>
description:
Secure Digital Host Controller Interface (SDHCI) present on
Qualcomm SOCs supports SD/MMC/SDIO devices.
properties:
compatible:
oneOf:
- enum:
- qcom,sdhci-msm-v4
deprecated: true
- items:
- enum:
- qcom,apq8084-sdhci
- qcom,msm8226-sdhci
- qcom,msm8953-sdhci
- qcom,msm8974-sdhci
- qcom,msm8976-sdhci
- qcom,msm8916-sdhci
- qcom,msm8992-sdhci
- qcom,msm8994-sdhci
- qcom,msm8996-sdhci
- qcom,msm8998-sdhci
- const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
- items:
- enum:
- qcom,ipq5018-sdhci
- qcom,ipq5332-sdhci
- qcom,ipq6018-sdhci
- qcom,ipq9574-sdhci
- qcom,qcm2290-sdhci
- qcom,qcs404-sdhci
- qcom,qdu1000-sdhci
- qcom,sc7180-sdhci
- qcom,sc7280-sdhci
- qcom,sc8280xp-sdhci
- qcom,sdm630-sdhci
- qcom,sdm670-sdhci
- qcom,sdm845-sdhci
- qcom,sdx55-sdhci
- qcom,sdx65-sdhci
- qcom,sm6115-sdhci
- qcom,sm6125-sdhci
- qcom,sm6350-sdhci
- qcom,sm6375-sdhci
- qcom,sm8150-sdhci
- qcom,sm8250-sdhci
- qcom,sm8350-sdhci
- qcom,sm8450-sdhci
- qcom,sm8550-sdhci
- const: qcom,sdhci-msm-v5 # for sdcc version 5.0
reg:
minItems: 1
maxItems: 4
reg-names:
minItems: 1
maxItems: 4
clocks:
minItems: 2
items:
- description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
- description: SDC MMC clock, MCLK
- description: TCXO clock
- description: clock for Inline Crypto Engine
- description: SDCC bus voter clock
- description: reference clock for RCLK delay calibration
- description: sleep clock for RCLK delay calibration
clock-names:
minItems: 2
items:
- const: iface
- const: core
- const: xo
- const: ice
- const: bus
- const: cal
- const: sleep
dma-coherent: true
interrupts:
maxItems: 2
interrupt-names:
items:
- const: hc_irq
- const: pwr_irq
pinctrl-names:
minItems: 1
items:
- const: default
- const: sleep
pinctrl-0:
description:
Should specify pin control groups used for this controller.
pinctrl-1:
description:
Should specify sleep pin control groups used for this controller.
resets:
maxItems: 1
qcom,ddr-config:
$ref: /schemas/types.yaml#/definitions/uint32
description: platform specific settings for DDR_CONFIG reg.
qcom,dll-config:
$ref: /schemas/types.yaml#/definitions/uint32
description: platform specific settings for DLL_CONFIG reg.
iommus:
minItems: 1
maxItems: 8
description: |
phandle to apps_smmu node with sid mask.
interconnects:
minItems: 1
items:
- description: data path, sdhc to ddr
- description: config path, cpu to sdhc
interconnect-names:
minItems: 1
items:
- const: sdhc-ddr
- const: cpu-sdhc
power-domains:
description: A phandle to sdhci power domain node
maxItems: 1
operating-points-v2: true
patternProperties:
'^opp-table(-[a-z0-9]+)?$':
if:
properties:
compatible:
const: operating-points-v2
then:
patternProperties:
'^opp-?[0-9]+$':
required:
- required-opps
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
allOf:
- $ref: sdhci-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,sdhci-msm-v4
then:
properties:
reg:
minItems: 2
items:
- description: Host controller register map
- description: SD Core register map
- description: CQE register map
- description: Inline Crypto Engine register map
reg-names:
minItems: 2
items:
- const: hc
- const: core
- const: cqhci
- const: ice
else:
properties:
reg:
minItems: 1
items:
- description: Host controller register map
- description: CQE register map
- description: Inline Crypto Engine register map
reg-names:
minItems: 1
items:
- const: hc
- const: cqhci
- const: ice
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
sdhc_2: mmc@8804000 {
compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "core", "xo";
iommus = <&apps_smmu 0x4a0 0x0>;
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&sdhc2_opp_table>;
sdhc2_opp_table: opp-table {
compatible = "operating-points-v2";
opp-19200000 {
opp-hz = /bits/ 64 <19200000>;
required-opps = <&rpmhpd_opp_min_svs>;
};
opp-50000000 {
opp-hz = /bits/ 64 <50000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
};
|
