summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml
blob: 7b7f840ffc4cf1eaef61affdb8c4bfeb1c9ed3af (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Nuvoton WPCM450 pin control and GPIO

maintainers:
  - Jonathan Neuschäfer <j.neuschaefer@gmx.net>

properties:
  compatible:
    const: nuvoton,wpcm450-pinctrl

  reg:
    maxItems: 1

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

patternProperties:
  # There are three kinds of subnodes:
  # 1. a GPIO controller node for each GPIO bank
  # 2. a pinmux node configures pin muxing for a group of pins (e.g. rmii2)
  # 3. a pinconf node configures properties of a single pin

  "^gpio@[0-7]$":
    type: object
    additionalProperties: false

    description:
      Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18
      GPIOs. Some GPIOs support interrupts.

    properties:
      reg:
        minimum: 0
        maximum: 7

      gpio-controller: true

      "#gpio-cells":
        const: 2

      interrupt-controller: true

      "#interrupt-cells":
        const: 2

      interrupts:
        maxItems: 3
        description:
          The interrupts associated with this GPIO bank

    required:
      - reg
      - gpio-controller
      - '#gpio-cells'

  "^mux-":
    $ref: pinmux-node.yaml#

    properties:
      groups:
        description:
          One or more groups of pins to mux to a certain function
        items:
          enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,
                  hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo,
                  clko, smi, uinc, gspi, mben, xcs2, xcs1, sdio, sspi, fi0,
                  fi1, fi2, fi3, fi4, fi5, fi6, fi7, fi8, fi9, fi10, fi11,
                  fi12, fi13, fi14, fi15, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5,
                  pwm6, pwm7, hg0, hg1, hg2, hg3, hg4, hg5, hg6, hg7 ]
      function:
        description:
          The function that a group of pins is muxed to
        enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,
                hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo0,
                dvo1, dvo2, dvo3, dvo4, dvo5, dvo6, dvo7, clko, smi, uinc,
                gspi, mben, xcs2, xcs1, sdio, sspi, fi0, fi1, fi2, fi3, fi4,
                fi5, fi6, fi7, fi8, fi9, fi10, fi11, fi12, fi13, fi14, fi15,
                pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, hg0, hg1,
                hg2, hg3, hg4, hg5, hg6, hg7, gpio ]

    dependencies:
      groups: [ function ]
      function: [ groups ]

    additionalProperties: false

  "^cfg-":
    $ref: pincfg-node.yaml#

    properties:
      pins:
        description:
          A list of pins to configure in certain ways, such as enabling
          debouncing
        items:
          pattern: "^gpio1?[0-9]{1,2}$"

      input-debounce: true

    additionalProperties: false

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/gpio/gpio.h>
    pinctrl: pinctrl@b8003000 {
      compatible = "nuvoton,wpcm450-pinctrl";
      reg = <0xb8003000 0x1000>;
      #address-cells = <1>;
      #size-cells = <0>;

      gpio0: gpio@0 {
        reg = <0>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
                     <3 IRQ_TYPE_LEVEL_HIGH>,
                     <4 IRQ_TYPE_LEVEL_HIGH>;
      };

      mux-rmii2 {
        groups = "rmii2";
        function = "rmii2";
      };

      pinmux_uid: mux-uid {
        groups = "gspi", "sspi";
        function = "gpio";
      };

      pinctrl_uid: cfg-uid {
        pins = "gpio14";
        input-debounce = <1>;
      };
    };

    gpio-keys {
      compatible = "gpio-keys";
      pinctrl-names = "default";
      pinctrl-0 = <&pinctrl_uid>, <&pinmux_uid>;

      button-uid {
        label = "UID";
        linux,code = <102>;
        gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
      };
    };