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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8150-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM8150 TLMM pin controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description:
Top Level Mode Multiplexer pin controller in Qualcomm SM8150 SoC.
properties:
compatible:
const: qcom,sm8150-pinctrl
reg:
maxItems: 4
reg-names:
items:
- const: west
- const: east
- const: north
- const: south
interrupts:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 88
gpio-line-names:
maxItems: 175
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-sm8150-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-sm8150-tlmm-state"
additionalProperties: false
$defs:
qcom-sm8150-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
atest_char0, atest_char1, atest_char2, atest_char3, audio_ref,
atest_usb1, atest_usb2, atest_usb10, atest_usb11, atest_usb12,
atest_usb13, atest_usb20, atest_usb21, atest_usb22,
atest_usb23, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd, emac_phy, emac_pps,
gcc_gp1, gcc_gp2, gcc_gp3, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s,
jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator,
pci_e0, phase_flag, pll_bypassnl, pll_bist, pci_e1, pll_reset,
pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti,
qlink_request, qlink_enable, qspi0, qspi1, qspi2, qspi3,
qspi_clk, qspi_cs, qua_mi2s, qup0, qup1, qup2, qup3, qup4,
qup5, qup6, qup7, qup8, qup9, qup10, qup11, qup12, qup13,
qup14, qup15, qup16, qup17, qup18, qup19, qup_l4, qup_l5,
qup_l6, rgmii, sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu,
ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt, usb2phy_ac,
usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
wlan2_adc0, wlan2_adc1, wmss_reset ]
required:
- pins
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
required:
- compatible
- reg
- reg-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@3100000 {
compatible = "qcom,sm8150-pinctrl";
reg = <0x03100000 0x300000>,
<0x03500000 0x300000>,
<0x03900000 0x300000>,
<0x03d00000 0x300000>;
reg-names = "west", "east", "north", "south";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&tlmm 0 0 176>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
qup-spi0-default-state {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "qup0";
drive-strength = <6>;
bias-disable;
};
pcie1-default-state {
perst-pins {
pins = "gpio102";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq-pins {
pins = "gpio103";
function = "pci_e1";
drive-strength = <2>;
bias-pull-up;
};
wake-pins {
pins = "gpio104";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};
|
