summaryrefslogtreecommitdiffstats
path: root/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
blob: 6315ffa6c1bb9b6e41d528210a8ebdf9c0fa1c93 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for the RZ/G3S SoC
 *
 * Copyright (C) 2023 Renesas Electronics Corp.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a08g045-cpg.h>

/ {
	compatible = "renesas,r9a08g045";
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a55";
			reg = <0>;
			device_type = "cpu";
			#cooling-cells = <2>;
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
		};

		L3_CA55: cache-controller-0 {
			compatible = "cache";
			cache-level = <3>;
			cache-unified;
			cache-size = <0x40000>;
		};
	};

	extal_clk: extal-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board. */
		clock-frequency = <0>;
	};

	soc: soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		scif0: serial@1004b800 {
			compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
			reg = <0 0x1004b800 0 0x400>;
			interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi",
					  "bri", "dri", "tei";
			clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
			clock-names = "fck";
			power-domains = <&cpg>;
			resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
			status = "disabled";
		};

		cpg: clock-controller@11010000 {
			compatible = "renesas,r9a08g045-cpg";
			reg = <0 0x11010000 0 0x10000>;
			clocks = <&extal_clk>;
			clock-names = "extal";
			#clock-cells = <2>;
			#reset-cells = <1>;
			#power-domain-cells = <0>;
		};

		sysc: system-controller@11020000 {
			compatible = "renesas,r9a08g045-sysc";
			reg = <0 0x11020000 0 0x10000>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "lpm_int", "ca55stbydone_int",
					  "cm33stbyr_int", "ca55_deny";
			status = "disabled";
		};

		pinctrl: pinctrl@11030000 {
			compatible = "renesas,r9a08g045-pinctrl";
			reg = <0 0x11030000 0 0x10000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&irqc>;
			gpio-ranges = <&pinctrl 0 0 152>;
			clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
			power-domains = <&cpg>;
			resets = <&cpg R9A08G045_GPIO_RSTN>,
				 <&cpg R9A08G045_GPIO_PORT_RESETN>,
				 <&cpg R9A08G045_GPIO_SPARE_RESETN>;
		};

		irqc: interrupt-controller@11050000 {
			compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc";
			#interrupt-cells = <2>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0 0x11050000 0 0x10000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "nmi",
					  "irq0", "irq1", "irq2", "irq3",
					  "irq4", "irq5", "irq6", "irq7",
					  "tint0", "tint1", "tint2", "tint3",
					  "tint4", "tint5", "tint6", "tint7",
					  "tint8", "tint9", "tint10", "tint11",
					  "tint12", "tint13", "tint14", "tint15",
					  "tint16", "tint17", "tint18", "tint19",
					  "tint20", "tint21", "tint22", "tint23",
					  "tint24", "tint25", "tint26", "tint27",
					  "tint28", "tint29", "tint30", "tint31",
					  "bus-err", "ec7tie1-0", "ec7tie2-0",
					  "ec7tiovf-0";
			clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
				 <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
			clock-names = "clk", "pclk";
			power-domains = <&cpg>;
			resets = <&cpg R9A08G045_IA55_RESETN>;
		};

		sdhi0: mmc@11c00000  {
			compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
			reg = <0x0 0x11c00000 0 0x10000>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>,
				 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>,
				 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>,
				 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
			clock-names = "core", "clkh", "cd", "aclk";
			resets = <&cpg R9A08G045_SDHI0_IXRST>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		sdhi1: mmc@11c10000 {
			compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
			reg = <0x0 0x11c10000 0 0x10000>;
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>,
				 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>,
				 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>,
				 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
			clock-names = "core", "clkh", "cd", "aclk";
			resets = <&cpg R9A08G045_SDHI1_IXRST>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		sdhi2: mmc@11c20000 {
			compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
			reg = <0x0 0x11c20000 0 0x10000>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>,
				 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>,
				 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>,
				 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
			clock-names = "core", "clkh", "cd", "aclk";
			resets = <&cpg R9A08G045_SDHI2_IXRST>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		eth0: ethernet@11c30000 {
			compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
			reg = <0 0x11c30000 0 0x10000>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "mux", "fil", "arp_ns";
			phy-mode = "rgmii";
			clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
				 <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
				 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
			clock-names = "axi", "chi", "refclk";
			resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
			power-domains = <&cpg>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		eth1: ethernet@11c40000 {
			compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
			reg = <0 0x11c40000 0 0x10000>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "mux", "fil", "arp_ns";
			phy-mode = "rgmii";
			clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>,
				 <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>,
				 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
			clock-names = "axi", "chi", "refclk";
			resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
			power-domains = <&cpg>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		gic: interrupt-controller@12400000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x0 0x12400000 0 0x40000>,
			      <0x0 0x12440000 0 0x60000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};
};