blob: 236051364f78e2e7586a3fc2097e0a55de2de36e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
|
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1985 MIPS Computer Systems, Inc.
* Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
* Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
* Copyright (C) 2011 Wind River Systems,
* written by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef _ASM_REGDEF_H
#define _ASM_REGDEF_H
#include <asm/sgidefs.h>
#if _MIPS_SIM == _MIPS_SIM_ABI32
/*
* General purpose register numbers for 32 bit ABI
*/
#define GPR_ZERO 0 /* wired zero */
#define GPR_AT 1 /* assembler temp */
#define GPR_V0 2 /* return value */
#define GPR_V1 3
#define GPR_A0 4 /* argument registers */
#define GPR_A1 5
#define GPR_A2 6
#define GPR_A3 7
#define GPR_T0 8 /* caller saved */
#define GPR_T1 9
#define GPR_T2 10
#define GPR_T3 11
#define GPR_T4 12
#define GPR_TA0 12
#define GPR_T5 13
#define GPR_TA1 13
#define GPR_T6 14
#define GPR_TA2 14
#define GPR_T7 15
#define GPR_TA3 15
#define GPR_S0 16 /* callee saved */
#define GPR_S1 17
#define GPR_S2 18
#define GPR_S3 19
#define GPR_S4 20
#define GPR_S5 21
#define GPR_S6 22
#define GPR_S7 23
#define GPR_T8 24 /* caller saved */
#define GPR_T9 25
#define GPR_JP 25 /* PIC jump register */
#define GPR_K0 26 /* kernel scratch */
#define GPR_K1 27
#define GPR_GP 28 /* global pointer */
#define GPR_SP 29 /* stack pointer */
#define GPR_FP 30 /* frame pointer */
#define GPR_S8 30 /* same like fp! */
#define GPR_RA 31 /* return address */
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
#define GPR_ZERO 0 /* wired zero */
#define GPR_AT 1 /* assembler temp */
#define GPR_V0 2 /* return value - caller saved */
#define GPR_V1 3
#define GPR_A0 4 /* argument registers */
#define GPR_A1 5
#define GPR_A2 6
#define GPR_A3 7
#define GPR_A4 8 /* arg reg 64 bit; caller saved in 32 bit */
#define GPR_TA0 8
#define GPR_A5 9
#define GPR_TA1 9
#define GPR_A6 10
#define GPR_TA2 10
#define GPR_A7 11
#define GPR_TA3 11
#define GPR_T0 12 /* caller saved */
#define GPR_T1 13
#define GPR_T2 14
#define GPR_T3 15
#define GPR_S0 16 /* callee saved */
#define GPR_S1 17
#define GPR_S2 18
#define GPR_S3 19
#define GPR_S4 20
#define GPR_S5 21
#define GPR_S6 22
#define GPR_S7 23
#define GPR_T8 24 /* caller saved */
#define GPR_T9 25 /* callee address for PIC/temp */
#define GPR_JP 25 /* PIC jump register */
#define GPR_K0 26 /* kernel temporary */
#define GPR_K1 27
#define GPR_GP 28 /* global pointer - caller saved for PIC */
#define GPR_SP 29 /* stack pointer */
#define GPR_FP 30 /* frame pointer */
#define GPR_S8 30 /* callee saved */
#define GPR_RA 31 /* return address */
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
#ifdef __ASSEMBLY__
#if _MIPS_SIM == _MIPS_SIM_ABI32
/*
* Symbolic register names for 32 bit ABI
*/
#define zero $0 /* wired zero */
#define AT $1 /* assembler temp - uppercase because of ".set at" */
#define v0 $2 /* return value */
#define v1 $3
#define a0 $4 /* argument registers */
#define a1 $5
#define a2 $6
#define a3 $7
#define t0 $8 /* caller saved */
#define t1 $9
#define t2 $10
#define t3 $11
#define t4 $12
#define ta0 $12
#define t5 $13
#define ta1 $13
#define t6 $14
#define ta2 $14
#define t7 $15
#define ta3 $15
#define s0 $16 /* callee saved */
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24 /* caller saved */
#define t9 $25
#define jp $25 /* PIC jump register */
#define k0 $26 /* kernel scratch */
#define k1 $27
#define gp $28 /* global pointer */
#define sp $29 /* stack pointer */
#define fp $30 /* frame pointer */
#define s8 $30 /* same like fp! */
#define ra $31 /* return address */
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
#define zero $0 /* wired zero */
#define AT $at /* assembler temp - uppercase because of ".set at" */
#define v0 $2 /* return value - caller saved */
#define v1 $3
#define a0 $4 /* argument registers */
#define a1 $5
#define a2 $6
#define a3 $7
#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */
#define ta0 $8
#define a5 $9
#define ta1 $9
#define a6 $10
#define ta2 $10
#define a7 $11
#define ta3 $11
#define t0 $12 /* caller saved */
#define t1 $13
#define t2 $14
#define t3 $15
#define s0 $16 /* callee saved */
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24 /* caller saved */
#define t9 $25 /* callee address for PIC/temp */
#define jp $25 /* PIC jump register */
#define k0 $26 /* kernel temporary */
#define k1 $27
#define gp $28 /* global pointer - caller saved for PIC */
#define sp $29 /* stack pointer */
#define fp $30 /* frame pointer */
#define s8 $30 /* callee saved */
#define ra $31 /* return address */
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
#endif /* __ASSEMBLY__ */
#endif /* _ASM_REGDEF_H */
|
