blob: 50847cccdf583e795d66b6bae1e0fcf5b895cda4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <vireshk@kernel.org>
*
* SPEAr clk - Common routines
*/
#include <linux/clk-provider.h>
#include <linux/types.h>
#include "clk.h"
long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt,
int *index)
{
unsigned long prev_rate, rate = 0;
for (*index = 0; *index < rtbl_cnt; (*index)++) {
prev_rate = rate;
rate = calc_rate(hw, parent_rate, *index);
if (drate < rate) {
/* previous clock was best */
if (*index) {
rate = prev_rate;
(*index)--;
}
break;
}
}
if ((*index) == rtbl_cnt)
(*index)--;
return rate;
}
|