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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/* Copyright (c) 2023 Imagination Technologies Ltd. */
#ifndef __PVR_ROGUE_FWIF_DEV_INFO_H__
#define __PVR_ROGUE_FWIF_DEV_INFO_H__
enum {
PVR_FW_HAS_BRN_44079 = 0,
PVR_FW_HAS_BRN_47217,
PVR_FW_HAS_BRN_48492,
PVR_FW_HAS_BRN_48545,
PVR_FW_HAS_BRN_49927,
PVR_FW_HAS_BRN_50767,
PVR_FW_HAS_BRN_51764,
PVR_FW_HAS_BRN_62269,
PVR_FW_HAS_BRN_63142,
PVR_FW_HAS_BRN_63553,
PVR_FW_HAS_BRN_66011,
PVR_FW_HAS_BRN_71242,
PVR_FW_HAS_BRN_MAX
};
enum {
PVR_FW_HAS_ERN_35421 = 0,
PVR_FW_HAS_ERN_38020,
PVR_FW_HAS_ERN_38748,
PVR_FW_HAS_ERN_42064,
PVR_FW_HAS_ERN_42290,
PVR_FW_HAS_ERN_42606,
PVR_FW_HAS_ERN_47025,
PVR_FW_HAS_ERN_57596,
PVR_FW_HAS_ERN_MAX
};
enum {
PVR_FW_HAS_FEATURE_AXI_ACELITE = 0,
PVR_FW_HAS_FEATURE_CDM_CONTROL_STREAM_FORMAT,
PVR_FW_HAS_FEATURE_CLUSTER_GROUPING,
PVR_FW_HAS_FEATURE_COMMON_STORE_SIZE_IN_DWORDS,
PVR_FW_HAS_FEATURE_COMPUTE,
PVR_FW_HAS_FEATURE_COMPUTE_MORTON_CAPABLE,
PVR_FW_HAS_FEATURE_COMPUTE_OVERLAP,
PVR_FW_HAS_FEATURE_COREID_PER_OS,
PVR_FW_HAS_FEATURE_DYNAMIC_DUST_POWER,
PVR_FW_HAS_FEATURE_ECC_RAMS,
PVR_FW_HAS_FEATURE_FBCDC,
PVR_FW_HAS_FEATURE_FBCDC_ALGORITHM,
PVR_FW_HAS_FEATURE_FBCDC_ARCHITECTURE,
PVR_FW_HAS_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS,
PVR_FW_HAS_FEATURE_FBC_MAX_LARGE_DESCRIPTORS,
PVR_FW_HAS_FEATURE_FB_CDC_V4,
PVR_FW_HAS_FEATURE_GPU_MULTICORE_SUPPORT,
PVR_FW_HAS_FEATURE_GPU_VIRTUALISATION,
PVR_FW_HAS_FEATURE_GS_RTA_SUPPORT,
PVR_FW_HAS_FEATURE_IRQ_PER_OS,
PVR_FW_HAS_FEATURE_ISP_MAX_TILES_IN_FLIGHT,
PVR_FW_HAS_FEATURE_ISP_SAMPLES_PER_PIXEL,
PVR_FW_HAS_FEATURE_ISP_ZLS_D24_S8_PACKING_OGL_MODE,
PVR_FW_HAS_FEATURE_LAYOUT_MARS,
PVR_FW_HAS_FEATURE_MAX_PARTITIONS,
PVR_FW_HAS_FEATURE_META,
PVR_FW_HAS_FEATURE_META_COREMEM_SIZE,
PVR_FW_HAS_FEATURE_MIPS,
PVR_FW_HAS_FEATURE_NUM_CLUSTERS,
PVR_FW_HAS_FEATURE_NUM_ISP_IPP_PIPES,
PVR_FW_HAS_FEATURE_NUM_OSIDS,
PVR_FW_HAS_FEATURE_NUM_RASTER_PIPES,
PVR_FW_HAS_FEATURE_PBE2_IN_XE,
PVR_FW_HAS_FEATURE_PBVNC_COREID_REG,
PVR_FW_HAS_FEATURE_PERFBUS,
PVR_FW_HAS_FEATURE_PERF_COUNTER_BATCH,
PVR_FW_HAS_FEATURE_PHYS_BUS_WIDTH,
PVR_FW_HAS_FEATURE_RISCV_FW_PROCESSOR,
PVR_FW_HAS_FEATURE_ROGUEXE,
PVR_FW_HAS_FEATURE_S7_TOP_INFRASTRUCTURE,
PVR_FW_HAS_FEATURE_SIMPLE_INTERNAL_PARAMETER_FORMAT,
PVR_FW_HAS_FEATURE_SIMPLE_INTERNAL_PARAMETER_FORMAT_V2,
PVR_FW_HAS_FEATURE_SIMPLE_PARAMETER_FORMAT_VERSION,
PVR_FW_HAS_FEATURE_SLC_BANKS,
PVR_FW_HAS_FEATURE_SLC_CACHE_LINE_SIZE_BITS,
PVR_FW_HAS_FEATURE_SLC_SIZE_CONFIGURABLE,
PVR_FW_HAS_FEATURE_SLC_SIZE_IN_KILOBYTES,
PVR_FW_HAS_FEATURE_SOC_TIMER,
PVR_FW_HAS_FEATURE_SYS_BUS_SECURE_RESET,
PVR_FW_HAS_FEATURE_TESSELLATION,
PVR_FW_HAS_FEATURE_TILE_REGION_PROTECTION,
PVR_FW_HAS_FEATURE_TILE_SIZE_X,
PVR_FW_HAS_FEATURE_TILE_SIZE_Y,
PVR_FW_HAS_FEATURE_TLA,
PVR_FW_HAS_FEATURE_TPU_CEM_DATAMASTER_GLOBAL_REGISTERS,
PVR_FW_HAS_FEATURE_TPU_DM_GLOBAL_REGISTERS,
PVR_FW_HAS_FEATURE_TPU_FILTERING_MODE_CONTROL,
PVR_FW_HAS_FEATURE_USC_MIN_OUTPUT_REGISTERS_PER_PIX,
PVR_FW_HAS_FEATURE_VDM_DRAWINDIRECT,
PVR_FW_HAS_FEATURE_VDM_OBJECT_LEVEL_LLS,
PVR_FW_HAS_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS,
PVR_FW_HAS_FEATURE_WATCHDOG_TIMER,
PVR_FW_HAS_FEATURE_WORKGROUP_PROTECTION,
PVR_FW_HAS_FEATURE_XE_ARCHITECTURE,
PVR_FW_HAS_FEATURE_XE_MEMORY_HIERARCHY,
PVR_FW_HAS_FEATURE_XE_TPU2,
PVR_FW_HAS_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH,
PVR_FW_HAS_FEATURE_XPU_MAX_SLAVES,
PVR_FW_HAS_FEATURE_XPU_REGISTER_BROADCAST,
PVR_FW_HAS_FEATURE_XT_TOP_INFRASTRUCTURE,
PVR_FW_HAS_FEATURE_ZLS_SUBTILE,
PVR_FW_HAS_FEATURE_MAX
};
#endif /* __PVR_ROGUE_FWIF_DEV_INFO_H__ */
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