summaryrefslogtreecommitdiffstats
path: root/drivers/soc/mediatek/mt8195-mmsys.h
blob: 9be2df2832a4797b8c78c4462a230021d8419a18 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
#define __SOC_MEDIATEK_MT8195_MMSYS_H

#define MT8195_VDO0_OVL_MOUT_EN					0xf14
#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			BIT(0)
#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			BIT(1)
#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			BIT(2)
#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			BIT(4)
#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			BIT(5)
#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			BIT(6)

#define MT8195_VDO0_SEL_IN					0xf34
#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK			GENMASK(1, 0)
#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT		(0 << 0)
#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1		(1 << 0)
#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0		(2 << 0)
#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK			GENMASK(4, 4)
#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0		(0 << 4)
#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE		(1 << 4)
#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK			GENMASK(5, 5)
#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1		(0 << 5)
#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE		(1 << 5)
#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK			GENMASK(8, 8)
#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE		(0 << 8)
#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT		(1 << 8)
#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK			GENMASK(9, 9)
#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT		(0 << 9)
#define MT8195_SEL_IN_DP_INTF0_FROM_MASK			GENMASK(13, 12)
#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT		(0 << 0)
#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE			(1 << 12)
#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0		(2 << 12)
#define MT8195_SEL_IN_DSI0_FROM_MASK				GENMASK(16, 16)
#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT			(0 << 16)
#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0			(1 << 16)
#define MT8195_SEL_IN_DSI1_FROM_MASK				GENMASK(17, 17)
#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT			(0 << 17)
#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE			(1 << 17)
#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK			GENMASK(20, 20)
#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			(0 << 20)
#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			(1 << 20)
#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK			GENMASK(21, 21)
#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN		(0 << 21)
#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1		(1 << 21)
#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK			GENMASK(22, 22)
#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			(0 << 22)

#define MT8195_VDO0_SEL_OUT					0xf38
#define MT8195_SOUT_DISP_DITHER0_TO_MASK			BIT(0)
#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN		(0 << 0)
#define MT8195_SOUT_DISP_DITHER0_TO_DSI0			(1 << 0)
#define MT8195_SOUT_DISP_DITHER1_TO_MASK			GENMASK(2, 1)
#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN		(0 << 1)
#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE			(1 << 1)
#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT		(2 << 1)
#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK			GENMASK(4, 4)
#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE			(0 << 4)
#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0			(1 << 4)
#define MT8195_SOUT_VPP_MERGE_TO_MASK				GENMASK(10, 8)
#define MT8195_SOUT_VPP_MERGE_TO_DSI1				(0 << 8)
#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0			(1 << 8)
#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0			(2 << 8)
#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1			(3 << 8)
#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN			(4 << 8)
#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK		GENMASK(11, 11)
#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN			(0 << 11)
#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK			GENMASK(13, 12)
#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0			(0 << 12)
#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0		(1 << 12)
#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE			(2 << 12)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK			GENMASK(17, 16)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1			(0 << 16)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0			(1 << 16)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)

#define MT8195_VDO1_SW0_RST_B					0x1d0
#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD				0xe30
#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD				0xe70
#define MT8195_VDO1_HDR_TOP_CFG					0xd00
#define MT8195_VDO1_MIXER_IN1_ALPHA				0xd30
#define MT8195_VDO1_MIXER_IN1_PAD				0xd40

#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN			0xf04
#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0			1

#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN			0xf08
#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1			1

#define MT8195_VDO1_DISP_DPI1_SEL_IN				0xf10
#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT			0

#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN			0xf14
#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT		0

#define MT8195_VDO1_MERGE4_SOUT_SEL				0xf18
#define MT8195_MERGE4_SOUT_TO_DPI1_SEL					2
#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL				3

#define MT8195_VDO1_MIXER_IN1_SEL_IN				0xf24
#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT			1

#define MT8195_VDO1_MIXER_IN2_SEL_IN				0xf28
#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT			1

#define MT8195_VDO1_MIXER_IN3_SEL_IN				0xf2c
#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT			1

#define MT8195_VDO1_MIXER_IN4_SEL_IN				0xf30
#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT			1

#define MT8195_VDO1_MIXER_OUT_SOUT_SEL				0xf34
#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL				1

#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN			0xf3c
#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2			1

#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL			0xf40
#define MT8195_SOUT_TO_MIXER_IN1_SEL					1

#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL			0xf44
#define MT8195_SOUT_TO_MIXER_IN2_SEL					1

#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL			0xf48
#define MT8195_SOUT_TO_MIXER_IN3_SEL					1

#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL			0xf4c
#define MT8195_SOUT_TO_MIXER_IN4_SEL					1

#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN				0xf50
#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT			1

#define MT8195_VDO1_MIXER_IN1_SOUT_SEL				0xf58
#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER				0

#define MT8195_VDO1_MIXER_IN2_SOUT_SEL				0xf5c
#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER				0

#define MT8195_VDO1_MIXER_IN3_SOUT_SEL				0xf60
#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER				0

#define MT8195_VDO1_MIXER_IN4_SOUT_SEL				0xf64
#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER				0

#define MT8195_VDO1_MIXER_SOUT_SEL_IN				0xf68
#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER			0

/* VPPSYS1 */
#define MT8195_VPP1_HW_DCM_1ST_DIS0				0x150
#define MT8195_VPP1_HW_DCM_1ST_DIS1				0x160
#define MT8195_VPP1_HW_DCM_2ND_DIS0				0x1a0
#define MT8195_VPP1_HW_DCM_2ND_DIS1				0x1b0
#define MT8195_SVPP2_BUF_BF_RSZ_SWITCH				0xf48
#define MT8195_SVPP3_BUF_BF_RSZ_SWITCH				0xf74

/* VPPSYS1 HW DCM client*/
#define MT8195_SVPP1_MDP_RSZ					BIT(25)
#define MT8195_SVPP2_MDP_RSZ					BIT(4)
#define MT8195_SVPP3_MDP_RSZ					BIT(5)

static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
	{
		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
		MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
	}, {
		DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
		MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
	}, {
		DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
		MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
	}, {
		DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
		MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
	}, {
		DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
		MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
	}, {
		DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
		MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
	}, {
		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
		MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
	}, {
		DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
		MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
	}, {
		DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
		MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
	}, {
		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
		MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
	}, {
		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
		MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
	}, {
		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
		MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
	}, {
		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
		MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
	}, {
		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
	}, {
		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
	}, {
		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
	}, {
		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
	}, {
		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
	}, {
		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
	}, {
		DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
		MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
	}, {
		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
		MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
	}, {
		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
		MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
	}, {
		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
		MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
	}, {
		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
		MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
	}, {
		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
		MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
	}, {
		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
		MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
	}, {
		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
		MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
	}, {
		DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
		MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
	}, {
		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
		MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
	}, {
		DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
		MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
	}, {
		DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
		MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
	}, {
		DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
	}, {
		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
	}, {
		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
	}, {
		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
	}, {
		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
	}, {
		DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
	}, {
		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
	}, {
		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
	}, {
		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
	}, {
		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
	}, {
		DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
		MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
	}, {
		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
		MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
	}, {
		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
		MT8195_SOUT_DISP_DITHER0_TO_DSI0
	}, {
		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
	}, {
		DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
		MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
	}, {
		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
	}, {
		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
	}, {
		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
	}, {
		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
	}, {
		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
	}, {
		DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
		MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
	}, {
		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
		MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
	}, {
		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
		MT8195_SOUT_VPP_MERGE_TO_DSI1
	}, {
		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
		MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
	}, {
		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
		MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
	}, {
		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
		MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
	}, {
		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
		MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
	}, {
		DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
		MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
	}, {
		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
		MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
	}, {
		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
		MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
	}, {
		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
		MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
	}, {
		DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
		MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
	}, {
		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
		MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
	}, {
		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
		MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
	}, {
		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
		MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
	}, {
		DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
		MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
	}, {
		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
		MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
	}, {
		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
		MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
	}, {
		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
		MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
	}, {
		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
		MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
	}, {
		DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
		MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
	}
};

static const struct mtk_mmsys_routes mmsys_mt8195_vdo1_routing_table[] = {
	{
		DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
		MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
		MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
	}, {
		DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
		MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
		MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
	}, {
		DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
		MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
		MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
	}, {
		DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
		MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
		MT8195_SOUT_TO_MIXER_IN1_SEL
	}, {
		DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
		MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
		MT8195_SOUT_TO_MIXER_IN2_SEL
	}, {
		DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
		MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
		MT8195_SOUT_TO_MIXER_IN3_SEL
	}, {
		DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
		MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
		MT8195_SOUT_TO_MIXER_IN4_SEL
	}, {
		DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
		MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
		MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
	}, {
		DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
		MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
		MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
	}, {
		DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
		MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
		MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
	}, {
		DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
		MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
		MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
	}, {
		DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
		MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
		MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
	}, {
		DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
		MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
		MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
	}, {
		DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
		MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
		MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
	}, {
		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
		MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
		MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
	}, {
		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
		MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
		MT8195_MERGE4_SOUT_TO_DPI1_SEL
	}, {
		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
		MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
		MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
	}, {
		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
		MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
		MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
	}
};
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */