summaryrefslogtreecommitdiffstats
path: root/drivers/tty/serial/sc16is7xx.c
blob: dba25e70903c38edd50ad42d0a9da4857c42076f (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
// SPDX-License-Identifier: GPL-2.0+
/*
 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
 * Author: Jon Ringle <jringle@gridpoint.com>
 *
 *  Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/gpio/driver.h>
#include <linux/i2c.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/spi/spi.h>
#include <linux/uaccess.h>
#include <linux/units.h>
#include <uapi/linux/sched/types.h>

#define SC16IS7XX_NAME			"sc16is7xx"
#define SC16IS7XX_MAX_DEVS		8

/* SC16IS7XX register definitions */
#define SC16IS7XX_RHR_REG		(0x00) /* RX FIFO */
#define SC16IS7XX_THR_REG		(0x00) /* TX FIFO */
#define SC16IS7XX_IER_REG		(0x01) /* Interrupt enable */
#define SC16IS7XX_IIR_REG		(0x02) /* Interrupt Identification */
#define SC16IS7XX_FCR_REG		(0x02) /* FIFO control */
#define SC16IS7XX_LCR_REG		(0x03) /* Line Control */
#define SC16IS7XX_MCR_REG		(0x04) /* Modem Control */
#define SC16IS7XX_LSR_REG		(0x05) /* Line Status */
#define SC16IS7XX_MSR_REG		(0x06) /* Modem Status */
#define SC16IS7XX_SPR_REG		(0x07) /* Scratch Pad */
#define SC16IS7XX_TXLVL_REG		(0x08) /* TX FIFO level */
#define SC16IS7XX_RXLVL_REG		(0x09) /* RX FIFO level */
#define SC16IS7XX_IODIR_REG		(0x0a) /* I/O Direction
						* - only on 75x/76x
						*/
#define SC16IS7XX_IOSTATE_REG		(0x0b) /* I/O State
						* - only on 75x/76x
						*/
#define SC16IS7XX_IOINTENA_REG		(0x0c) /* I/O Interrupt Enable
						* - only on 75x/76x
						*/
#define SC16IS7XX_IOCONTROL_REG		(0x0e) /* I/O Control
						* - only on 75x/76x
						*/
#define SC16IS7XX_EFCR_REG		(0x0f) /* Extra Features Control */

/* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
#define SC16IS7XX_TCR_REG		(0x06) /* Transmit control */
#define SC16IS7XX_TLR_REG		(0x07) /* Trigger level */

/* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
#define SC16IS7XX_DLL_REG		(0x00) /* Divisor Latch Low */
#define SC16IS7XX_DLH_REG		(0x01) /* Divisor Latch High */

/* Enhanced Register set: Only if (LCR == 0xBF) */
#define SC16IS7XX_EFR_REG		(0x02) /* Enhanced Features */
#define SC16IS7XX_XON1_REG		(0x04) /* Xon1 word */
#define SC16IS7XX_XON2_REG		(0x05) /* Xon2 word */
#define SC16IS7XX_XOFF1_REG		(0x06) /* Xoff1 word */
#define SC16IS7XX_XOFF2_REG		(0x07) /* Xoff2 word */

/* IER register bits */
#define SC16IS7XX_IER_RDI_BIT		(1 << 0) /* Enable RX data interrupt */
#define SC16IS7XX_IER_THRI_BIT		(1 << 1) /* Enable TX holding register
						  * interrupt */
#define SC16IS7XX_IER_RLSI_BIT		(1 << 2) /* Enable RX line status
						  * interrupt */
#define SC16IS7XX_IER_MSI_BIT		(1 << 3) /* Enable Modem status
						  * interrupt */

/* IER register bits - write only if (EFR[4] == 1) */
#define SC16IS7XX_IER_SLEEP_BIT		(1 << 4) /* Enable Sleep mode */
#define SC16IS7XX_IER_XOFFI_BIT		(1 << 5) /* Enable Xoff interrupt */
#define SC16IS7XX_IER_RTSI_BIT		(1 << 6) /* Enable nRTS interrupt */
#define SC16IS7XX_IER_CTSI_BIT		(1 << 7) /* Enable nCTS interrupt */

/* FCR register bits */
#define SC16IS7XX_FCR_FIFO_BIT		(1 << 0) /* Enable FIFO */
#define SC16IS7XX_FCR_RXRESET_BIT	(1 << 1) /* Reset RX FIFO */
#define SC16IS7XX_FCR_TXRESET_BIT	(1 << 2) /* Reset TX FIFO */
#define SC16IS7XX_FCR_RXLVLL_BIT	(1 << 6) /* RX Trigger level LSB */
#define SC16IS7XX_FCR_RXLVLH_BIT	(1 << 7) /* RX Trigger level MSB */

/* FCR register bits - write only if (EFR[4] == 1) */
#define SC16IS7XX_FCR_TXLVLL_BIT	(1 << 4) /* TX Trigger level LSB */
#define SC16IS7XX_FCR_TXLVLH_BIT	(1 << 5) /* TX Trigger level MSB */

/* IIR register bits */
#define SC16IS7XX_IIR_NO_INT_BIT	(1 << 0) /* No interrupts pending */
#define SC16IS7XX_IIR_ID_MASK		0x3e     /* Mask for the interrupt ID */
#define SC16IS7XX_IIR_THRI_SRC		0x02     /* TX holding register empty */
#define SC16IS7XX_IIR_RDI_SRC		0x04     /* RX data interrupt */
#define SC16IS7XX_IIR_RLSE_SRC		0x06     /* RX line status error */
#define SC16IS7XX_IIR_RTOI_SRC		0x0c     /* RX time-out interrupt */
#define SC16IS7XX_IIR_MSI_SRC		0x00     /* Modem status interrupt
						  * - only on 75x/76x
						  */
#define SC16IS7XX_IIR_INPIN_SRC		0x30     /* Input pin change of state
						  * - only on 75x/76x
						  */
#define SC16IS7XX_IIR_XOFFI_SRC		0x10     /* Received Xoff */
#define SC16IS7XX_IIR_CTSRTS_SRC	0x20     /* nCTS,nRTS change of state
						  * from active (LOW)
						  * to inactive (HIGH)
						  */
/* LCR register bits */
#define SC16IS7XX_LCR_LENGTH0_BIT	(1 << 0) /* Word length bit 0 */
#define SC16IS7XX_LCR_LENGTH1_BIT	(1 << 1) /* Word length bit 1
						  *
						  * Word length bits table:
						  * 00 -> 5 bit words
						  * 01 -> 6 bit words
						  * 10 -> 7 bit words
						  * 11 -> 8 bit words
						  */
#define SC16IS7XX_LCR_STOPLEN_BIT	(1 << 2) /* STOP length bit
						  *
						  * STOP length bit table:
						  * 0 -> 1 stop bit
						  * 1 -> 1-1.5 stop bits if
						  *      word length is 5,
						  *      2 stop bits otherwise
						  */
#define SC16IS7XX_LCR_PARITY_BIT	(1 << 3) /* Parity bit enable */
#define SC16IS7XX_LCR_EVENPARITY_BIT	(1 << 4) /* Even parity bit enable */
#define SC16IS7XX_LCR_FORCEPARITY_BIT	(1 << 5) /* 9-bit multidrop parity */
#define SC16IS7XX_LCR_TXBREAK_BIT	(1 << 6) /* TX break enable */
#define SC16IS7XX_LCR_DLAB_BIT		(1 << 7) /* Divisor Latch enable */
#define SC16IS7XX_LCR_WORD_LEN_5	(0x00)
#define SC16IS7XX_LCR_WORD_LEN_6	(0x01)
#define SC16IS7XX_LCR_WORD_LEN_7	(0x02)
#define SC16IS7XX_LCR_WORD_LEN_8	(0x03)
#define SC16IS7XX_LCR_CONF_MODE_A	SC16IS7XX_LCR_DLAB_BIT /* Special
								* reg set */
#define SC16IS7XX_LCR_CONF_MODE_B	0xBF                   /* Enhanced
								* reg set */

/* MCR register bits */
#define SC16IS7XX_MCR_DTR_BIT		(1 << 0) /* DTR complement
						  * - only on 75x/76x
						  */
#define SC16IS7XX_MCR_RTS_BIT		(1 << 1) /* RTS complement */
#define SC16IS7XX_MCR_TCRTLR_BIT	(1 << 2) /* TCR/TLR register enable */
#define SC16IS7XX_MCR_LOOP_BIT		(1 << 4) /* Enable loopback test mode */
#define SC16IS7XX_MCR_XONANY_BIT	(1 << 5) /* Enable Xon Any
						  * - write enabled
						  * if (EFR[4] == 1)
						  */
#define SC16IS7XX_MCR_IRDA_BIT		(1 << 6) /* Enable IrDA mode
						  * - write enabled
						  * if (EFR[4] == 1)
						  */
#define SC16IS7XX_MCR_CLKSEL_BIT	(1 << 7) /* Divide clock by 4
						  * - write enabled
						  * if (EFR[4] == 1)
						  */

/* LSR register bits */
#define SC16IS7XX_LSR_DR_BIT		(1 << 0) /* Receiver data ready */
#define SC16IS7XX_LSR_OE_BIT		(1 << 1) /* Overrun Error */
#define SC16IS7XX_LSR_PE_BIT		(1 << 2) /* Parity Error */
#define SC16IS7XX_LSR_FE_BIT		(1 << 3) /* Frame Error */
#define SC16IS7XX_LSR_BI_BIT		(1 << 4) /* Break Interrupt */
#define SC16IS7XX_LSR_BRK_ERROR_MASK	0x1E     /* BI, FE, PE, OE bits */
#define SC16IS7XX_LSR_THRE_BIT		(1 << 5) /* TX holding register empty */
#define SC16IS7XX_LSR_TEMT_BIT		(1 << 6) /* Transmitter empty */
#define SC16IS7XX_LSR_FIFOE_BIT		(1 << 7) /* Fifo Error */

/* MSR register bits */
#define SC16IS7XX_MSR_DCTS_BIT		(1 << 0) /* Delta CTS Clear To Send */
#define SC16IS7XX_MSR_DDSR_BIT		(1 << 1) /* Delta DSR Data Set Ready
						  * or (IO4)
						  * - only on 75x/76x
						  */
#define SC16IS7XX_MSR_DRI_BIT		(1 << 2) /* Delta RI Ring Indicator
						  * or (IO7)
						  * - only on 75x/76x
						  */
#define SC16IS7XX_MSR_DCD_BIT		(1 << 3) /* Delta CD Carrier Detect
						  * or (IO6)
						  * - only on 75x/76x
						  */
#define SC16IS7XX_MSR_CTS_BIT		(1 << 4) /* CTS */
#define SC16IS7XX_MSR_DSR_BIT		(1 << 5) /* DSR (IO4)
						  * - only on 75x/76x
						  */
#define SC16IS7XX_MSR_RI_BIT		(1 << 6) /* RI (IO7)
						  * - only on 75x/76x
						  */
#define SC16IS7XX_MSR_CD_BIT		(1 << 7) /* CD (IO6)
						  * - only on 75x/76x
						  */
#define SC16IS7XX_MSR_DELTA_MASK	0x0F     /* Any of the delta bits! */

/*
 * TCR register bits
 * TCR trigger levels are available from 0 to 60 characters with a granularity
 * of four.
 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
 * no built-in hardware check to make sure this condition is met. Also, the TCR
 * must be programmed with this condition before auto RTS or software flow
 * control is enabled to avoid spurious operation of the device.
 */
#define SC16IS7XX_TCR_RX_HALT(words)	((((words) / 4) & 0x0f) << 0)
#define SC16IS7XX_TCR_RX_RESUME(words)	((((words) / 4) & 0x0f) << 4)

/*
 * TLR register bits
 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
 * trigger levels. Trigger levels from 4 characters to 60 characters are
 * available with a granularity of four.
 *
 * When the trigger level setting in TLR is zero, the SC16IS74x/75x/76x uses the
 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
 * the trigger level defined in FCR is discarded. This applies to both transmit
 * FIFO and receive FIFO trigger level setting.
 *
 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
 * default state, that is, '00'.
 */
#define SC16IS7XX_TLR_TX_TRIGGER(words)	((((words) / 4) & 0x0f) << 0)
#define SC16IS7XX_TLR_RX_TRIGGER(words)	((((words) / 4) & 0x0f) << 4)

/* IOControl register bits (Only 75x/76x) */
#define SC16IS7XX_IOCONTROL_LATCH_BIT	(1 << 0) /* Enable input latching */
#define SC16IS7XX_IOCONTROL_MODEM_A_BIT	(1 << 1) /* Enable GPIO[7:4] as modem A pins */
#define SC16IS7XX_IOCONTROL_MODEM_B_BIT	(1 << 2) /* Enable GPIO[3:0] as modem B pins */
#define SC16IS7XX_IOCONTROL_SRESET_BIT	(1 << 3) /* Software Reset */

/* EFCR register bits */
#define SC16IS7XX_EFCR_9BIT_MODE_BIT	(1 << 0) /* Enable 9-bit or Multidrop
						  * mode (RS485) */
#define SC16IS7XX_EFCR_RXDISABLE_BIT	(1 << 1) /* Disable receiver */
#define SC16IS7XX_EFCR_TXDISABLE_BIT	(1 << 2) /* Disable transmitter */
#define SC16IS7XX_EFCR_AUTO_RS485_BIT	(1 << 4) /* Auto RS485 RTS direction */
#define SC16IS7XX_EFCR_RTS_INVERT_BIT	(1 << 5) /* RTS output inversion */
#define SC16IS7XX_EFCR_IRDA_MODE_BIT	(1 << 7) /* IrDA mode
						  * 0 = rate upto 115.2 kbit/s
						  *   - Only 75x/76x
						  * 1 = rate upto 1.152 Mbit/s
						  *   - Only 76x
						  */

/* EFR register bits */
#define SC16IS7XX_EFR_AUTORTS_BIT	(1 << 6) /* Auto RTS flow ctrl enable */
#define SC16IS7XX_EFR_AUTOCTS_BIT	(1 << 7) /* Auto CTS flow ctrl enable */
#define SC16IS7XX_EFR_XOFF2_DETECT_BIT	(1 << 5) /* Enable Xoff2 detection */
#define SC16IS7XX_EFR_ENABLE_BIT	(1 << 4) /* Enable enhanced functions
						  * and writing to IER[7:4],
						  * FCR[5:4], MCR[7:5]
						  */
#define SC16IS7XX_EFR_SWFLOW3_BIT	(1 << 3) /* SWFLOW bit 3 */
#define SC16IS7XX_EFR_SWFLOW2_BIT	(1 << 2) /* SWFLOW bit 2
						  *
						  * SWFLOW bits 3 & 2 table:
						  * 00 -> no transmitter flow
						  *       control
						  * 01 -> transmitter generates
						  *       XON2 and XOFF2
						  * 10 -> transmitter generates
						  *       XON1 and XOFF1
						  * 11 -> transmitter generates
						  *       XON1, XON2, XOFF1 and
						  *       XOFF2
						  */
#define SC16IS7XX_EFR_SWFLOW1_BIT	(1 << 1) /* SWFLOW bit 2 */
#define SC16IS7XX_EFR_SWFLOW0_BIT	(1 << 0) /* SWFLOW bit 3
						  *
						  * SWFLOW bits 3 & 2 table:
						  * 00 -> no received flow
						  *       control
						  * 01 -> receiver compares
						  *       XON2 and XOFF2
						  * 10 -> receiver compares
						  *       XON1 and XOFF1
						  * 11 -> receiver compares
						  *       XON1, XON2, XOFF1 and
						  *       XOFF2
						  */
#define SC16IS7XX_EFR_FLOWCTRL_BITS	(SC16IS7XX_EFR_AUTORTS_BIT | \
					SC16IS7XX_EFR_AUTOCTS_BIT | \
					SC16IS7XX_EFR_XOFF2_DETECT_BIT | \
					SC16IS7XX_EFR_SWFLOW3_BIT | \
					SC16IS7XX_EFR_SWFLOW2_BIT | \
					SC16IS7XX_EFR_SWFLOW1_BIT | \
					SC16IS7XX_EFR_SWFLOW0_BIT)


/* Misc definitions */
#define SC16IS7XX_SPI_READ_BIT		BIT(7)
#define SC16IS7XX_FIFO_SIZE		(64)
#define SC16IS7XX_GPIOS_PER_BANK	4

struct sc16is7xx_devtype {
	char	name[10];
	int	nr_gpio;
	int	nr_uart;
};

#define SC16IS7XX_RECONF_MD		(1 << 0)
#define SC16IS7XX_RECONF_IER		(1 << 1)
#define SC16IS7XX_RECONF_RS485		(1 << 2)

struct sc16is7xx_one_config {
	unsigned int			flags;
	u8				ier_mask;
	u8				ier_val;
};

struct sc16is7xx_one {
	struct uart_port		port;
	struct regmap			*regmap;
	struct mutex			efr_lock; /* EFR registers access */
	struct kthread_work		tx_work;
	struct kthread_work		reg_work;
	struct kthread_delayed_work	ms_work;
	struct sc16is7xx_one_config	config;
	bool				irda_mode;
	unsigned int			old_mctrl;
};

struct sc16is7xx_port {
	const struct sc16is7xx_devtype	*devtype;
	struct clk			*clk;
#ifdef CONFIG_GPIOLIB
	struct gpio_chip		gpio;
	unsigned long			gpio_valid_mask;
#endif
	u8				mctrl_mask;
	unsigned char			buf[SC16IS7XX_FIFO_SIZE];
	struct kthread_worker		kworker;
	struct task_struct		*kworker_task;
	struct sc16is7xx_one		p[];
};

static unsigned long sc16is7xx_lines;

static struct uart_driver sc16is7xx_uart = {
	.owner		= THIS_MODULE,
	.dev_name	= "ttySC",
	.nr		= SC16IS7XX_MAX_DEVS,
};

static void sc16is7xx_ier_set(struct uart_port *port, u8 bit);
static void sc16is7xx_stop_tx(struct uart_port *port);

#define to_sc16is7xx_one(p,e)	((container_of((p), struct sc16is7xx_one, e)))

static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
{
	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
	unsigned int val = 0;

	regmap_read(one->regmap, reg, &val);

	return val;
}

static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
{
	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);

	regmap_write(one->regmap, reg, val);
}

static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen)
{
	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);

	regmap_noinc_read(one->regmap, SC16IS7XX_RHR_REG, s->buf, rxlen);
}

static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send)
{
	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);

	/*
	 * Don't send zero-length data, at least on SPI it confuses the chip
	 * delivering wrong TXLVL data.
	 */
	if (unlikely(!to_send))
		return;

	regmap_noinc_write(one->regmap, SC16IS7XX_THR_REG, s->buf, to_send);
}

static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
				  u8 mask, u8 val)
{
	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);

	regmap_update_bits(one->regmap, reg, mask, val);
}

static void sc16is7xx_power(struct uart_port *port, int on)
{
	sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
			      SC16IS7XX_IER_SLEEP_BIT,
			      on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
}

static const struct sc16is7xx_devtype sc16is74x_devtype = {
	.name		= "SC16IS74X",
	.nr_gpio	= 0,
	.nr_uart	= 1,
};

static const struct sc16is7xx_devtype sc16is750_devtype = {
	.name		= "SC16IS750",
	.nr_gpio	= 8,
	.nr_uart	= 1,
};

static const struct sc16is7xx_devtype sc16is752_devtype = {
	.name		= "SC16IS752",
	.nr_gpio	= 8,
	.nr_uart	= 2,
};

static const struct sc16is7xx_devtype sc16is760_devtype = {
	.name		= "SC16IS760",
	.nr_gpio	= 8,
	.nr_uart	= 1,
};

static const struct sc16is7xx_devtype sc16is762_devtype = {
	.name		= "SC16IS762",
	.nr_gpio	= 8,
	.nr_uart	= 2,
};

static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case SC16IS7XX_RHR_REG:
	case SC16IS7XX_IIR_REG:
	case SC16IS7XX_LSR_REG:
	case SC16IS7XX_MSR_REG:
	case SC16IS7XX_TXLVL_REG:
	case SC16IS7XX_RXLVL_REG:
	case SC16IS7XX_IOSTATE_REG:
	case SC16IS7XX_IOCONTROL_REG:
		return true;
	default:
		break;
	}

	return false;
}

static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case SC16IS7XX_RHR_REG:
		return true;
	default:
		break;
	}

	return false;
}

static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg)
{
	return reg == SC16IS7XX_RHR_REG;
}

static int sc16is7xx_set_baud(struct uart_port *port, int baud)
{
	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
	u8 lcr;
	u8 prescaler = 0;
	unsigned long clk = port->uartclk, div = clk / 16 / baud;

	if (div > 0xffff) {
		prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
		div /= 4;
	}

	/* In an amazing feat of design, the Enhanced Features Register shares
	 * the address of the Interrupt Identification Register, and is
	 * switched in by writing a magic value (0xbf) to the Line Control
	 * Register. Any interrupt firing during this time will see the EFR
	 * where it expects the IIR to be, leading to "Unexpected interrupt"
	 * messages.
	 *
	 * Prevent this possibility by claiming a mutex while accessing the
	 * EFR, and claiming the same mutex from within the interrupt handler.
	 * This is similar to disabling the interrupt, but that doesn't work
	 * because the bulk of the interrupt processing is run as a workqueue
	 * job in thread context.
	 */
	mutex_lock(&one->efr_lock);

	lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);

	/* Open the LCR divisors for configuration */
	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
			     SC16IS7XX_LCR_CONF_MODE_B);

	/* Enable enhanced features */
	regcache_cache_bypass(one->regmap, true);
	sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
			      SC16IS7XX_EFR_ENABLE_BIT,
			      SC16IS7XX_EFR_ENABLE_BIT);

	regcache_cache_bypass(one->regmap, false);

	/* Put LCR back to the normal mode */
	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);

	mutex_unlock(&one->efr_lock);

	sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
			      SC16IS7XX_MCR_CLKSEL_BIT,
			      prescaler);

	/* Open the LCR divisors for configuration */
	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
			     SC16IS7XX_LCR_CONF_MODE_A);

	/* Write the new divisor */
	regcache_cache_bypass(one->regmap, true);
	sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
	sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
	regcache_cache_bypass(one->regmap, false);

	/* Put LCR back to the normal mode */
	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);

	return DIV_ROUND_CLOSEST(clk / 16, div);
}

static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
				unsigned int iir)
{
	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
	unsigned int lsr = 0, bytes_read, i;
	bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
	u8 ch, flag;

	if (unlikely(rxlen >= sizeof(s->buf))) {
		dev_warn_ratelimited(port->dev,
				     "ttySC%i: Possible RX FIFO overrun: %d\n",
				     port->line, rxlen);
		port->icount.buf_overrun++;
		/* Ensure sanity of RX level */
		rxlen = sizeof(s->buf);
	}

	while (rxlen) {
		/* Only read lsr if there are possible errors in FIFO */
		if (read_lsr) {
			lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
			if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
				read_lsr = false; /* No errors left in FIFO */
		} else
			lsr = 0;

		if (read_lsr) {
			s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
			bytes_read = 1;
		} else {
			sc16is7xx_fifo_read(port, rxlen);
			bytes_read = rxlen;
		}

		lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;

		port->icount.rx++;
		flag = TTY_NORMAL;

		if (unlikely(lsr)) {
			if (lsr & SC16IS7XX_LSR_BI_BIT) {
				port->icount.brk++;
				if (uart_handle_break(port))
					continue;
			} else if (lsr & SC16IS7XX_LSR_PE_BIT)
				port->icount.parity++;
			else if (lsr & SC16IS7XX_LSR_FE_BIT)
				port->icount.frame++;
			else if (lsr & SC16IS7XX_LSR_OE_BIT)
				port->icount.overrun++;

			lsr &= port->read_status_mask;
			if (lsr & SC16IS7XX_LSR_BI_BIT)
				flag = TTY_BREAK;
			else if (lsr & SC16IS7XX_LSR_PE_BIT)
				flag = TTY_PARITY;
			else if (lsr & SC16IS7XX_LSR_FE_BIT)
				flag = TTY_FRAME;
			else if (lsr & SC16IS7XX_LSR_OE_BIT)
				flag = TTY_OVERRUN;
		}

		for (i = 0; i < bytes_read; ++i) {
			ch = s->buf[i];
			if (uart_handle_sysrq_char(port, ch))
				continue;

			if (lsr & port->ignore_status_mask)
				continue;

			uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
					 flag);
		}
		rxlen -= bytes_read;
	}

	tty_flip_buffer_push(&port->state->port);
}

static void sc16is7xx_handle_tx(struct uart_port *port)
{
	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
	struct circ_buf *xmit = &port->state->xmit;
	unsigned int txlen, to_send, i;
	unsigned long flags;

	if (unlikely(port->x_char)) {
		sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
		port->icount.tx++;
		port->x_char = 0;
		return;
	}

	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
		uart_port_lock_irqsave(port, &flags);
		sc16is7xx_stop_tx(port);
		uart_port_unlock_irqrestore(port, flags);
		return;
	}

	/* Get length of data pending in circular buffer */
	to_send = uart_circ_chars_pending(xmit);
	if (likely(to_send)) {
		/* Limit to size of TX FIFO */
		txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
		if (txlen > SC16IS7XX_FIFO_SIZE) {
			dev_err_ratelimited(port->dev,
				"chip reports %d free bytes in TX fifo, but it only has %d",
				txlen, SC16IS7XX_FIFO_SIZE);
			txlen = 0;
		}
		to_send = (to_send > txlen) ? txlen : to_send;

		/* Convert to linear buffer */
		for (i = 0; i < to_send; ++i) {
			s->buf[i] = xmit->buf[xmit->tail];
			uart_xmit_advance(port, 1);
		}

		sc16is7xx_fifo_write(port, to_send);
	}

	uart_port_lock_irqsave(port, &flags);
	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
		uart_write_wakeup(port);

	if (uart_circ_empty(xmit))
		sc16is7xx_stop_tx(port);
	else
		sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT);
	uart_port_unlock_irqrestore(port, flags);
}

static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port)
{
	u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
	unsigned int mctrl = 0;

	mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0;
	mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0;
	mctrl |= (msr & SC16IS7XX_MSR_CD_BIT)  ? TIOCM_CAR : 0;
	mctrl |= (msr & SC16IS7XX_MSR_RI_BIT)  ? TIOCM_RNG : 0;
	return mctrl;
}

static void sc16is7xx_update_mlines(struct sc16is7xx_one *one)
{
	struct uart_port *port = &one->port;
	unsigned long flags;
	unsigned int status, changed;

	lockdep_assert_held_once(&one->efr_lock);

	status = sc16is7xx_get_hwmctrl(port);
	changed = status ^ one->old_mctrl;

	if (changed == 0)
		return;

	one->old_mctrl = status;

	uart_port_lock_irqsave(port, &flags);
	if ((changed & TIOCM_RNG) && (status & TIOCM_RNG))
		port->icount.rng++;
	if (changed & TIOCM_DSR)
		port->icount.dsr++;
	if (changed & TIOCM_CAR)
		uart_handle_dcd_change(port, status & TIOCM_CAR);
	if (changed & TIOCM_CTS)
		uart_handle_cts_change(port, status & TIOCM_CTS);

	wake_up_interruptible(&port->state->port.delta_msr_wait);
	uart_port_unlock_irqrestore(port, flags);
}

static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
{
	bool rc = true;
	unsigned int iir, rxlen;
	struct uart_port *port = &s->p[portno].port;
	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);

	mutex_lock(&one->efr_lock);

	iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
	if (iir & SC16IS7XX_IIR_NO_INT_BIT) {
		rc = false;
		goto out_port_irq;
	}

	iir &= SC16IS7XX_IIR_ID_MASK;

	switch (iir) {
	case SC16IS7XX_IIR_RDI_SRC:
	case SC16IS7XX_IIR_RLSE_SRC:
	case SC16IS7XX_IIR_RTOI_SRC:
	case SC16IS7XX_IIR_XOFFI_SRC:
		rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);

		/*
		 * There is a silicon bug that makes the chip report a
		 * time-out interrupt but no data in the FIFO. This is
		 * described in errata section 18.1.4.
		 *
		 * When this happens, read one byte from the FIFO to
		 * clear the interrupt.
		 */
		if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen)
			rxlen = 1;

		if (rxlen)
			sc16is7xx_handle_rx(port, rxlen, iir);
		break;
		/* CTSRTS interrupt comes only when CTS goes inactive */
	case SC16IS7XX_IIR_CTSRTS_SRC:
	case SC16IS7XX_IIR_MSI_SRC:
		sc16is7xx_update_mlines(one);
		break;
	case SC16IS7XX_IIR_THRI_SRC:
		sc16is7xx_handle_tx(port);
		break;
	default:
		dev_err_ratelimited(port->dev,
				    "ttySC%i: Unexpected interrupt: %x",
				    port->line, iir);
		break;
	}

out_port_irq:
	mutex_unlock(&one->efr_lock);

	return rc;
}

static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
{
	bool keep_polling;

	struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;

	do {
		int i;

		keep_polling = false;

		for (i = 0; i < s->devtype->nr_uart; ++i)
			keep_polling |= sc16is7xx_port_irq(s, i);
	} while (keep_polling);

	return IRQ_HANDLED;
}

static void sc16is7xx_tx_proc(struct kthread_work *ws)
{
	struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);

	if ((port->rs485.flags & SER_RS485_ENABLED) &&
	    (port->rs485.delay_rts_before_send > 0))
		msleep(port->rs485.delay_rts_before_send);

	mutex_lock(&one->efr_lock);
	sc16is7xx_handle_tx(port);
	mutex_unlock(&one->efr_lock);
}

static void sc16is7xx_reconf_rs485(struct uart_port *port)
{
	const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
			 SC16IS7XX_EFCR_RTS_INVERT_BIT;
	u32 efcr = 0;
	struct serial_rs485 *rs485 = &port->rs485;
	unsigned long irqflags;

	uart_port_lock_irqsave(port, &irqflags);
	if (rs485->flags & SER_RS485_ENABLED) {
		efcr |=	SC16IS7XX_EFCR_AUTO_RS485_BIT;

		if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
			efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
	}
	uart_port_unlock_irqrestore(port, irqflags);

	sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
}

static void sc16is7xx_reg_proc(struct kthread_work *ws)
{
	struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
	struct sc16is7xx_one_config config;
	unsigned long irqflags;

	uart_port_lock_irqsave(&one->port, &irqflags);
	config = one->config;
	memset(&one->config, 0, sizeof(one->config));
	uart_port_unlock_irqrestore(&one->port, irqflags);

	if (config.flags & SC16IS7XX_RECONF_MD) {
		u8 mcr = 0;

		/* Device ignores RTS setting when hardware flow is enabled */
		if (one->port.mctrl & TIOCM_RTS)
			mcr |= SC16IS7XX_MCR_RTS_BIT;

		if (one->port.mctrl & TIOCM_DTR)
			mcr |= SC16IS7XX_MCR_DTR_BIT;

		if (one->port.mctrl & TIOCM_LOOP)
			mcr |= SC16IS7XX_MCR_LOOP_BIT;
		sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
				      SC16IS7XX_MCR_RTS_BIT |
				      SC16IS7XX_MCR_DTR_BIT |
				      SC16IS7XX_MCR_LOOP_BIT,
				      mcr);
	}

	if (config.flags & SC16IS7XX_RECONF_IER)
		sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
				      config.ier_mask, config.ier_val);

	if (config.flags & SC16IS7XX_RECONF_RS485)
		sc16is7xx_reconf_rs485(&one->port);
}

static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
{
	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);

	lockdep_assert_held_once(&port->lock);

	one->config.flags |= SC16IS7XX_RECONF_IER;
	one->config.ier_mask |= bit;
	one->config.ier_val &= ~bit;
	kthread_queue_work(&s->kworker, &one->reg_work);
}

static void sc16is7xx_ier_set(struct uart_port *port, u8 bit)
{
	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);

	lockdep_assert_held_once(&port->lock);

	one->config.flags |= SC16IS7XX_RECONF_IER;
	one->config.ier_mask |= bit;
	one->config.ier_val |= bit;
	kthread_queue_work(&s->kworker, &one->reg_work);
}

static void sc16is7xx_stop_tx(struct uart_port *port)
{
	sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
}

static void sc16is7xx_stop_rx(struct uart_port *port)
{
	sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
}

static void sc16is7xx_ms_proc(struct kthread_work *ws)
{
	struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work);
	struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev);

	if (one->port.state) {
		mutex_lock(&one->efr_lock);
		sc16is7xx_update_mlines(one);
		mutex_unlock(&one->efr_lock);

		kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ);
	}
}

static void sc16is7xx_enable_ms(struct uart_port *port)
{
	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);

	lockdep_assert_held_once(&port->lock);

	kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0);
}

static void sc16is7xx_start_tx(struct uart_port *port)
{
	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);

	kthread_queue_work(&s->kworker, &one->tx_work);
}

static void sc16is7xx_throttle(struct uart_port *port)
{
	unsigned long flags;

	/*
	 * Hardware flow control is enabled and thus the device ignores RTS
	 * value set in MCR register. Stop reading data from RX FIFO so the
	 * AutoRTS feature will de-activate RTS output.
	 */
	uart_port_lock_irqsave(port, &flags);
	sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
	uart_port_unlock_irqrestore(port, flags);
}

static void sc16is7xx_unthrottle(struct uart_port *port)
{
	unsigned long flags;

	uart_port_lock_irqsave(port, &flags);
	sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT);
	uart_port_unlock_irqrestore(port, flags);
}

static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
{
	unsigned int lsr;

	lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);

	return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
}

static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
{
	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);

	/* Called with port lock taken so we can only return cached value */
	return one->old_mctrl;
}

static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);

	one->config.flags |= SC16IS7XX_RECONF_MD;
	kthread_queue_work(&s->kworker, &one->reg_work);
}

static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
{
	sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
			      SC16IS7XX_LCR_TXBREAK_BIT,
			      break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
}

static void sc16is7xx_set_termios(struct uart_port *port,
				  struct ktermios *termios,
				  const struct ktermios *old)
{
	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
	unsigned int lcr, flow = 0;
	int baud;
	unsigned long flags;

	kthread_cancel_delayed_work_sync(&one->ms_work);

	/* Mask termios capabilities we don't support */
	termios->c_cflag &= ~CMSPAR;

	/* Word size */
	switch (termios->c_cflag & CSIZE) {
	case CS5:
		lcr = SC16IS7XX_LCR_WORD_LEN_5;
		break;
	case CS6:
		lcr = SC16IS7XX_LCR_WORD_LEN_6;
		break;
	case CS7:
		lcr = SC16IS7XX_LCR_WORD_LEN_7;
		break;
	case CS8:
		lcr = SC16IS7XX_LCR_WORD_LEN_8;
		break;
	default:
		lcr = SC16IS7XX_LCR_WORD_LEN_8;
		termios->c_cflag &= ~CSIZE;
		termios->c_cflag |= CS8;
		break;
	}

	/* Parity */
	if (termios->c_cflag & PARENB) {
		lcr |= SC16IS7XX_LCR_PARITY_BIT;
		if (!(termios->c_cflag & PARODD))
			lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
	}

	/* Stop bits */
	if (termios->c_cflag & CSTOPB)
		lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */

	/* Set read status mask */
	port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
	if (termios->c_iflag & INPCK)
		port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
					  SC16IS7XX_LSR_FE_BIT;
	if (termios->c_iflag & (BRKINT | PARMRK))
		port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;

	/* Set status ignore mask */
	port->ignore_status_mask = 0;
	if (termios->c_iflag & IGNBRK)
		port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
	if (!(termios->c_cflag & CREAD))
		port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;

	/* As above, claim the mutex while accessing the EFR. */
	mutex_lock(&one->efr_lock);

	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
			     SC16IS7XX_LCR_CONF_MODE_B);

	/* Configure flow control */
	regcache_cache_bypass(one->regmap, true);
	sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
	sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);

	port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
	if (termios->c_cflag & CRTSCTS) {
		flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
			SC16IS7XX_EFR_AUTORTS_BIT;
		port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
	}
	if (termios->c_iflag & IXON)
		flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
	if (termios->c_iflag & IXOFF)
		flow |= SC16IS7XX_EFR_SWFLOW1_BIT;

	sc16is7xx_port_update(port,
			      SC16IS7XX_EFR_REG,
			      SC16IS7XX_EFR_FLOWCTRL_BITS,
			      flow);
	regcache_cache_bypass(one->regmap, false);

	/* Update LCR register */
	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);

	mutex_unlock(&one->efr_lock);

	/* Get baud rate generator configuration */
	baud = uart_get_baud_rate(port, termios, old,
				  port->uartclk / 16 / 4 / 0xffff,
				  port->uartclk / 16);

	/* Setup baudrate generator */
	baud = sc16is7xx_set_baud(port, baud);

	uart_port_lock_irqsave(port, &flags);

	/* Update timeout according to new baud rate */
	uart_update_timeout(port, termios->c_cflag, baud);

	if (UART_ENABLE_MS(port, termios->c_cflag))
		sc16is7xx_enable_ms(port);

	uart_port_unlock_irqrestore(port, flags);
}

static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios,
				  struct serial_rs485 *rs485)
{
	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);

	if (rs485->flags & SER_RS485_ENABLED) {
		/*
		 * RTS signal is handled by HW, it's timing can't be influenced.
		 * However, it's sometimes useful to delay TX even without RTS
		 * control therefore we try to handle .delay_rts_before_send.
		 */
		if (rs485->delay_rts_after_send)
			return -EINVAL;
	}

	one->config.flags |= SC16IS7XX_RECONF_RS485;
	kthread_queue_work(&s->kworker, &one->reg_work);

	return 0;
}

static int sc16is7xx_startup(struct uart_port *port)
{
	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
	unsigned int val;
	unsigned long flags;

	sc16is7xx_power(port, 1);

	/* Reset FIFOs*/
	val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
	sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
	udelay(5);
	sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
			     SC16IS7XX_FCR_FIFO_BIT);

	/* Enable EFR */
	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
			     SC16IS7XX_LCR_CONF_MODE_B);

	regcache_cache_bypass(one->regmap, true);

	/* Enable write access to enhanced features and internal clock div */
	sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
			      SC16IS7XX_EFR_ENABLE_BIT,
			      SC16IS7XX_EFR_ENABLE_BIT);

	/* Enable TCR/TLR */
	sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
			      SC16IS7XX_MCR_TCRTLR_BIT,
			      SC16IS7XX_MCR_TCRTLR_BIT);

	/* Configure flow control levels */
	/* Flow control halt level 48, resume level 24 */
	sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
			     SC16IS7XX_TCR_RX_RESUME(24) |
			     SC16IS7XX_TCR_RX_HALT(48));

	regcache_cache_bypass(one->regmap, false);

	/* Now, initialize the UART */
	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);

	/* Enable IrDA mode if requested in DT */
	/* This bit must be written with LCR[7] = 0 */
	sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
			      SC16IS7XX_MCR_IRDA_BIT,
			      one->irda_mode ?
				SC16IS7XX_MCR_IRDA_BIT : 0);

	/* Enable the Rx and Tx FIFO */
	sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
			      SC16IS7XX_EFCR_RXDISABLE_BIT |
			      SC16IS7XX_EFCR_TXDISABLE_BIT,
			      0);

	/* Enable RX, CTS change and modem lines interrupts */
	val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT |
	      SC16IS7XX_IER_MSI_BIT;
	sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);

	/* Enable modem status polling */
	uart_port_lock_irqsave(port, &flags);
	sc16is7xx_enable_ms(port);
	uart_port_unlock_irqrestore(port, flags);

	return 0;
}

static void sc16is7xx_shutdown(struct uart_port *port)
{
	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);

	kthread_cancel_delayed_work_sync(&one->ms_work);

	/* Disable all interrupts */
	sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
	/* Disable TX/RX */
	sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
			      SC16IS7XX_EFCR_RXDISABLE_BIT |
			      SC16IS7XX_EFCR_TXDISABLE_BIT,
			      SC16IS7XX_EFCR_RXDISABLE_BIT |
			      SC16IS7XX_EFCR_TXDISABLE_BIT);

	sc16is7xx_power(port, 0);

	kthread_flush_worker(&s->kworker);
}

static const char *sc16is7xx_type(struct uart_port *port)
{
	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);

	return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
}

static int sc16is7xx_request_port(struct uart_port *port)
{
	/* Do nothing */
	return 0;
}

static void sc16is7xx_config_port(struct uart_port *port, int flags)
{
	if (flags & UART_CONFIG_TYPE)
		port->type = PORT_SC16IS7XX;
}

static int sc16is7xx_verify_port(struct uart_port *port,
				 struct serial_struct *s)
{
	if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
		return -EINVAL;
	if (s->irq != port->irq)
		return -EINVAL;

	return 0;
}

static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
			 unsigned int oldstate)
{
	sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
}

static void sc16is7xx_null_void(struct uart_port *port)
{
	/* Do nothing */
}

static const struct uart_ops sc16is7xx_ops = {
	.tx_empty	= sc16is7xx_tx_empty,
	.set_mctrl	= sc16is7xx_set_mctrl,
	.get_mctrl	= sc16is7xx_get_mctrl,
	.stop_tx	= sc16is7xx_stop_tx,
	.start_tx	= sc16is7xx_start_tx,
	.throttle	= sc16is7xx_throttle,
	.unthrottle	= sc16is7xx_unthrottle,
	.stop_rx	= sc16is7xx_stop_rx,
	.enable_ms	= sc16is7xx_enable_ms,
	.break_ctl	= sc16is7xx_break_ctl,
	.startup	= sc16is7xx_startup,
	.shutdown	= sc16is7xx_shutdown,
	.set_termios	= sc16is7xx_set_termios,
	.type		= sc16is7xx_type,
	.request_port	= sc16is7xx_request_port,
	.release_port	= sc16is7xx_null_void,
	.config_port	= sc16is7xx_config_port,
	.verify_port	= sc16is7xx_verify_port,
	.pm		= sc16is7xx_pm,
};

#ifdef CONFIG_GPIOLIB
static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	unsigned int val;
	struct sc16is7xx_port *s = gpiochip_get_data(chip);
	struct uart_port *port = &s->p[0].port;

	val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);

	return !!(val & BIT(offset));
}

static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct sc16is7xx_port *s = gpiochip_get_data(chip);
	struct uart_port *port = &s->p[0].port;

	sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
			      val ? BIT(offset) : 0);
}

static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
					  unsigned offset)
{
	struct sc16is7xx_port *s = gpiochip_get_data(chip);
	struct uart_port *port = &s->p[0].port;

	sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);

	return 0;
}

static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
					   unsigned offset, int val)
{
	struct sc16is7xx_port *s = gpiochip_get_data(chip);
	struct uart_port *port = &s->p[0].port;
	u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);

	if (val)
		state |= BIT(offset);
	else
		state &= ~BIT(offset);

	/*
	 * If we write IOSTATE first, and then IODIR, the output value is not
	 * transferred to the corresponding I/O pin.
	 * The datasheet states that each register bit will be transferred to
	 * the corresponding I/O pin programmed as output when writing to
	 * IOSTATE. Therefore, configure direction first with IODIR, and then
	 * set value after with IOSTATE.
	 */
	sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
			      BIT(offset));
	sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);

	return 0;
}

static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip,
					  unsigned long *valid_mask,
					  unsigned int ngpios)
{
	struct sc16is7xx_port *s = gpiochip_get_data(chip);

	*valid_mask = s->gpio_valid_mask;

	return 0;
}

static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s)
{
	struct device *dev = s->p[0].port.dev;

	if (!s->devtype->nr_gpio)
		return 0;

	switch (s->mctrl_mask) {
	case 0:
		s->gpio_valid_mask = GENMASK(7, 0);
		break;
	case SC16IS7XX_IOCONTROL_MODEM_A_BIT:
		s->gpio_valid_mask = GENMASK(3, 0);
		break;
	case SC16IS7XX_IOCONTROL_MODEM_B_BIT:
		s->gpio_valid_mask = GENMASK(7, 4);
		break;
	default:
		break;
	}

	if (s->gpio_valid_mask == 0)
		return 0;

	s->gpio.owner		 = THIS_MODULE;
	s->gpio.parent		 = dev;
	s->gpio.label		 = dev_name(dev);
	s->gpio.init_valid_mask	 = sc16is7xx_gpio_init_valid_mask;
	s->gpio.direction_input	 = sc16is7xx_gpio_direction_input;
	s->gpio.get		 = sc16is7xx_gpio_get;
	s->gpio.direction_output = sc16is7xx_gpio_direction_output;
	s->gpio.set		 = sc16is7xx_gpio_set;
	s->gpio.base		 = -1;
	s->gpio.ngpio		 = s->devtype->nr_gpio;
	s->gpio.can_sleep	 = 1;

	return gpiochip_add_data(&s->gpio, s);
}
#endif

static void sc16is7xx_setup_irda_ports(struct sc16is7xx_port *s)
{
	int i;
	int ret;
	int count;
	u32 irda_port[2];
	struct device *dev = s->p[0].port.dev;

	count = device_property_count_u32(dev, "irda-mode-ports");
	if (count < 0 || count > ARRAY_SIZE(irda_port))
		return;

	ret = device_property_read_u32_array(dev, "irda-mode-ports",
					     irda_port, count);
	if (ret)
		return;

	for (i = 0; i < count; i++) {
		if (irda_port[i] < s->devtype->nr_uart)
			s->p[irda_port[i]].irda_mode = true;
	}
}

/*
 * Configure ports designated to operate as modem control lines.
 */
static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s,
				       struct regmap *regmap)
{
	int i;
	int ret;
	int count;
	u32 mctrl_port[2];
	struct device *dev = s->p[0].port.dev;

	count = device_property_count_u32(dev, "nxp,modem-control-line-ports");
	if (count < 0 || count > ARRAY_SIZE(mctrl_port))
		return 0;

	ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports",
					     mctrl_port, count);
	if (ret)
		return ret;

	s->mctrl_mask = 0;

	for (i = 0; i < count; i++) {
		/* Use GPIO lines as modem control lines */
		if (mctrl_port[i] == 0)
			s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT;
		else if (mctrl_port[i] == 1)
			s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT;
	}

	if (s->mctrl_mask)
		regmap_update_bits(
			regmap,
			SC16IS7XX_IOCONTROL_REG,
			SC16IS7XX_IOCONTROL_MODEM_A_BIT |
			SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask);

	return 0;
}

static const struct serial_rs485 sc16is7xx_rs485_supported = {
	.flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND,
	.delay_rts_before_send = 1,
	.delay_rts_after_send = 1,	/* Not supported but keep returning -EINVAL */
};

static int sc16is7xx_probe(struct device *dev,
			   const struct sc16is7xx_devtype *devtype,
			   struct regmap *regmaps[], int irq)
{
	unsigned long freq = 0, *pfreq = dev_get_platdata(dev);
	unsigned int val;
	u32 uartclk = 0;
	int i, ret;
	struct sc16is7xx_port *s;

	for (i = 0; i < devtype->nr_uart; i++)
		if (IS_ERR(regmaps[i]))
			return PTR_ERR(regmaps[i]);

	/*
	 * This device does not have an identification register that would
	 * tell us if we are really connected to the correct device.
	 * The best we can do is to check if communication is at all possible.
	 *
	 * Note: regmap[0] is used in the probe function to access registers
	 * common to all channels/ports, as it is guaranteed to be present on
	 * all variants.
	 */
	ret = regmap_read(regmaps[0], SC16IS7XX_LSR_REG, &val);
	if (ret < 0)
		return -EPROBE_DEFER;

	/* Alloc port structure */
	s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL);
	if (!s) {
		dev_err(dev, "Error allocating port structure\n");
		return -ENOMEM;
	}

	/* Always ask for fixed clock rate from a property. */
	device_property_read_u32(dev, "clock-frequency", &uartclk);

	s->clk = devm_clk_get_optional(dev, NULL);
	if (IS_ERR(s->clk))
		return PTR_ERR(s->clk);

	ret = clk_prepare_enable(s->clk);
	if (ret)
		return ret;

	freq = clk_get_rate(s->clk);
	if (freq == 0) {
		if (uartclk)
			freq = uartclk;
		if (pfreq)
			freq = *pfreq;
		if (freq)
			dev_dbg(dev, "Clock frequency: %luHz\n", freq);
		else
			return -EINVAL;
	}

	s->devtype = devtype;
	dev_set_drvdata(dev, s);

	kthread_init_worker(&s->kworker);
	s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
				      "sc16is7xx");
	if (IS_ERR(s->kworker_task)) {
		ret = PTR_ERR(s->kworker_task);
		goto out_clk;
	}
	sched_set_fifo(s->kworker_task);

	/* reset device, purging any pending irq / data */
	regmap_write(regmaps[0], SC16IS7XX_IOCONTROL_REG,
		     SC16IS7XX_IOCONTROL_SRESET_BIT);

	for (i = 0; i < devtype->nr_uart; ++i) {
		s->p[i].port.line = find_first_zero_bit(&sc16is7xx_lines,
							SC16IS7XX_MAX_DEVS);
		if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) {
			ret = -ERANGE;
			goto out_ports;
		}

		/* Initialize port data */
		s->p[i].port.dev	= dev;
		s->p[i].port.irq	= irq;
		s->p[i].port.type	= PORT_SC16IS7XX;
		s->p[i].port.fifosize	= SC16IS7XX_FIFO_SIZE;
		s->p[i].port.flags	= UPF_FIXED_TYPE | UPF_LOW_LATENCY;
		s->p[i].port.iobase	= i;
		/*
		 * Use all ones as membase to make sure uart_configure_port() in
		 * serial_core.c does not abort for SPI/I2C devices where the
		 * membase address is not applicable.
		 */
		s->p[i].port.membase	= (void __iomem *)~0;
		s->p[i].port.iotype	= UPIO_PORT;
		s->p[i].port.uartclk	= freq;
		s->p[i].port.rs485_config = sc16is7xx_config_rs485;
		s->p[i].port.rs485_supported = sc16is7xx_rs485_supported;
		s->p[i].port.ops	= &sc16is7xx_ops;
		s->p[i].old_mctrl	= 0;
		s->p[i].regmap		= regmaps[i];

		mutex_init(&s->p[i].efr_lock);

		ret = uart_get_rs485_mode(&s->p[i].port);
		if (ret)
			goto out_ports;

		/* Disable all interrupts */
		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
		/* Disable TX/RX */
		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
				     SC16IS7XX_EFCR_RXDISABLE_BIT |
				     SC16IS7XX_EFCR_TXDISABLE_BIT);

		/* Initialize kthread work structs */
		kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
		kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
		kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc);

		/* Register port */
		ret = uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);
		if (ret)
			goto out_ports;

		set_bit(s->p[i].port.line, &sc16is7xx_lines);

		/* Enable EFR */
		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG,
				     SC16IS7XX_LCR_CONF_MODE_B);

		regcache_cache_bypass(regmaps[i], true);

		/* Enable write access to enhanced features */
		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG,
				     SC16IS7XX_EFR_ENABLE_BIT);

		regcache_cache_bypass(regmaps[i], false);

		/* Restore access to general registers */
		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00);

		/* Go to suspend mode */
		sc16is7xx_power(&s->p[i].port, 0);
	}

	sc16is7xx_setup_irda_ports(s);

	ret = sc16is7xx_setup_mctrl_ports(s, regmaps[0]);
	if (ret)
		goto out_ports;

#ifdef CONFIG_GPIOLIB
	ret = sc16is7xx_setup_gpio_chip(s);
	if (ret)
		goto out_ports;
#endif

	/*
	 * Setup interrupt. We first try to acquire the IRQ line as level IRQ.
	 * If that succeeds, we can allow sharing the interrupt as well.
	 * In case the interrupt controller doesn't support that, we fall
	 * back to a non-shared falling-edge trigger.
	 */
	ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
					IRQF_TRIGGER_LOW | IRQF_SHARED |
					IRQF_ONESHOT,
					dev_name(dev), s);
	if (!ret)
		return 0;

	ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
					IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
					dev_name(dev), s);
	if (!ret)
		return 0;

#ifdef CONFIG_GPIOLIB
	if (s->gpio_valid_mask)
		gpiochip_remove(&s->gpio);
#endif

out_ports:
	for (i = 0; i < devtype->nr_uart; i++)
		if (test_and_clear_bit(s->p[i].port.line, &sc16is7xx_lines))
			uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);

	kthread_stop(s->kworker_task);

out_clk:
	clk_disable_unprepare(s->clk);

	return ret;
}

static void sc16is7xx_remove(struct device *dev)
{
	struct sc16is7xx_port *s = dev_get_drvdata(dev);
	int i;

#ifdef CONFIG_GPIOLIB
	if (s->gpio_valid_mask)
		gpiochip_remove(&s->gpio);
#endif

	for (i = 0; i < s->devtype->nr_uart; i++) {
		kthread_cancel_delayed_work_sync(&s->p[i].ms_work);
		if (test_and_clear_bit(s->p[i].port.line, &sc16is7xx_lines))
			uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
		sc16is7xx_power(&s->p[i].port, 0);
	}

	kthread_flush_worker(&s->kworker);
	kthread_stop(s->kworker_task);

	clk_disable_unprepare(s->clk);
}

static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
	{ .compatible = "nxp,sc16is740",	.data = &sc16is74x_devtype, },
	{ .compatible = "nxp,sc16is741",	.data = &sc16is74x_devtype, },
	{ .compatible = "nxp,sc16is750",	.data = &sc16is750_devtype, },
	{ .compatible = "nxp,sc16is752",	.data = &sc16is752_devtype, },
	{ .compatible = "nxp,sc16is760",	.data = &sc16is760_devtype, },
	{ .compatible = "nxp,sc16is762",	.data = &sc16is762_devtype, },
	{ }
};
MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);

static struct regmap_config regcfg = {
	.reg_bits = 5,
	.pad_bits = 3,
	.val_bits = 8,
	.cache_type = REGCACHE_RBTREE,
	.volatile_reg = sc16is7xx_regmap_volatile,
	.precious_reg = sc16is7xx_regmap_precious,
	.writeable_noinc_reg = sc16is7xx_regmap_noinc,
	.readable_noinc_reg = sc16is7xx_regmap_noinc,
	.max_raw_read = SC16IS7XX_FIFO_SIZE,
	.max_raw_write = SC16IS7XX_FIFO_SIZE,
	.max_register = SC16IS7XX_EFCR_REG,
};

static const char *sc16is7xx_regmap_name(u8 port_id)
{
	switch (port_id) {
	case 0:	return "port0";
	case 1:	return "port1";
	default:
		WARN_ON(true);
		return NULL;
	}
}

static unsigned int sc16is7xx_regmap_port_mask(unsigned int port_id)
{
	/* CH1,CH0 are at bits 2:1. */
	return port_id << 1;
}

#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
static int sc16is7xx_spi_probe(struct spi_device *spi)
{
	const struct sc16is7xx_devtype *devtype;
	struct regmap *regmaps[2];
	unsigned int i;
	int ret;

	/* Setup SPI bus */
	spi->bits_per_word	= 8;
	/* For all variants, only mode 0 is supported */
	if ((spi->mode & SPI_MODE_X_MASK) != SPI_MODE_0)
		return dev_err_probe(&spi->dev, -EINVAL, "Unsupported SPI mode\n");

	spi->mode		= spi->mode ? : SPI_MODE_0;
	spi->max_speed_hz	= spi->max_speed_hz ? : 4 * HZ_PER_MHZ;
	ret = spi_setup(spi);
	if (ret)
		return ret;

	if (spi->dev.of_node) {
		devtype = device_get_match_data(&spi->dev);
		if (!devtype)
			return -ENODEV;
	} else {
		const struct spi_device_id *id_entry = spi_get_device_id(spi);

		devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
	}

	for (i = 0; i < devtype->nr_uart; i++) {
		regcfg.name = sc16is7xx_regmap_name(i);
		/*
		 * If read_flag_mask is 0, the regmap code sets it to a default
		 * of 0x80. Since we specify our own mask, we must add the READ
		 * bit ourselves:
		 */
		regcfg.read_flag_mask = sc16is7xx_regmap_port_mask(i) |
			SC16IS7XX_SPI_READ_BIT;
		regcfg.write_flag_mask = sc16is7xx_regmap_port_mask(i);
		regmaps[i] = devm_regmap_init_spi(spi, &regcfg);
	}

	return sc16is7xx_probe(&spi->dev, devtype, regmaps, spi->irq);
}

static void sc16is7xx_spi_remove(struct spi_device *spi)
{
	sc16is7xx_remove(&spi->dev);
}

static const struct spi_device_id sc16is7xx_spi_id_table[] = {
	{ "sc16is74x",	(kernel_ulong_t)&sc16is74x_devtype, },
	{ "sc16is740",	(kernel_ulong_t)&sc16is74x_devtype, },
	{ "sc16is741",	(kernel_ulong_t)&sc16is74x_devtype, },
	{ "sc16is750",	(kernel_ulong_t)&sc16is750_devtype, },
	{ "sc16is752",	(kernel_ulong_t)&sc16is752_devtype, },
	{ "sc16is760",	(kernel_ulong_t)&sc16is760_devtype, },
	{ "sc16is762",	(kernel_ulong_t)&sc16is762_devtype, },
	{ }
};

MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);

static struct spi_driver sc16is7xx_spi_uart_driver = {
	.driver = {
		.name		= SC16IS7XX_NAME,
		.of_match_table	= sc16is7xx_dt_ids,
	},
	.probe		= sc16is7xx_spi_probe,
	.remove		= sc16is7xx_spi_remove,
	.id_table	= sc16is7xx_spi_id_table,
};

MODULE_ALIAS("spi:sc16is7xx");
#endif

#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
static int sc16is7xx_i2c_probe(struct i2c_client *i2c)
{
	const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
	const struct sc16is7xx_devtype *devtype;
	struct regmap *regmaps[2];
	unsigned int i;

	if (i2c->dev.of_node) {
		devtype = device_get_match_data(&i2c->dev);
		if (!devtype)
			return -ENODEV;
	} else {
		devtype = (struct sc16is7xx_devtype *)id->driver_data;
	}

	for (i = 0; i < devtype->nr_uart; i++) {
		regcfg.name = sc16is7xx_regmap_name(i);
		regcfg.read_flag_mask = sc16is7xx_regmap_port_mask(i);
		regcfg.write_flag_mask = sc16is7xx_regmap_port_mask(i);
		regmaps[i] = devm_regmap_init_i2c(i2c, &regcfg);
	}

	return sc16is7xx_probe(&i2c->dev, devtype, regmaps, i2c->irq);
}

static void sc16is7xx_i2c_remove(struct i2c_client *client)
{
	sc16is7xx_remove(&client->dev);
}

static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
	{ "sc16is74x",	(kernel_ulong_t)&sc16is74x_devtype, },
	{ "sc16is740",	(kernel_ulong_t)&sc16is74x_devtype, },
	{ "sc16is741",	(kernel_ulong_t)&sc16is74x_devtype, },
	{ "sc16is750",	(kernel_ulong_t)&sc16is750_devtype, },
	{ "sc16is752",	(kernel_ulong_t)&sc16is752_devtype, },
	{ "sc16is760",	(kernel_ulong_t)&sc16is760_devtype, },
	{ "sc16is762",	(kernel_ulong_t)&sc16is762_devtype, },
	{ }
};
MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);

static struct i2c_driver sc16is7xx_i2c_uart_driver = {
	.driver = {
		.name		= SC16IS7XX_NAME,
		.of_match_table	= sc16is7xx_dt_ids,
	},
	.probe		= sc16is7xx_i2c_probe,
	.remove		= sc16is7xx_i2c_remove,
	.id_table	= sc16is7xx_i2c_id_table,
};

#endif

static int __init sc16is7xx_init(void)
{
	int ret;

	ret = uart_register_driver(&sc16is7xx_uart);
	if (ret) {
		pr_err("Registering UART driver failed\n");
		return ret;
	}

#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
	ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
	if (ret < 0) {
		pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
		goto err_i2c;
	}
#endif

#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
	ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
	if (ret < 0) {
		pr_err("failed to init sc16is7xx spi --> %d\n", ret);
		goto err_spi;
	}
#endif
	return ret;

#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
err_spi:
#endif
#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
	i2c_del_driver(&sc16is7xx_i2c_uart_driver);
err_i2c:
#endif
	uart_unregister_driver(&sc16is7xx_uart);
	return ret;
}
module_init(sc16is7xx_init);

static void __exit sc16is7xx_exit(void)
{
#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
	i2c_del_driver(&sc16is7xx_i2c_uart_driver);
#endif

#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
	spi_unregister_driver(&sc16is7xx_spi_uart_driver);
#endif
	uart_unregister_driver(&sc16is7xx_uart);
}
module_exit(sc16is7xx_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
MODULE_DESCRIPTION("SC16IS7XX serial driver");