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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
*/
#ifndef _DT_BINDINGS_CLK_SUN50I_A100_H_
#define _DT_BINDINGS_CLK_SUN50I_A100_H_
#define CLK_PLL_PERIPH0 3
#define CLK_CPUX 24
#define CLK_APB1 29
#define CLK_MBUS 31
#define CLK_DE 32
#define CLK_BUS_DE 33
#define CLK_G2D 34
#define CLK_BUS_G2D 35
#define CLK_GPU 36
#define CLK_BUS_GPU 37
#define CLK_CE 38
#define CLK_BUS_CE 39
#define CLK_VE 40
#define CLK_BUS_VE 41
#define CLK_BUS_DMA 42
#define CLK_BUS_MSGBOX 43
#define CLK_BUS_SPINLOCK 44
#define CLK_BUS_HSTIMER 45
#define CLK_AVS 46
#define CLK_BUS_DBG 47
#define CLK_BUS_PSI 48
#define CLK_BUS_PWM 49
#define CLK_BUS_IOMMU 50
#define CLK_MBUS_DMA 51
#define CLK_MBUS_VE 52
#define CLK_MBUS_CE 53
#define CLK_MBUS_NAND 54
#define CLK_MBUS_CSI 55
#define CLK_MBUS_ISP 56
#define CLK_MBUS_G2D 57
#define CLK_NAND0 59
#define CLK_NAND1 60
#define CLK_BUS_NAND 61
#define CLK_MMC0 62
#define CLK_MMC1 63
#define CLK_MMC2 64
#define CLK_MMC3 65
#define CLK_BUS_MMC0 66
#define CLK_BUS_MMC1 67
#define CLK_BUS_MMC2 68
#define CLK_BUS_UART0 69
#define CLK_BUS_UART1 70
#define CLK_BUS_UART2 71
#define CLK_BUS_UART3 72
#define CLK_BUS_UART4 73
#define CLK_BUS_I2C0 74
#define CLK_BUS_I2C1 75
#define CLK_BUS_I2C2 76
#define CLK_BUS_I2C3 77
#define CLK_SPI0 78
#define CLK_SPI1 79
#define CLK_SPI2 80
#define CLK_BUS_SPI0 81
#define CLK_BUS_SPI1 82
#define CLK_BUS_SPI2 83
#define CLK_EMAC_25M 84
#define CLK_BUS_EMAC 85
#define CLK_IR_RX 86
#define CLK_BUS_IR_RX 87
#define CLK_IR_TX 88
#define CLK_BUS_IR_TX 89
#define CLK_BUS_GPADC 90
#define CLK_BUS_THS 91
#define CLK_I2S0 92
#define CLK_I2S1 93
#define CLK_I2S2 94
#define CLK_I2S3 95
#define CLK_BUS_I2S0 96
#define CLK_BUS_I2S1 97
#define CLK_BUS_I2S2 98
#define CLK_BUS_I2S3 99
#define CLK_SPDIF 100
#define CLK_BUS_SPDIF 101
#define CLK_DMIC 102
#define CLK_BUS_DMIC 103
#define CLK_AUDIO_DAC 104
#define CLK_AUDIO_ADC 105
#define CLK_AUDIO_4X 106
#define CLK_BUS_AUDIO_CODEC 107
#define CLK_USB_OHCI0 108
#define CLK_USB_PHY0 109
#define CLK_USB_OHCI1 110
#define CLK_USB_PHY1 111
#define CLK_BUS_OHCI0 112
#define CLK_BUS_OHCI1 113
#define CLK_BUS_EHCI0 114
#define CLK_BUS_EHCI1 115
#define CLK_BUS_OTG 116
#define CLK_BUS_LRADC 117
#define CLK_BUS_DPSS_TOP0 118
#define CLK_BUS_DPSS_TOP1 119
#define CLK_MIPI_DSI 120
#define CLK_BUS_MIPI_DSI 121
#define CLK_TCON_LCD 122
#define CLK_BUS_TCON_LCD 123
#define CLK_LEDC 124
#define CLK_BUS_LEDC 125
#define CLK_CSI_TOP 126
#define CLK_CSI0_MCLK 127
#define CLK_CSI1_MCLK 128
#define CLK_BUS_CSI 129
#define CLK_CSI_ISP 130
#endif /* _DT_BINDINGS_CLK_SUN50I_A100_H_ */
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